![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
828 lines
22 KiB
C
828 lines
22 KiB
C
/*
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* PCI Express Hot Plug Controller Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <greg@kroah.com>, <dely.l.sy@intel.com>
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*
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/workqueue.h>
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#include <linux/proc_fs.h>
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#include <linux/pci.h>
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#include "../pci.h"
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#include "pciehp.h"
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#ifndef CONFIG_IA64
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#include "../../../arch/i386/pci/pci.h" /* horrible hack showing how processor dependant we are... */
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#endif
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int pciehp_configure_device (struct controller* ctrl, struct pci_func* func)
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{
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unsigned char bus;
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struct pci_bus *child;
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int num;
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if (func->pci_dev == NULL)
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func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
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/* Still NULL ? Well then scan for it ! */
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if (func->pci_dev == NULL) {
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dbg("%s: pci_dev still null. do pci_scan_slot\n", __FUNCTION__);
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num = pci_scan_slot(ctrl->pci_dev->subordinate, PCI_DEVFN(func->device, func->function));
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if (num)
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pci_bus_add_devices(ctrl->pci_dev->subordinate);
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func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
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if (func->pci_dev == NULL) {
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dbg("ERROR: pci_dev still null\n");
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return 0;
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}
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}
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if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
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pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
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child = pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
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pci_do_scan_bus(child);
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}
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return 0;
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}
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int pciehp_unconfigure_device(struct pci_func* func)
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{
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int rc = 0;
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int j;
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struct pci_bus *pbus;
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dbg("%s: bus/dev/func = %x/%x/%x\n", __FUNCTION__, func->bus,
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func->device, func->function);
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pbus = func->pci_dev->bus;
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for (j=0; j<8 ; j++) {
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struct pci_dev* temp = pci_find_slot(func->bus,
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(func->device << 3) | j);
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if (temp) {
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pci_remove_bus_device(temp);
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}
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}
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/*
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* Some PCI Express root ports require fixup after hot-plug operation.
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*/
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if (pcie_mch_quirk)
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pci_fixup_device(pci_fixup_final, pbus->self);
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return rc;
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}
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/*
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* pciehp_set_irq
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*
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* @bus_num: bus number of PCI device
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* @dev_num: device number of PCI device
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* @slot: pointer to u8 where slot number will be returned
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*/
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int pciehp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
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{
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#if defined(CONFIG_X86) && !defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_64)
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int rc;
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u16 temp_word;
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struct pci_dev fakedev;
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struct pci_bus fakebus;
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fakedev.devfn = dev_num << 3;
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fakedev.bus = &fakebus;
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fakebus.number = bus_num;
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dbg("%s: dev %d, bus %d, pin %d, num %d\n",
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__FUNCTION__, dev_num, bus_num, int_pin, irq_num);
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rc = pcibios_set_irq_routing(&fakedev, int_pin - 0x0a, irq_num);
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dbg("%s: rc %d\n", __FUNCTION__, rc);
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if (!rc)
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return !rc;
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/* set the Edge Level Control Register (ELCR) */
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temp_word = inb(0x4d0);
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temp_word |= inb(0x4d1) << 8;
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temp_word |= 0x01 << irq_num;
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/* This should only be for x86 as it sets the Edge Level Control Register */
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outb((u8) (temp_word & 0xFF), 0x4d0);
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outb((u8) ((temp_word & 0xFF00) >> 8), 0x4d1);
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#endif
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return 0;
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}
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/* More PCI configuration routines; this time centered around hotplug controller */
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/*
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* pciehp_save_config
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*
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* Reads configuration for all slots in a PCI bus and saves info.
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*
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* Note: For non-hot plug busses, the slot # saved is the device #
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*
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* returns 0 if success
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*/
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int pciehp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num)
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{
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int rc;
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u8 class_code;
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u8 header_type;
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u32 ID;
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u8 secondary_bus;
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struct pci_func *new_slot;
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int sub_bus;
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int max_functions;
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int function;
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u8 DevError;
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int device = 0;
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int cloop = 0;
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int stop_it;
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int index;
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int is_hot_plug = num_ctlr_slots || first_device_num;
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struct pci_bus lpci_bus, *pci_bus;
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int FirstSupported, LastSupported;
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dbg("%s: Enter\n", __FUNCTION__);
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memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
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pci_bus = &lpci_bus;
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dbg("%s: num_ctlr_slots = %d, first_device_num = %d\n", __FUNCTION__,
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num_ctlr_slots, first_device_num);
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/* Decide which slots are supported */
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if (is_hot_plug) {
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/*********************************
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* is_hot_plug is the slot mask
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*********************************/
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FirstSupported = first_device_num;
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LastSupported = FirstSupported + num_ctlr_slots - 1;
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} else {
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FirstSupported = 0;
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LastSupported = 0x1F;
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}
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dbg("FirstSupported = %d, LastSupported = %d\n", FirstSupported,
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LastSupported);
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/* Save PCI configuration space for all devices in supported slots */
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dbg("%s: pci_bus->number = %x\n", __FUNCTION__, pci_bus->number);
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pci_bus->number = busnumber;
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dbg("%s: bus = %x, dev = %x\n", __FUNCTION__, busnumber, device);
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for (device = FirstSupported; device <= LastSupported; device++) {
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ID = 0xFFFFFFFF;
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rc = pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0),
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PCI_VENDOR_ID, &ID);
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if (ID != 0xFFFFFFFF) { /* device in slot */
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dbg("%s: ID = %x\n", __FUNCTION__, ID);
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rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
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0x0B, &class_code);
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if (rc)
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return rc;
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rc = pci_bus_read_config_byte(pci_bus, PCI_DEVFN(device, 0),
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PCI_HEADER_TYPE, &header_type);
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if (rc)
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return rc;
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dbg("class_code = %x, header_type = %x\n", class_code, header_type);
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/* If multi-function device, set max_functions to 8 */
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if (header_type & 0x80)
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max_functions = 8;
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else
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max_functions = 1;
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function = 0;
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do {
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DevError = 0;
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dbg("%s: In do loop\n", __FUNCTION__);
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if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* P-P Bridge */
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/* Recurse the subordinate bus
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* get the subordinate bus number
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*/
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rc = pci_bus_read_config_byte(pci_bus,
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PCI_DEVFN(device, function),
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PCI_SECONDARY_BUS, &secondary_bus);
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if (rc) {
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return rc;
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} else {
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sub_bus = (int) secondary_bus;
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/* Save secondary bus cfg spc with this recursive call. */
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rc = pciehp_save_config(ctrl, sub_bus, 0, 0);
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if (rc)
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return rc;
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}
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}
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index = 0;
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new_slot = pciehp_slot_find(busnumber, device, index++);
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dbg("%s: new_slot = %p bus %x dev %x fun %x\n",
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__FUNCTION__, new_slot, busnumber, device, index-1);
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while (new_slot && (new_slot->function != (u8) function)) {
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new_slot = pciehp_slot_find(busnumber, device, index++);
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dbg("%s: while loop, new_slot = %p bus %x dev %x fun %x\n",
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__FUNCTION__, new_slot, busnumber, device, index-1);
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}
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if (!new_slot) {
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/* Setup slot structure. */
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new_slot = pciehp_slot_create(busnumber);
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dbg("%s: if, new_slot = %p bus %x dev %x fun %x\n",
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__FUNCTION__, new_slot, busnumber, device, function);
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if (new_slot == NULL)
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return(1);
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}
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new_slot->bus = (u8) busnumber;
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new_slot->device = (u8) device;
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new_slot->function = (u8) function;
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new_slot->is_a_board = 1;
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new_slot->switch_save = 0x10;
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/* In case of unsupported board */
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new_slot->status = DevError;
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new_slot->pci_dev = pci_find_slot(new_slot->bus,
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(new_slot->device << 3) | new_slot->function);
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dbg("new_slot->pci_dev = %p\n", new_slot->pci_dev);
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for (cloop = 0; cloop < 0x20; cloop++) {
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rc = pci_bus_read_config_dword(pci_bus,
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PCI_DEVFN(device, function),
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cloop << 2,
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(u32 *) &(new_slot->config_space [cloop]));
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/* dbg("new_slot->config_space[%x] = %x\n",
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cloop, new_slot->config_space[cloop]); */
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if (rc)
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return rc;
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}
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function++;
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stop_it = 0;
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/* this loop skips to the next present function
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* reading in Class Code and Header type.
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*/
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while ((function < max_functions)&&(!stop_it)) {
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dbg("%s: In while loop \n", __FUNCTION__);
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rc = pci_bus_read_config_dword(pci_bus,
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PCI_DEVFN(device, function),
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PCI_VENDOR_ID, &ID);
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if (ID == 0xFFFFFFFF) { /* nothing there. */
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function++;
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dbg("Nothing there\n");
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} else { /* Something there */
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rc = pci_bus_read_config_byte(pci_bus,
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PCI_DEVFN(device, function),
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0x0B, &class_code);
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if (rc)
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return rc;
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rc = pci_bus_read_config_byte(pci_bus,
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PCI_DEVFN(device, function),
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PCI_HEADER_TYPE, &header_type);
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if (rc)
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return rc;
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dbg("class_code = %x, header_type = %x\n", class_code, header_type);
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stop_it++;
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}
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}
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} while (function < max_functions);
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/* End of IF (device in slot?) */
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} else if (is_hot_plug) {
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/* Setup slot structure with entry for empty slot */
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new_slot = pciehp_slot_create(busnumber);
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if (new_slot == NULL) {
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return(1);
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}
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dbg("new_slot = %p, bus = %x, dev = %x, fun = %x\n", new_slot,
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new_slot->bus, new_slot->device, new_slot->function);
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new_slot->bus = (u8) busnumber;
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new_slot->device = (u8) device;
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new_slot->function = 0;
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new_slot->is_a_board = 0;
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new_slot->presence_save = 0;
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new_slot->switch_save = 0;
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}
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} /* End of FOR loop */
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dbg("%s: Exit\n", __FUNCTION__);
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return(0);
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}
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/*
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* pciehp_save_slot_config
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*
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* Saves configuration info for all PCI devices in a given slot
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* including subordinate busses.
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*
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* returns 0 if success
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*/
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int pciehp_save_slot_config(struct controller *ctrl, struct pci_func * new_slot)
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{
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int rc;
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u8 class_code;
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u8 header_type;
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u32 ID;
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u8 secondary_bus;
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int sub_bus;
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int max_functions;
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int function;
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int cloop = 0;
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int stop_it;
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struct pci_bus lpci_bus, *pci_bus;
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memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
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pci_bus = &lpci_bus;
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pci_bus->number = new_slot->bus;
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ID = 0xFFFFFFFF;
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pci_bus_read_config_dword(pci_bus, PCI_DEVFN(new_slot->device, 0),
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PCI_VENDOR_ID, &ID);
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if (ID != 0xFFFFFFFF) { /* device in slot */
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pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
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0x0B, &class_code);
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pci_bus_read_config_byte(pci_bus, PCI_DEVFN(new_slot->device, 0),
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PCI_HEADER_TYPE, &header_type);
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if (header_type & 0x80) /* Multi-function device */
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max_functions = 8;
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else
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max_functions = 1;
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function = 0;
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do {
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if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
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/* Recurse the subordinate bus */
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pci_bus_read_config_byte(pci_bus,
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PCI_DEVFN(new_slot->device, function),
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PCI_SECONDARY_BUS, &secondary_bus);
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sub_bus = (int) secondary_bus;
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/* Save the config headers for the secondary bus. */
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rc = pciehp_save_config(ctrl, sub_bus, 0, 0);
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if (rc)
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return rc;
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} /* End of IF */
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new_slot->status = 0;
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for (cloop = 0; cloop < 0x20; cloop++) {
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pci_bus_read_config_dword(pci_bus,
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PCI_DEVFN(new_slot->device, function),
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cloop << 2,
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(u32 *) &(new_slot->config_space [cloop]));
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}
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function++;
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stop_it = 0;
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/* this loop skips to the next present function
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* reading in the Class Code and the Header type.
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*/
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while ((function < max_functions) && (!stop_it)) {
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pci_bus_read_config_dword(pci_bus,
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PCI_DEVFN(new_slot->device, function),
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PCI_VENDOR_ID, &ID);
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if (ID == 0xFFFFFFFF) { /* nothing there. */
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function++;
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} else { /* Something there */
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pci_bus_read_config_byte(pci_bus,
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PCI_DEVFN(new_slot->device, function),
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0x0B, &class_code);
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pci_bus_read_config_byte(pci_bus,
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PCI_DEVFN(new_slot->device, function),
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PCI_HEADER_TYPE, &header_type);
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stop_it++;
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}
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}
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} while (function < max_functions);
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} /* End of IF (device in slot?) */
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else {
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return 2;
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}
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return 0;
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}
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/*
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* pciehp_save_used_resources
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*
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* Stores used resource information for existing boards. this is
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* for boards that were in the system when this driver was loaded.
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* this function is for hot plug ADD
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*
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* returns 0 if success
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* if disable == 1(DISABLE_CARD),
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* it loops for all functions of the slot and disables them.
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* else, it just get resources of the function and return.
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*/
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int pciehp_save_used_resources(struct controller *ctrl, struct pci_func *func, int disable)
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{
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u8 cloop;
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u8 header_type;
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u8 secondary_bus;
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u8 temp_byte;
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u16 command;
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u16 save_command;
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u16 w_base, w_length;
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u32 temp_register;
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u32 save_base;
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u32 base, length;
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u64 base64 = 0;
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int index = 0;
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unsigned int devfn;
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struct pci_resource *mem_node = NULL;
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struct pci_resource *p_mem_node = NULL;
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struct pci_resource *t_mem_node;
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struct pci_resource *io_node;
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struct pci_resource *bus_node;
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struct pci_bus lpci_bus, *pci_bus;
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memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));
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pci_bus = &lpci_bus;
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if (disable)
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func = pciehp_slot_find(func->bus, func->device, index++);
|
|
|
|
while ((func != NULL) && func->is_a_board) {
|
|
pci_bus->number = func->bus;
|
|
devfn = PCI_DEVFN(func->device, func->function);
|
|
|
|
/* Save the command register */
|
|
pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
|
|
|
|
if (disable) {
|
|
/* disable card */
|
|
command = 0x00;
|
|
pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
|
|
}
|
|
|
|
/* Check for Bridge */
|
|
pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
|
|
|
|
if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */
|
|
dbg("Save_used_res of PCI bridge b:d=0x%x:%x, sc=0x%x\n",
|
|
func->bus, func->device, save_command);
|
|
if (disable) {
|
|
/* Clear Bridge Control Register */
|
|
command = 0x00;
|
|
pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
|
|
}
|
|
|
|
pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
|
|
pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
|
|
|
|
bus_node = kmalloc(sizeof(struct pci_resource),
|
|
GFP_KERNEL);
|
|
if (!bus_node)
|
|
return -ENOMEM;
|
|
|
|
bus_node->base = (ulong)secondary_bus;
|
|
bus_node->length = (ulong)(temp_byte - secondary_bus + 1);
|
|
|
|
bus_node->next = func->bus_head;
|
|
func->bus_head = bus_node;
|
|
|
|
/* Save IO base and Limit registers */
|
|
pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &temp_byte);
|
|
base = temp_byte;
|
|
pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &temp_byte);
|
|
length = temp_byte;
|
|
|
|
if ((base <= length) && (!disable || (save_command & PCI_COMMAND_IO))) {
|
|
io_node = kmalloc(sizeof(struct pci_resource),
|
|
GFP_KERNEL);
|
|
if (!io_node)
|
|
return -ENOMEM;
|
|
|
|
io_node->base = (ulong)(base & PCI_IO_RANGE_MASK) << 8;
|
|
io_node->length = (ulong)(length - base + 0x10) << 8;
|
|
|
|
io_node->next = func->io_head;
|
|
func->io_head = io_node;
|
|
}
|
|
|
|
/* Save memory base and Limit registers */
|
|
pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
|
|
pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
|
|
|
|
if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
|
|
mem_node = kmalloc(sizeof(struct pci_resource),
|
|
GFP_KERNEL);
|
|
if (!mem_node)
|
|
return -ENOMEM;
|
|
|
|
mem_node->base = (ulong)w_base << 16;
|
|
mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
|
|
|
|
mem_node->next = func->mem_head;
|
|
func->mem_head = mem_node;
|
|
}
|
|
/* Save prefetchable memory base and Limit registers */
|
|
pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
|
|
pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
|
|
|
|
if ((w_base <= w_length) && (!disable || (save_command & PCI_COMMAND_MEMORY))) {
|
|
p_mem_node = kmalloc(sizeof(struct pci_resource),
|
|
GFP_KERNEL);
|
|
if (!p_mem_node)
|
|
return -ENOMEM;
|
|
|
|
p_mem_node->base = (ulong)w_base << 16;
|
|
p_mem_node->length = (ulong)(w_length - w_base + 0x10) << 16;
|
|
|
|
p_mem_node->next = func->p_mem_head;
|
|
func->p_mem_head = p_mem_node;
|
|
}
|
|
} else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
|
|
dbg("Save_used_res of PCI adapter b:d=0x%x:%x, sc=0x%x\n",
|
|
func->bus, func->device, save_command);
|
|
|
|
/* Figure out IO and memory base lengths */
|
|
for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {
|
|
pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
|
|
|
|
temp_register = 0xFFFFFFFF;
|
|
pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
|
|
pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
|
|
|
|
if (!disable)
|
|
pci_bus_write_config_dword(pci_bus, devfn, cloop, save_base);
|
|
|
|
if (!temp_register)
|
|
continue;
|
|
|
|
base = temp_register;
|
|
|
|
if ((base & PCI_BASE_ADDRESS_SPACE_IO) &&
|
|
(!disable || (save_command & PCI_COMMAND_IO))) {
|
|
/* IO base */
|
|
/* set temp_register = amount of IO space requested */
|
|
base = base & 0xFFFFFFFCL;
|
|
base = (~base) + 1;
|
|
|
|
io_node = kmalloc(sizeof (struct pci_resource),
|
|
GFP_KERNEL);
|
|
if (!io_node)
|
|
return -ENOMEM;
|
|
|
|
io_node->base = (ulong)save_base & PCI_BASE_ADDRESS_IO_MASK;
|
|
io_node->length = (ulong)base;
|
|
dbg("sur adapter: IO bar=0x%x(length=0x%x)\n",
|
|
io_node->base, io_node->length);
|
|
|
|
io_node->next = func->io_head;
|
|
func->io_head = io_node;
|
|
} else { /* map Memory */
|
|
int prefetchable = 1;
|
|
/* struct pci_resources **res_node; */
|
|
char *res_type_str = "PMEM";
|
|
u32 temp_register2;
|
|
|
|
t_mem_node = kmalloc(sizeof (struct pci_resource),
|
|
GFP_KERNEL);
|
|
if (!t_mem_node)
|
|
return -ENOMEM;
|
|
|
|
if (!(base & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
|
|
(!disable || (save_command & PCI_COMMAND_MEMORY))) {
|
|
prefetchable = 0;
|
|
mem_node = t_mem_node;
|
|
res_type_str++;
|
|
} else
|
|
p_mem_node = t_mem_node;
|
|
|
|
base = base & 0xFFFFFFF0L;
|
|
base = (~base) + 1;
|
|
|
|
switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
|
|
case PCI_BASE_ADDRESS_MEM_TYPE_32:
|
|
if (prefetchable) {
|
|
p_mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
|
|
p_mem_node->length = (ulong)base;
|
|
dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
|
|
res_type_str,
|
|
p_mem_node->base,
|
|
p_mem_node->length);
|
|
|
|
p_mem_node->next = func->p_mem_head;
|
|
func->p_mem_head = p_mem_node;
|
|
} else {
|
|
mem_node->base = (ulong)save_base & PCI_BASE_ADDRESS_MEM_MASK;
|
|
mem_node->length = (ulong)base;
|
|
dbg("sur adapter: 32 %s bar=0x%x(length=0x%x)\n",
|
|
res_type_str,
|
|
mem_node->base,
|
|
mem_node->length);
|
|
|
|
mem_node->next = func->mem_head;
|
|
func->mem_head = mem_node;
|
|
}
|
|
break;
|
|
case PCI_BASE_ADDRESS_MEM_TYPE_64:
|
|
pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);
|
|
base64 = temp_register2;
|
|
base64 = (base64 << 32) | save_base;
|
|
|
|
if (temp_register2) {
|
|
dbg("sur adapter: 64 %s high dword of base64(0x%x:%x) masked to 0\n",
|
|
res_type_str, temp_register2, (u32)base64);
|
|
base64 &= 0x00000000FFFFFFFFL;
|
|
}
|
|
|
|
if (prefetchable) {
|
|
p_mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
|
|
p_mem_node->length = base;
|
|
dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
|
|
res_type_str,
|
|
p_mem_node->base,
|
|
p_mem_node->length);
|
|
|
|
p_mem_node->next = func->p_mem_head;
|
|
func->p_mem_head = p_mem_node;
|
|
} else {
|
|
mem_node->base = base64 & PCI_BASE_ADDRESS_MEM_MASK;
|
|
mem_node->length = base;
|
|
dbg("sur adapter: 64 %s base=0x%x(len=0x%x)\n",
|
|
res_type_str,
|
|
mem_node->base,
|
|
mem_node->length);
|
|
|
|
mem_node->next = func->mem_head;
|
|
func->mem_head = mem_node;
|
|
}
|
|
cloop += 4;
|
|
break;
|
|
default:
|
|
dbg("asur: reserved BAR type=0x%x\n",
|
|
temp_register);
|
|
break;
|
|
}
|
|
}
|
|
} /* End of base register loop */
|
|
} else { /* Some other unknown header type */
|
|
dbg("Save_used_res of PCI unknown type b:d=0x%x:%x. skip.\n",
|
|
func->bus, func->device);
|
|
}
|
|
|
|
/* find the next device in this slot */
|
|
if (!disable)
|
|
break;
|
|
func = pciehp_slot_find(func->bus, func->device, index++);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**
|
|
* kfree_resource_list: release memory of all list members
|
|
* @res: resource list to free
|
|
*/
|
|
static inline void
|
|
return_resource_list(struct pci_resource **func, struct pci_resource **res)
|
|
{
|
|
struct pci_resource *node;
|
|
struct pci_resource *t_node;
|
|
|
|
node = *func;
|
|
*func = NULL;
|
|
while (node) {
|
|
t_node = node->next;
|
|
return_resource(res, node);
|
|
node = t_node;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* pciehp_return_board_resources
|
|
*
|
|
* this routine returns all resources allocated to a board to
|
|
* the available pool.
|
|
*
|
|
* returns 0 if success
|
|
*/
|
|
int pciehp_return_board_resources(struct pci_func * func,
|
|
struct resource_lists * resources)
|
|
{
|
|
int rc;
|
|
|
|
dbg("%s\n", __FUNCTION__);
|
|
|
|
if (!func)
|
|
return 1;
|
|
|
|
return_resource_list(&(func->io_head),&(resources->io_head));
|
|
return_resource_list(&(func->mem_head),&(resources->mem_head));
|
|
return_resource_list(&(func->p_mem_head),&(resources->p_mem_head));
|
|
return_resource_list(&(func->bus_head),&(resources->bus_head));
|
|
|
|
rc = pciehp_resource_sort_and_combine(&(resources->mem_head));
|
|
rc |= pciehp_resource_sort_and_combine(&(resources->p_mem_head));
|
|
rc |= pciehp_resource_sort_and_combine(&(resources->io_head));
|
|
rc |= pciehp_resource_sort_and_combine(&(resources->bus_head));
|
|
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* kfree_resource_list: release memory of all list members
|
|
* @res: resource list to free
|
|
*/
|
|
static inline void
|
|
kfree_resource_list(struct pci_resource **r)
|
|
{
|
|
struct pci_resource *res, *tres;
|
|
|
|
res = *r;
|
|
*r = NULL;
|
|
|
|
while (res) {
|
|
tres = res;
|
|
res = res->next;
|
|
kfree(tres);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* pciehp_destroy_resource_list: put node back in the resource list
|
|
* @resources: list to put nodes back
|
|
*/
|
|
void pciehp_destroy_resource_list(struct resource_lists * resources)
|
|
{
|
|
kfree_resource_list(&(resources->io_head));
|
|
kfree_resource_list(&(resources->mem_head));
|
|
kfree_resource_list(&(resources->p_mem_head));
|
|
kfree_resource_list(&(resources->bus_head));
|
|
}
|
|
|
|
/**
|
|
* pciehp_destroy_board_resources: put node back in the resource list
|
|
* @resources: list to put nodes back
|
|
*/
|
|
void pciehp_destroy_board_resources(struct pci_func * func)
|
|
{
|
|
kfree_resource_list(&(func->io_head));
|
|
kfree_resource_list(&(func->mem_head));
|
|
kfree_resource_list(&(func->p_mem_head));
|
|
kfree_resource_list(&(func->bus_head));
|
|
}
|