![Jörn Engel](/assets/img/avatar_default.png)
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
344 lines
10 KiB
C
344 lines
10 KiB
C
/*
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* linux/drivers/serial/cpm_uart_cpm2.c
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*
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* Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
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*
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* Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
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* Pantelis Antoniou (panto@intracom.gr) (CPM1)
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*
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* Copyright (C) 2004 Freescale Semiconductor, Inc.
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* (C) 2004 Intracom, S.A.
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* (C) 2006 MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/tty.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/bootmem.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <linux/serial_core.h>
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#include <linux/kernel.h>
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#include "cpm_uart.h"
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/**************************************************************/
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void cpm_line_cr_cmd(int line, int cmd)
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{
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volatile cpm_cpm2_t *cp = cpmp;
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ulong val;
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switch (line) {
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case UART_SMC1:
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val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
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cmd) | CPM_CR_FLG;
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break;
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case UART_SMC2:
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val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
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cmd) | CPM_CR_FLG;
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break;
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case UART_SCC1:
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val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
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cmd) | CPM_CR_FLG;
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break;
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case UART_SCC2:
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val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
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cmd) | CPM_CR_FLG;
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break;
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case UART_SCC3:
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val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
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cmd) | CPM_CR_FLG;
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break;
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case UART_SCC4:
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val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
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cmd) | CPM_CR_FLG;
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break;
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default:
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return;
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}
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cp->cp_cpcr = val;
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while (cp->cp_cpcr & CPM_CR_FLG) ;
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}
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void smc1_lineif(struct uart_cpm_port *pinfo)
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{
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volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
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/* SMC1 is only on port D */
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io->iop_ppard |= 0x00c00000;
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io->iop_pdird |= 0x00400000;
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io->iop_pdird &= ~0x00800000;
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io->iop_psord &= ~0x00c00000;
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/* Wire BRG1 to SMC1 */
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cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
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pinfo->brg = 1;
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}
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void smc2_lineif(struct uart_cpm_port *pinfo)
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{
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volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
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/* SMC2 is only on port A */
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io->iop_ppara |= 0x00c00000;
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io->iop_pdira |= 0x00400000;
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io->iop_pdira &= ~0x00800000;
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io->iop_psora &= ~0x00c00000;
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/* Wire BRG2 to SMC2 */
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cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
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pinfo->brg = 2;
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}
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void scc1_lineif(struct uart_cpm_port *pinfo)
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{
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volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
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/* Use Port D for SCC1 instead of other functions. */
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io->iop_ppard |= 0x00000003;
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io->iop_psord &= ~0x00000001; /* Rx */
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io->iop_psord |= 0x00000002; /* Tx */
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io->iop_pdird &= ~0x00000001; /* Rx */
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io->iop_pdird |= 0x00000002; /* Tx */
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/* Wire BRG1 to SCC1 */
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cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
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cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
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pinfo->brg = 1;
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}
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void scc2_lineif(struct uart_cpm_port *pinfo)
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{
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/*
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* STx GP3 uses the SCC2 secondary option pin assignment
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* which this driver doesn't account for in the static
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* pin assignments. This kind of board specific info
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* really has to get out of the driver so boards can
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* be supported in a sane fashion.
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*/
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#ifndef CONFIG_STX_GP3
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volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
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io->iop_pparb |= 0x008b0000;
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io->iop_pdirb |= 0x00880000;
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io->iop_psorb |= 0x00880000;
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io->iop_pdirb &= ~0x00030000;
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io->iop_psorb &= ~0x00030000;
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#endif
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cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
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cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
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pinfo->brg = 2;
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}
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void scc3_lineif(struct uart_cpm_port *pinfo)
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{
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volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
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io->iop_pparb |= 0x008b0000;
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io->iop_pdirb |= 0x00880000;
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io->iop_psorb |= 0x00880000;
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io->iop_pdirb &= ~0x00030000;
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io->iop_psorb &= ~0x00030000;
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cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
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cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
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pinfo->brg = 3;
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}
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void scc4_lineif(struct uart_cpm_port *pinfo)
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{
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volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
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io->iop_ppard |= 0x00000600;
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io->iop_psord &= ~0x00000600; /* Tx/Rx */
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io->iop_pdird &= ~0x00000200; /* Rx */
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io->iop_pdird |= 0x00000400; /* Tx */
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cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
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cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
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pinfo->brg = 4;
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}
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/*
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* Allocate DP-Ram and memory buffers. We need to allocate a transmit and
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* receive buffer descriptors from dual port ram, and a character
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* buffer area from host mem. If we are allocating for the console we need
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* to do it from bootmem
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*/
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int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
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{
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int dpmemsz, memsz;
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u8 *dp_mem;
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uint dp_offset;
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u8 *mem_addr;
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dma_addr_t dma_addr = 0;
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pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
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dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
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dp_offset = cpm_dpalloc(dpmemsz, 8);
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if (IS_DPERR(dp_offset)) {
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printk(KERN_ERR
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"cpm_uart_cpm.c: could not allocate buffer descriptors\n");
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return -ENOMEM;
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}
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dp_mem = cpm_dpram_addr(dp_offset);
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memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
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L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
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if (is_con) {
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mem_addr = alloc_bootmem(memsz);
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dma_addr = virt_to_bus(mem_addr);
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}
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else
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mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
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GFP_KERNEL);
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if (mem_addr == NULL) {
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cpm_dpfree(dp_offset);
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printk(KERN_ERR
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"cpm_uart_cpm.c: could not allocate coherent memory\n");
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return -ENOMEM;
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}
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pinfo->dp_addr = dp_offset;
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pinfo->mem_addr = mem_addr;
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pinfo->dma_addr = dma_addr;
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pinfo->mem_size = memsz;
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pinfo->rx_buf = mem_addr;
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pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
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* pinfo->rx_fifosize);
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pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
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pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
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return 0;
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}
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void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
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{
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dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
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pinfo->rx_fifosize) +
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L1_CACHE_ALIGN(pinfo->tx_nrfifos *
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pinfo->tx_fifosize), pinfo->mem_addr,
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pinfo->dma_addr);
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cpm_dpfree(pinfo->dp_addr);
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}
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/* Setup any dynamic params in the uart desc */
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int cpm_uart_init_portdesc(void)
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{
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pr_debug("CPM uart[-]:init portdesc\n");
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cpm_uart_nr = 0;
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#ifdef CONFIG_SERIAL_CPM_SMC1
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cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
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cpm_uart_ports[UART_SMC1].smcup =
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(smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
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*(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
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cpm_uart_ports[UART_SMC1].port.mapbase =
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(unsigned long)&cpm2_immr->im_smc[0];
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cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
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cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
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cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC2
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cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
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cpm_uart_ports[UART_SMC2].smcup =
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(smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
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*(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2;
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cpm_uart_ports[UART_SMC2].port.mapbase =
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(unsigned long)&cpm2_immr->im_smc[1];
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cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
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cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
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cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC1
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cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
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cpm_uart_ports[UART_SCC1].sccup =
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(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
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cpm_uart_ports[UART_SCC1].port.mapbase =
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(unsigned long)&cpm2_immr->im_scc[0];
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cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
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~(UART_SCCM_TX | UART_SCCM_RX);
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cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
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cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC2
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cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
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cpm_uart_ports[UART_SCC2].sccup =
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(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
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cpm_uart_ports[UART_SCC2].port.mapbase =
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(unsigned long)&cpm2_immr->im_scc[1];
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cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
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~(UART_SCCM_TX | UART_SCCM_RX);
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cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
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cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC3
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cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
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cpm_uart_ports[UART_SCC3].sccup =
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(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
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cpm_uart_ports[UART_SCC3].port.mapbase =
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(unsigned long)&cpm2_immr->im_scc[2];
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cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
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~(UART_SCCM_TX | UART_SCCM_RX);
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cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
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cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SCC4
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cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
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cpm_uart_ports[UART_SCC4].sccup =
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(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
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cpm_uart_ports[UART_SCC4].port.mapbase =
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(unsigned long)&cpm2_immr->im_scc[3];
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cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
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~(UART_SCCM_TX | UART_SCCM_RX);
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cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
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cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
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#endif
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return 0;
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}
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