![Dan Williams](/assets/img/avatar_default.png)
* Rename 'next' to 'dep' * Move the channel switch check inside the loop to simplify termination Acked-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
644 lines
16 KiB
C
644 lines
16 KiB
C
/*
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* core routines for the asynchronous memory transfer/transform api
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*
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* Copyright © 2006, Intel Corporation.
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*
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* Dan Williams <dan.j.williams@intel.com>
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*
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* with architecture considerations by:
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* Neil Brown <neilb@suse.de>
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* Jeff Garzik <jeff@garzik.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/rculist.h>
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#include <linux/kernel.h>
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#include <linux/async_tx.h>
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#ifdef CONFIG_DMA_ENGINE
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static enum dma_state_client
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dma_channel_add_remove(struct dma_client *client,
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struct dma_chan *chan, enum dma_state state);
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static struct dma_client async_tx_dma = {
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.event_callback = dma_channel_add_remove,
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/* .cap_mask == 0 defaults to all channels */
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};
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/**
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* dma_cap_mask_all - enable iteration over all operation types
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*/
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static dma_cap_mask_t dma_cap_mask_all;
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/**
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* chan_ref_percpu - tracks channel allocations per core/opertion
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*/
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struct chan_ref_percpu {
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struct dma_chan_ref *ref;
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};
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static int channel_table_initialized;
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static struct chan_ref_percpu *channel_table[DMA_TX_TYPE_END];
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/**
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* async_tx_lock - protect modification of async_tx_master_list and serialize
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* rebalance operations
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*/
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static spinlock_t async_tx_lock;
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static LIST_HEAD(async_tx_master_list);
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/* async_tx_issue_pending_all - start all transactions on all channels */
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void async_tx_issue_pending_all(void)
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{
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struct dma_chan_ref *ref;
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rcu_read_lock();
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list_for_each_entry_rcu(ref, &async_tx_master_list, node)
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ref->chan->device->device_issue_pending(ref->chan);
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rcu_read_unlock();
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}
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EXPORT_SYMBOL_GPL(async_tx_issue_pending_all);
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/* dma_wait_for_async_tx - spin wait for a transcation to complete
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* @tx: transaction to wait on
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*/
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enum dma_status
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dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
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{
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enum dma_status status;
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struct dma_async_tx_descriptor *iter;
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struct dma_async_tx_descriptor *parent;
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if (!tx)
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return DMA_SUCCESS;
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/* poll through the dependency chain, return when tx is complete */
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do {
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iter = tx;
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/* find the root of the unsubmitted dependency chain */
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do {
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parent = iter->parent;
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if (!parent)
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break;
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else
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iter = parent;
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} while (parent);
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/* there is a small window for ->parent == NULL and
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* ->cookie == -EBUSY
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*/
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while (iter->cookie == -EBUSY)
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cpu_relax();
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status = dma_sync_wait(iter->chan, iter->cookie);
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} while (status == DMA_IN_PROGRESS || (iter != tx));
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return status;
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}
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EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
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/* async_tx_run_dependencies - helper routine for dma drivers to process
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* (start) dependent operations on their target channel
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* @tx: transaction with dependencies
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*/
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void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx)
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{
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struct dma_async_tx_descriptor *dep = tx->next;
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struct dma_async_tx_descriptor *dep_next;
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struct dma_chan *chan;
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if (!dep)
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return;
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chan = dep->chan;
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/* keep submitting up until a channel switch is detected
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* in that case we will be called again as a result of
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* processing the interrupt from async_tx_channel_switch
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*/
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for (; dep; dep = dep_next) {
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spin_lock_bh(&dep->lock);
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dep->parent = NULL;
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dep_next = dep->next;
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if (dep_next && dep_next->chan == chan)
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dep->next = NULL; /* ->next will be submitted */
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else
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dep_next = NULL; /* submit current dep and terminate */
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spin_unlock_bh(&dep->lock);
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dep->tx_submit(dep);
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}
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chan->device->device_issue_pending(chan);
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}
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EXPORT_SYMBOL_GPL(async_tx_run_dependencies);
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static void
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free_dma_chan_ref(struct rcu_head *rcu)
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{
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struct dma_chan_ref *ref;
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ref = container_of(rcu, struct dma_chan_ref, rcu);
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kfree(ref);
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}
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static void
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init_dma_chan_ref(struct dma_chan_ref *ref, struct dma_chan *chan)
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{
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INIT_LIST_HEAD(&ref->node);
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INIT_RCU_HEAD(&ref->rcu);
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ref->chan = chan;
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atomic_set(&ref->count, 0);
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}
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/**
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* get_chan_ref_by_cap - returns the nth channel of the given capability
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* defaults to returning the channel with the desired capability and the
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* lowest reference count if the index can not be satisfied
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* @cap: capability to match
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* @index: nth channel desired, passing -1 has the effect of forcing the
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* default return value
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*/
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static struct dma_chan_ref *
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get_chan_ref_by_cap(enum dma_transaction_type cap, int index)
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{
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struct dma_chan_ref *ret_ref = NULL, *min_ref = NULL, *ref;
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rcu_read_lock();
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list_for_each_entry_rcu(ref, &async_tx_master_list, node)
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if (dma_has_cap(cap, ref->chan->device->cap_mask)) {
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if (!min_ref)
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min_ref = ref;
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else if (atomic_read(&ref->count) <
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atomic_read(&min_ref->count))
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min_ref = ref;
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if (index-- == 0) {
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ret_ref = ref;
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break;
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}
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}
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rcu_read_unlock();
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if (!ret_ref)
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ret_ref = min_ref;
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if (ret_ref)
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atomic_inc(&ret_ref->count);
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return ret_ref;
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}
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/**
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* async_tx_rebalance - redistribute the available channels, optimize
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* for cpu isolation in the SMP case, and opertaion isolation in the
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* uniprocessor case
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*/
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static void async_tx_rebalance(void)
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{
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int cpu, cap, cpu_idx = 0;
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unsigned long flags;
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if (!channel_table_initialized)
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return;
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spin_lock_irqsave(&async_tx_lock, flags);
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/* undo the last distribution */
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for_each_dma_cap_mask(cap, dma_cap_mask_all)
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for_each_possible_cpu(cpu) {
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struct dma_chan_ref *ref =
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per_cpu_ptr(channel_table[cap], cpu)->ref;
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if (ref) {
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atomic_set(&ref->count, 0);
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per_cpu_ptr(channel_table[cap], cpu)->ref =
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NULL;
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}
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}
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for_each_dma_cap_mask(cap, dma_cap_mask_all)
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for_each_online_cpu(cpu) {
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struct dma_chan_ref *new;
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if (NR_CPUS > 1)
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new = get_chan_ref_by_cap(cap, cpu_idx++);
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else
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new = get_chan_ref_by_cap(cap, -1);
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per_cpu_ptr(channel_table[cap], cpu)->ref = new;
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}
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spin_unlock_irqrestore(&async_tx_lock, flags);
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}
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static enum dma_state_client
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dma_channel_add_remove(struct dma_client *client,
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struct dma_chan *chan, enum dma_state state)
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{
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unsigned long found, flags;
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struct dma_chan_ref *master_ref, *ref;
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enum dma_state_client ack = DMA_DUP; /* default: take no action */
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switch (state) {
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case DMA_RESOURCE_AVAILABLE:
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found = 0;
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rcu_read_lock();
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list_for_each_entry_rcu(ref, &async_tx_master_list, node)
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if (ref->chan == chan) {
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found = 1;
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break;
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}
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rcu_read_unlock();
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pr_debug("async_tx: dma resource available [%s]\n",
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found ? "old" : "new");
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if (!found)
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ack = DMA_ACK;
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else
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break;
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/* add the channel to the generic management list */
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master_ref = kmalloc(sizeof(*master_ref), GFP_KERNEL);
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if (master_ref) {
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/* keep a reference until async_tx is unloaded */
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dma_chan_get(chan);
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init_dma_chan_ref(master_ref, chan);
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spin_lock_irqsave(&async_tx_lock, flags);
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list_add_tail_rcu(&master_ref->node,
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&async_tx_master_list);
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spin_unlock_irqrestore(&async_tx_lock,
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flags);
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} else {
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printk(KERN_WARNING "async_tx: unable to create"
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" new master entry in response to"
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" a DMA_RESOURCE_ADDED event"
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" (-ENOMEM)\n");
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return 0;
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}
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async_tx_rebalance();
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break;
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case DMA_RESOURCE_REMOVED:
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found = 0;
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spin_lock_irqsave(&async_tx_lock, flags);
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list_for_each_entry(ref, &async_tx_master_list, node)
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if (ref->chan == chan) {
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/* permit backing devices to go away */
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dma_chan_put(ref->chan);
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list_del_rcu(&ref->node);
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call_rcu(&ref->rcu, free_dma_chan_ref);
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found = 1;
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break;
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}
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spin_unlock_irqrestore(&async_tx_lock, flags);
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pr_debug("async_tx: dma resource removed [%s]\n",
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found ? "ours" : "not ours");
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if (found)
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ack = DMA_ACK;
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else
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break;
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async_tx_rebalance();
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break;
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case DMA_RESOURCE_SUSPEND:
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case DMA_RESOURCE_RESUME:
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printk(KERN_WARNING "async_tx: does not support dma channel"
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" suspend/resume\n");
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break;
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default:
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BUG();
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}
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return ack;
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}
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static int __init
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async_tx_init(void)
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{
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enum dma_transaction_type cap;
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spin_lock_init(&async_tx_lock);
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bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
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/* an interrupt will never be an explicit operation type.
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* clearing this bit prevents allocation to a slot in 'channel_table'
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*/
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clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
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for_each_dma_cap_mask(cap, dma_cap_mask_all) {
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channel_table[cap] = alloc_percpu(struct chan_ref_percpu);
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if (!channel_table[cap])
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goto err;
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}
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channel_table_initialized = 1;
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dma_async_client_register(&async_tx_dma);
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dma_async_client_chan_request(&async_tx_dma);
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printk(KERN_INFO "async_tx: api initialized (async)\n");
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return 0;
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err:
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printk(KERN_ERR "async_tx: initialization failure\n");
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while (--cap >= 0)
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free_percpu(channel_table[cap]);
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return 1;
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}
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static void __exit async_tx_exit(void)
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{
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enum dma_transaction_type cap;
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channel_table_initialized = 0;
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for_each_dma_cap_mask(cap, dma_cap_mask_all)
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if (channel_table[cap])
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free_percpu(channel_table[cap]);
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dma_async_client_unregister(&async_tx_dma);
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}
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/**
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* __async_tx_find_channel - find a channel to carry out the operation or let
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* the transaction execute synchronously
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* @depend_tx: transaction dependency
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* @tx_type: transaction type
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*/
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struct dma_chan *
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__async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
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enum dma_transaction_type tx_type)
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{
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/* see if we can keep the chain on one channel */
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if (depend_tx &&
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dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
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return depend_tx->chan;
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else if (likely(channel_table_initialized)) {
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struct dma_chan_ref *ref;
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int cpu = get_cpu();
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ref = per_cpu_ptr(channel_table[tx_type], cpu)->ref;
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put_cpu();
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return ref ? ref->chan : NULL;
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} else
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return NULL;
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}
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EXPORT_SYMBOL_GPL(__async_tx_find_channel);
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#else
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static int __init async_tx_init(void)
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{
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printk(KERN_INFO "async_tx: api initialized (sync-only)\n");
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return 0;
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}
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static void __exit async_tx_exit(void)
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{
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do { } while (0);
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}
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#endif
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/**
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* async_tx_channel_switch - queue an interrupt descriptor with a dependency
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* pre-attached.
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* @depend_tx: the operation that must finish before the new operation runs
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* @tx: the new operation
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*/
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static void
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async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
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struct dma_async_tx_descriptor *tx)
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{
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struct dma_chan *chan;
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struct dma_device *device;
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struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
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/* first check to see if we can still append to depend_tx */
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spin_lock_bh(&depend_tx->lock);
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if (depend_tx->parent && depend_tx->chan == tx->chan) {
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tx->parent = depend_tx;
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depend_tx->next = tx;
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intr_tx = NULL;
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}
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spin_unlock_bh(&depend_tx->lock);
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if (!intr_tx)
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return;
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chan = depend_tx->chan;
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device = chan->device;
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/* see if we can schedule an interrupt
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* otherwise poll for completion
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*/
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if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
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intr_tx = device->device_prep_dma_interrupt(chan, 0);
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else
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intr_tx = NULL;
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if (intr_tx) {
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intr_tx->callback = NULL;
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intr_tx->callback_param = NULL;
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tx->parent = intr_tx;
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/* safe to set ->next outside the lock since we know we are
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* not submitted yet
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*/
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intr_tx->next = tx;
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/* check if we need to append */
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spin_lock_bh(&depend_tx->lock);
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if (depend_tx->parent) {
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intr_tx->parent = depend_tx;
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depend_tx->next = intr_tx;
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async_tx_ack(intr_tx);
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intr_tx = NULL;
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}
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spin_unlock_bh(&depend_tx->lock);
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if (intr_tx) {
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intr_tx->parent = NULL;
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intr_tx->tx_submit(intr_tx);
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async_tx_ack(intr_tx);
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}
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} else {
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if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
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panic("%s: DMA_ERROR waiting for depend_tx\n",
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__func__);
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tx->tx_submit(tx);
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}
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}
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/**
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* submit_disposition - while holding depend_tx->lock we must avoid submitting
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* new operations to prevent a circular locking dependency with
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* drivers that already hold a channel lock when calling
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* async_tx_run_dependencies.
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* @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
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* @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
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* @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
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*/
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enum submit_disposition {
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ASYNC_TX_SUBMITTED,
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ASYNC_TX_CHANNEL_SWITCH,
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ASYNC_TX_DIRECT_SUBMIT,
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};
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void
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async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
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enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx,
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dma_async_tx_callback cb_fn, void *cb_param)
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{
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tx->callback = cb_fn;
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tx->callback_param = cb_param;
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if (depend_tx) {
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enum submit_disposition s;
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/* sanity check the dependency chain:
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* 1/ if ack is already set then we cannot be sure
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* we are referring to the correct operation
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* 2/ dependencies are 1:1 i.e. two transactions can
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* not depend on the same parent
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*/
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BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
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tx->parent);
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/* the lock prevents async_tx_run_dependencies from missing
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* the setting of ->next when ->parent != NULL
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*/
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spin_lock_bh(&depend_tx->lock);
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if (depend_tx->parent) {
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/* we have a parent so we can not submit directly
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* if we are staying on the same channel: append
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* else: channel switch
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*/
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if (depend_tx->chan == chan) {
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tx->parent = depend_tx;
|
|
depend_tx->next = tx;
|
|
s = ASYNC_TX_SUBMITTED;
|
|
} else
|
|
s = ASYNC_TX_CHANNEL_SWITCH;
|
|
} else {
|
|
/* we do not have a parent so we may be able to submit
|
|
* directly if we are staying on the same channel
|
|
*/
|
|
if (depend_tx->chan == chan)
|
|
s = ASYNC_TX_DIRECT_SUBMIT;
|
|
else
|
|
s = ASYNC_TX_CHANNEL_SWITCH;
|
|
}
|
|
spin_unlock_bh(&depend_tx->lock);
|
|
|
|
switch (s) {
|
|
case ASYNC_TX_SUBMITTED:
|
|
break;
|
|
case ASYNC_TX_CHANNEL_SWITCH:
|
|
async_tx_channel_switch(depend_tx, tx);
|
|
break;
|
|
case ASYNC_TX_DIRECT_SUBMIT:
|
|
tx->parent = NULL;
|
|
tx->tx_submit(tx);
|
|
break;
|
|
}
|
|
} else {
|
|
tx->parent = NULL;
|
|
tx->tx_submit(tx);
|
|
}
|
|
|
|
if (flags & ASYNC_TX_ACK)
|
|
async_tx_ack(tx);
|
|
|
|
if (depend_tx && (flags & ASYNC_TX_DEP_ACK))
|
|
async_tx_ack(depend_tx);
|
|
}
|
|
EXPORT_SYMBOL_GPL(async_tx_submit);
|
|
|
|
/**
|
|
* async_trigger_callback - schedules the callback function to be run after
|
|
* any dependent operations have been completed.
|
|
* @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK
|
|
* @depend_tx: 'callback' requires the completion of this transaction
|
|
* @cb_fn: function to call after depend_tx completes
|
|
* @cb_param: parameter to pass to the callback routine
|
|
*/
|
|
struct dma_async_tx_descriptor *
|
|
async_trigger_callback(enum async_tx_flags flags,
|
|
struct dma_async_tx_descriptor *depend_tx,
|
|
dma_async_tx_callback cb_fn, void *cb_param)
|
|
{
|
|
struct dma_chan *chan;
|
|
struct dma_device *device;
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
if (depend_tx) {
|
|
chan = depend_tx->chan;
|
|
device = chan->device;
|
|
|
|
/* see if we can schedule an interrupt
|
|
* otherwise poll for completion
|
|
*/
|
|
if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
|
|
device = NULL;
|
|
|
|
tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
|
|
} else
|
|
tx = NULL;
|
|
|
|
if (tx) {
|
|
pr_debug("%s: (async)\n", __func__);
|
|
|
|
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
|
|
} else {
|
|
pr_debug("%s: (sync)\n", __func__);
|
|
|
|
/* wait for any prerequisite operations */
|
|
async_tx_quiesce(&depend_tx);
|
|
|
|
async_tx_sync_epilog(cb_fn, cb_param);
|
|
}
|
|
|
|
return tx;
|
|
}
|
|
EXPORT_SYMBOL_GPL(async_trigger_callback);
|
|
|
|
/**
|
|
* async_tx_quiesce - ensure tx is complete and freeable upon return
|
|
* @tx - transaction to quiesce
|
|
*/
|
|
void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
|
|
{
|
|
if (*tx) {
|
|
/* if ack is already set then we cannot be sure
|
|
* we are referring to the correct operation
|
|
*/
|
|
BUG_ON(async_tx_test_ack(*tx));
|
|
if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
|
|
panic("DMA_ERROR waiting for transaction\n");
|
|
async_tx_ack(*tx);
|
|
*tx = NULL;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(async_tx_quiesce);
|
|
|
|
module_init(async_tx_init);
|
|
module_exit(async_tx_exit);
|
|
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
|
|
MODULE_LICENSE("GPL");
|