![Russell King](/assets/img/avatar_default.png)
The start_tx and stop_tx methods were passed a flag to indicate whether the start/stop was from the tty start/stop callbacks, and some drivers used this flag to decide whether to ask the UART to immediately stop transmission (where the UART supports such a feature.) There are other cases when we wish this to occur - when CTS is lowered, or if we change from soft to hard flow control and CTS is inactive. In these cases, this flag was false, and we would allow the transmitter to drain before stopping. There is really only one case where we want to let the transmitter drain before disabling, and that's when we run out of characters to send. Hence, re-jig the start_tx and stop_tx methods to eliminate this flag, and introduce new functions for the special "disable and allow transmitter to drain" case. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1051 lines
22 KiB
C
1051 lines
22 KiB
C
/*
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* Driver for NEC VR4100 series Serial Interface Unit.
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*
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* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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*
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* Based on drivers/serial/8250.c, by Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/console.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <asm/io.h>
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#include <asm/vr41xx/siu.h>
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#include <asm/vr41xx/vr41xx.h>
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#define SIU_PORTS_MAX 2
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#define SIU_BAUD_BASE 1152000
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#define SIU_MAJOR 204
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#define SIU_MINOR_BASE 82
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#define RX_MAX_COUNT 256
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#define TX_MAX_COUNT 15
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#define SIUIRSEL 0x08
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#define TMICMODE 0x20
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#define TMICTX 0x10
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#define IRMSEL 0x0c
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#define IRMSEL_HP 0x08
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#define IRMSEL_TEMIC 0x04
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#define IRMSEL_SHARP 0x00
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#define IRUSESEL 0x02
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#define SIRSEL 0x01
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struct siu_port {
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unsigned int type;
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unsigned int irq;
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unsigned long start;
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};
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static const struct siu_port siu_type1_ports[] = {
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{ .type = PORT_VR41XX_SIU,
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.irq = SIU_IRQ,
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.start = 0x0c000000UL, },
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};
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#define SIU_TYPE1_NR_PORTS (sizeof(siu_type1_ports) / sizeof(struct siu_port))
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static const struct siu_port siu_type2_ports[] = {
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{ .type = PORT_VR41XX_SIU,
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.irq = SIU_IRQ,
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.start = 0x0f000800UL, },
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{ .type = PORT_VR41XX_DSIU,
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.irq = DSIU_IRQ,
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.start = 0x0f000820UL, },
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};
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#define SIU_TYPE2_NR_PORTS (sizeof(siu_type2_ports) / sizeof(struct siu_port))
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static struct uart_port siu_uart_ports[SIU_PORTS_MAX];
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static uint8_t lsr_break_flag[SIU_PORTS_MAX];
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#define siu_read(port, offset) readb((port)->membase + (offset))
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#define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
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void vr41xx_select_siu_interface(siu_interface_t interface)
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{
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struct uart_port *port;
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unsigned long flags;
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uint8_t irsel;
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port = &siu_uart_ports[0];
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spin_lock_irqsave(&port->lock, flags);
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irsel = siu_read(port, SIUIRSEL);
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if (interface == SIU_INTERFACE_IRDA)
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irsel |= SIRSEL;
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else
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irsel &= ~SIRSEL;
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siu_write(port, SIUIRSEL, irsel);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface);
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void vr41xx_use_irda(irda_use_t use)
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{
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struct uart_port *port;
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unsigned long flags;
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uint8_t irsel;
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port = &siu_uart_ports[0];
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spin_lock_irqsave(&port->lock, flags);
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irsel = siu_read(port, SIUIRSEL);
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if (use == FIR_USE_IRDA)
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irsel |= IRUSESEL;
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else
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irsel &= ~IRUSESEL;
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siu_write(port, SIUIRSEL, irsel);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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EXPORT_SYMBOL_GPL(vr41xx_use_irda);
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void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
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{
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struct uart_port *port;
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unsigned long flags;
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uint8_t irsel;
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port = &siu_uart_ports[0];
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spin_lock_irqsave(&port->lock, flags);
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irsel = siu_read(port, SIUIRSEL);
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irsel &= ~(IRMSEL | TMICTX | TMICMODE);
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switch (module) {
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case SHARP_IRDA:
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irsel |= IRMSEL_SHARP;
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break;
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case TEMIC_IRDA:
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irsel |= IRMSEL_TEMIC | TMICMODE;
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if (speed == IRDA_TX_4MBPS)
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irsel |= TMICTX;
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break;
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case HP_IRDA:
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irsel |= IRMSEL_HP;
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break;
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default:
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break;
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}
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siu_write(port, SIUIRSEL, irsel);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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EXPORT_SYMBOL_GPL(vr41xx_select_irda_module);
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static inline void siu_clear_fifo(struct uart_port *port)
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{
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siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO);
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siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
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UART_FCR_CLEAR_XMIT);
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siu_write(port, UART_FCR, 0);
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}
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static inline int siu_probe_ports(void)
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{
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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case CPU_VR4121:
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return SIU_TYPE1_NR_PORTS;
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case CPU_VR4122:
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case CPU_VR4131:
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case CPU_VR4133:
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return SIU_TYPE2_NR_PORTS;
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}
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return 0;
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}
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static inline unsigned long siu_port_size(struct uart_port *port)
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{
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switch (port->type) {
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case PORT_VR41XX_SIU:
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return 11UL;
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case PORT_VR41XX_DSIU:
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return 8UL;
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}
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return 0;
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}
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static inline unsigned int siu_check_type(struct uart_port *port)
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{
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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case CPU_VR4121:
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if (port->line == 0)
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return PORT_VR41XX_SIU;
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break;
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case CPU_VR4122:
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case CPU_VR4131:
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case CPU_VR4133:
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if (port->line == 0)
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return PORT_VR41XX_SIU;
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else if (port->line == 1)
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return PORT_VR41XX_DSIU;
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break;
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}
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return PORT_UNKNOWN;
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}
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static inline const char *siu_type_name(struct uart_port *port)
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{
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switch (port->type) {
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case PORT_VR41XX_SIU:
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return "SIU";
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case PORT_VR41XX_DSIU:
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return "DSIU";
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}
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return NULL;
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}
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static unsigned int siu_tx_empty(struct uart_port *port)
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{
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uint8_t lsr;
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lsr = siu_read(port, UART_LSR);
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if (lsr & UART_LSR_TEMT)
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return TIOCSER_TEMT;
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return 0;
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}
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static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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uint8_t mcr = 0;
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if (mctrl & TIOCM_DTR)
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mcr |= UART_MCR_DTR;
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if (mctrl & TIOCM_RTS)
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mcr |= UART_MCR_RTS;
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if (mctrl & TIOCM_OUT1)
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mcr |= UART_MCR_OUT1;
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if (mctrl & TIOCM_OUT2)
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mcr |= UART_MCR_OUT2;
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if (mctrl & TIOCM_LOOP)
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mcr |= UART_MCR_LOOP;
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siu_write(port, UART_MCR, mcr);
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}
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static unsigned int siu_get_mctrl(struct uart_port *port)
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{
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uint8_t msr;
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unsigned int mctrl = 0;
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msr = siu_read(port, UART_MSR);
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if (msr & UART_MSR_DCD)
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mctrl |= TIOCM_CAR;
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if (msr & UART_MSR_RI)
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mctrl |= TIOCM_RNG;
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if (msr & UART_MSR_DSR)
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mctrl |= TIOCM_DSR;
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if (msr & UART_MSR_CTS)
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mctrl |= TIOCM_CTS;
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return mctrl;
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}
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static void siu_stop_tx(struct uart_port *port)
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{
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unsigned long flags;
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uint8_t ier;
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spin_lock_irqsave(&port->lock, flags);
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ier = siu_read(port, UART_IER);
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ier &= ~UART_IER_THRI;
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siu_write(port, UART_IER, ier);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static void siu_start_tx(struct uart_port *port)
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{
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unsigned long flags;
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uint8_t ier;
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spin_lock_irqsave(&port->lock, flags);
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ier = siu_read(port, UART_IER);
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ier |= UART_IER_THRI;
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siu_write(port, UART_IER, ier);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static void siu_stop_rx(struct uart_port *port)
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{
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unsigned long flags;
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uint8_t ier;
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spin_lock_irqsave(&port->lock, flags);
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ier = siu_read(port, UART_IER);
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ier &= ~UART_IER_RLSI;
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siu_write(port, UART_IER, ier);
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port->read_status_mask &= ~UART_LSR_DR;
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static void siu_enable_ms(struct uart_port *port)
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{
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unsigned long flags;
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uint8_t ier;
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spin_lock_irqsave(&port->lock, flags);
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ier = siu_read(port, UART_IER);
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ier |= UART_IER_MSI;
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siu_write(port, UART_IER, ier);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static void siu_break_ctl(struct uart_port *port, int ctl)
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{
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unsigned long flags;
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uint8_t lcr;
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spin_lock_irqsave(&port->lock, flags);
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lcr = siu_read(port, UART_LCR);
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if (ctl == -1)
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lcr |= UART_LCR_SBC;
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else
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lcr &= ~UART_LCR_SBC;
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siu_write(port, UART_LCR, lcr);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static inline void receive_chars(struct uart_port *port, uint8_t *status,
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struct pt_regs *regs)
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{
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struct tty_struct *tty;
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uint8_t lsr, ch;
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char flag;
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int max_count = RX_MAX_COUNT;
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tty = port->info->tty;
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lsr = *status;
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do {
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if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
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if (tty->low_latency)
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tty_flip_buffer_push(tty);
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}
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ch = siu_read(port, UART_RX);
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port->icount.rx++;
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flag = TTY_NORMAL;
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#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
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lsr |= lsr_break_flag[port->line];
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lsr_break_flag[port->line] = 0;
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#endif
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if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE |
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UART_LSR_PE | UART_LSR_OE))) {
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if (lsr & UART_LSR_BI) {
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lsr &= ~(UART_LSR_FE | UART_LSR_PE);
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port->icount.brk++;
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if (uart_handle_break(port))
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goto ignore_char;
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}
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if (lsr & UART_LSR_FE)
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port->icount.frame++;
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if (lsr & UART_LSR_PE)
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port->icount.parity++;
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if (lsr & UART_LSR_OE)
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port->icount.overrun++;
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lsr &= port->read_status_mask;
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if (lsr & UART_LSR_BI)
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flag = TTY_BREAK;
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if (lsr & UART_LSR_FE)
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flag = TTY_FRAME;
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if (lsr & UART_LSR_PE)
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flag = TTY_PARITY;
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}
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if (uart_handle_sysrq_char(port, ch, regs))
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goto ignore_char;
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uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
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ignore_char:
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lsr = siu_read(port, UART_LSR);
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} while ((lsr & UART_LSR_DR) && (max_count-- > 0));
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tty_flip_buffer_push(tty);
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*status = lsr;
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}
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static inline void check_modem_status(struct uart_port *port)
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{
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uint8_t msr;
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msr = siu_read(port, UART_MSR);
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if ((msr & UART_MSR_ANY_DELTA) == 0)
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return;
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if (msr & UART_MSR_DDCD)
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uart_handle_dcd_change(port, msr & UART_MSR_DCD);
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if (msr & UART_MSR_TERI)
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port->icount.rng++;
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if (msr & UART_MSR_DDSR)
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port->icount.dsr++;
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if (msr & UART_MSR_DCTS)
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uart_handle_cts_change(port, msr & UART_MSR_CTS);
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wake_up_interruptible(&port->info->delta_msr_wait);
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}
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|
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static inline void transmit_chars(struct uart_port *port)
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{
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struct circ_buf *xmit;
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int max_count = TX_MAX_COUNT;
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xmit = &port->info->xmit;
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|
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if (port->x_char) {
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siu_write(port, UART_TX, port->x_char);
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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|
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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siu_stop_tx(port);
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return;
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}
|
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do {
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siu_write(port, UART_TX, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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} while (max_count-- > 0);
|
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|
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
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uart_write_wakeup(port);
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|
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if (uart_circ_empty(xmit))
|
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siu_stop_tx(port);
|
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}
|
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|
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static irqreturn_t siu_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
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{
|
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struct uart_port *port;
|
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uint8_t iir, lsr;
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|
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port = (struct uart_port *)dev_id;
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|
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iir = siu_read(port, UART_IIR);
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if (iir & UART_IIR_NO_INT)
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return IRQ_NONE;
|
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|
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lsr = siu_read(port, UART_LSR);
|
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if (lsr & UART_LSR_DR)
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receive_chars(port, &lsr, regs);
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|
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check_modem_status(port);
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|
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if (lsr & UART_LSR_THRE)
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transmit_chars(port);
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|
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return IRQ_HANDLED;
|
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}
|
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|
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static int siu_startup(struct uart_port *port)
|
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{
|
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int retval;
|
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|
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if (port->membase == NULL)
|
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return -ENODEV;
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|
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siu_clear_fifo(port);
|
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|
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(void)siu_read(port, UART_LSR);
|
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(void)siu_read(port, UART_RX);
|
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(void)siu_read(port, UART_IIR);
|
|
(void)siu_read(port, UART_MSR);
|
|
|
|
if (siu_read(port, UART_LSR) == 0xff)
|
|
return -ENODEV;
|
|
|
|
retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port);
|
|
if (retval)
|
|
return retval;
|
|
|
|
if (port->type == PORT_VR41XX_DSIU)
|
|
vr41xx_enable_dsiuint(DSIUINT_ALL);
|
|
|
|
siu_write(port, UART_LCR, UART_LCR_WLEN8);
|
|
|
|
spin_lock_irq(&port->lock);
|
|
siu_set_mctrl(port, port->mctrl);
|
|
spin_unlock_irq(&port->lock);
|
|
|
|
siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI);
|
|
|
|
(void)siu_read(port, UART_LSR);
|
|
(void)siu_read(port, UART_RX);
|
|
(void)siu_read(port, UART_IIR);
|
|
(void)siu_read(port, UART_MSR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void siu_shutdown(struct uart_port *port)
|
|
{
|
|
unsigned long flags;
|
|
uint8_t lcr;
|
|
|
|
siu_write(port, UART_IER, 0);
|
|
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
|
|
port->mctrl &= ~TIOCM_OUT2;
|
|
siu_set_mctrl(port, port->mctrl);
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
|
|
lcr = siu_read(port, UART_LCR);
|
|
lcr &= ~UART_LCR_SBC;
|
|
siu_write(port, UART_LCR, lcr);
|
|
|
|
siu_clear_fifo(port);
|
|
|
|
(void)siu_read(port, UART_RX);
|
|
|
|
if (port->type == PORT_VR41XX_DSIU)
|
|
vr41xx_disable_dsiuint(DSIUINT_ALL);
|
|
|
|
free_irq(port->irq, port);
|
|
}
|
|
|
|
static void siu_set_termios(struct uart_port *port, struct termios *new,
|
|
struct termios *old)
|
|
{
|
|
tcflag_t c_cflag, c_iflag;
|
|
uint8_t lcr, fcr, ier;
|
|
unsigned int baud, quot;
|
|
unsigned long flags;
|
|
|
|
c_cflag = new->c_cflag;
|
|
switch (c_cflag & CSIZE) {
|
|
case CS5:
|
|
lcr = UART_LCR_WLEN5;
|
|
break;
|
|
case CS6:
|
|
lcr = UART_LCR_WLEN6;
|
|
break;
|
|
case CS7:
|
|
lcr = UART_LCR_WLEN7;
|
|
break;
|
|
default:
|
|
lcr = UART_LCR_WLEN8;
|
|
break;
|
|
}
|
|
|
|
if (c_cflag & CSTOPB)
|
|
lcr |= UART_LCR_STOP;
|
|
if (c_cflag & PARENB)
|
|
lcr |= UART_LCR_PARITY;
|
|
if ((c_cflag & PARODD) != PARODD)
|
|
lcr |= UART_LCR_EPAR;
|
|
if (c_cflag & CMSPAR)
|
|
lcr |= UART_LCR_SPAR;
|
|
|
|
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
|
|
quot = uart_get_divisor(port, baud);
|
|
|
|
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
|
|
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
|
|
uart_update_timeout(port, c_cflag, baud);
|
|
|
|
c_iflag = new->c_iflag;
|
|
|
|
port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
|
|
if (c_iflag & INPCK)
|
|
port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
|
|
if (c_iflag & (BRKINT | PARMRK))
|
|
port->read_status_mask |= UART_LSR_BI;
|
|
|
|
port->ignore_status_mask = 0;
|
|
if (c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
|
|
if (c_iflag & IGNBRK) {
|
|
port->ignore_status_mask |= UART_LSR_BI;
|
|
if (c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= UART_LSR_OE;
|
|
}
|
|
|
|
if ((c_cflag & CREAD) == 0)
|
|
port->ignore_status_mask |= UART_LSR_DR;
|
|
|
|
ier = siu_read(port, UART_IER);
|
|
ier &= ~UART_IER_MSI;
|
|
if (UART_ENABLE_MS(port, c_cflag))
|
|
ier |= UART_IER_MSI;
|
|
siu_write(port, UART_IER, ier);
|
|
|
|
siu_write(port, UART_LCR, lcr | UART_LCR_DLAB);
|
|
|
|
siu_write(port, UART_DLL, (uint8_t)quot);
|
|
siu_write(port, UART_DLM, (uint8_t)(quot >> 8));
|
|
|
|
siu_write(port, UART_LCR, lcr);
|
|
|
|
siu_write(port, UART_FCR, fcr);
|
|
|
|
siu_set_mctrl(port, port->mctrl);
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
|
|
{
|
|
switch (state) {
|
|
case 0:
|
|
switch (port->type) {
|
|
case PORT_VR41XX_SIU:
|
|
vr41xx_supply_clock(SIU_CLOCK);
|
|
break;
|
|
case PORT_VR41XX_DSIU:
|
|
vr41xx_supply_clock(DSIU_CLOCK);
|
|
break;
|
|
}
|
|
break;
|
|
case 3:
|
|
switch (port->type) {
|
|
case PORT_VR41XX_SIU:
|
|
vr41xx_mask_clock(SIU_CLOCK);
|
|
break;
|
|
case PORT_VR41XX_DSIU:
|
|
vr41xx_mask_clock(DSIU_CLOCK);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const char *siu_type(struct uart_port *port)
|
|
{
|
|
return siu_type_name(port);
|
|
}
|
|
|
|
static void siu_release_port(struct uart_port *port)
|
|
{
|
|
unsigned long size;
|
|
|
|
if (port->flags & UPF_IOREMAP) {
|
|
iounmap(port->membase);
|
|
port->membase = NULL;
|
|
}
|
|
|
|
size = siu_port_size(port);
|
|
release_mem_region(port->mapbase, size);
|
|
}
|
|
|
|
static int siu_request_port(struct uart_port *port)
|
|
{
|
|
unsigned long size;
|
|
struct resource *res;
|
|
|
|
size = siu_port_size(port);
|
|
res = request_mem_region(port->mapbase, size, siu_type_name(port));
|
|
if (res == NULL)
|
|
return -EBUSY;
|
|
|
|
if (port->flags & UPF_IOREMAP) {
|
|
port->membase = ioremap(port->mapbase, size);
|
|
if (port->membase == NULL) {
|
|
release_resource(res);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void siu_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = siu_check_type(port);
|
|
(void)siu_request_port(port);
|
|
}
|
|
}
|
|
|
|
static int siu_verify_port(struct uart_port *port, struct serial_struct *serial)
|
|
{
|
|
if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU)
|
|
return -EINVAL;
|
|
if (port->irq != serial->irq)
|
|
return -EINVAL;
|
|
if (port->iotype != serial->io_type)
|
|
return -EINVAL;
|
|
if (port->mapbase != (unsigned long)serial->iomem_base)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct uart_ops siu_uart_ops = {
|
|
.tx_empty = siu_tx_empty,
|
|
.set_mctrl = siu_set_mctrl,
|
|
.get_mctrl = siu_get_mctrl,
|
|
.stop_tx = siu_stop_tx,
|
|
.start_tx = siu_start_tx,
|
|
.stop_rx = siu_stop_rx,
|
|
.enable_ms = siu_enable_ms,
|
|
.break_ctl = siu_break_ctl,
|
|
.startup = siu_startup,
|
|
.shutdown = siu_shutdown,
|
|
.set_termios = siu_set_termios,
|
|
.pm = siu_pm,
|
|
.type = siu_type,
|
|
.release_port = siu_release_port,
|
|
.request_port = siu_request_port,
|
|
.config_port = siu_config_port,
|
|
.verify_port = siu_verify_port,
|
|
};
|
|
|
|
static int siu_init_ports(void)
|
|
{
|
|
const struct siu_port *siu;
|
|
struct uart_port *port;
|
|
int i, num;
|
|
|
|
switch (current_cpu_data.cputype) {
|
|
case CPU_VR4111:
|
|
case CPU_VR4121:
|
|
siu = siu_type1_ports;
|
|
break;
|
|
case CPU_VR4122:
|
|
case CPU_VR4131:
|
|
case CPU_VR4133:
|
|
siu = siu_type2_ports;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
port = siu_uart_ports;
|
|
num = siu_probe_ports();
|
|
for (i = 0; i < num; i++) {
|
|
spin_lock_init(&port->lock);
|
|
port->irq = siu->irq;
|
|
port->uartclk = SIU_BAUD_BASE * 16;
|
|
port->fifosize = 16;
|
|
port->regshift = 0;
|
|
port->iotype = UPIO_MEM;
|
|
port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
|
|
port->type = siu->type;
|
|
port->line = i;
|
|
port->mapbase = siu->start;
|
|
siu++;
|
|
port++;
|
|
}
|
|
|
|
return num;
|
|
}
|
|
|
|
#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
|
|
|
|
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
|
|
|
|
static void wait_for_xmitr(struct uart_port *port)
|
|
{
|
|
int timeout = 10000;
|
|
uint8_t lsr, msr;
|
|
|
|
do {
|
|
lsr = siu_read(port, UART_LSR);
|
|
if (lsr & UART_LSR_BI)
|
|
lsr_break_flag[port->line] = UART_LSR_BI;
|
|
|
|
if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
|
|
break;
|
|
} while (timeout-- > 0);
|
|
|
|
if (port->flags & UPF_CONS_FLOW) {
|
|
timeout = 1000000;
|
|
|
|
do {
|
|
msr = siu_read(port, UART_MSR);
|
|
if ((msr & UART_MSR_CTS) != 0)
|
|
break;
|
|
} while (timeout-- > 0);
|
|
}
|
|
}
|
|
|
|
static void siu_console_write(struct console *con, const char *s, unsigned count)
|
|
{
|
|
struct uart_port *port;
|
|
uint8_t ier;
|
|
unsigned i;
|
|
|
|
port = &siu_uart_ports[con->index];
|
|
|
|
ier = siu_read(port, UART_IER);
|
|
siu_write(port, UART_IER, 0);
|
|
|
|
for (i = 0; i < count && *s != '\0'; i++, s++) {
|
|
wait_for_xmitr(port);
|
|
siu_write(port, UART_TX, *s);
|
|
if (*s == '\n') {
|
|
wait_for_xmitr(port);
|
|
siu_write(port, UART_TX, '\r');
|
|
}
|
|
}
|
|
|
|
wait_for_xmitr(port);
|
|
siu_write(port, UART_IER, ier);
|
|
}
|
|
|
|
static int siu_console_setup(struct console *con, char *options)
|
|
{
|
|
struct uart_port *port;
|
|
int baud = 9600;
|
|
int parity = 'n';
|
|
int bits = 8;
|
|
int flow = 'n';
|
|
|
|
if (con->index >= SIU_PORTS_MAX)
|
|
con->index = 0;
|
|
|
|
port = &siu_uart_ports[con->index];
|
|
if (port->membase == NULL) {
|
|
if (port->mapbase == 0)
|
|
return -ENODEV;
|
|
port->membase = ioremap(port->mapbase, siu_port_size(port));
|
|
}
|
|
|
|
vr41xx_select_siu_interface(SIU_INTERFACE_RS232C);
|
|
|
|
if (options != NULL)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(port, con, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver siu_uart_driver;
|
|
|
|
static struct console siu_console = {
|
|
.name = "ttyVR",
|
|
.write = siu_console_write,
|
|
.device = uart_console_device,
|
|
.setup = siu_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &siu_uart_driver,
|
|
};
|
|
|
|
static int __devinit siu_console_init(void)
|
|
{
|
|
struct uart_port *port;
|
|
int num, i;
|
|
|
|
num = siu_init_ports();
|
|
if (num <= 0)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
port = &siu_uart_ports[i];
|
|
port->ops = &siu_uart_ops;
|
|
}
|
|
|
|
register_console(&siu_console);
|
|
|
|
return 0;
|
|
}
|
|
|
|
console_initcall(siu_console_init);
|
|
|
|
#define SERIAL_VR41XX_CONSOLE &siu_console
|
|
#else
|
|
#define SERIAL_VR41XX_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver siu_uart_driver = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "SIU",
|
|
.dev_name = "ttyVR",
|
|
.devfs_name = "ttvr/",
|
|
.major = SIU_MAJOR,
|
|
.minor = SIU_MINOR_BASE,
|
|
.cons = SERIAL_VR41XX_CONSOLE,
|
|
};
|
|
|
|
static int siu_probe(struct device *dev)
|
|
{
|
|
struct uart_port *port;
|
|
int num, i, retval;
|
|
|
|
num = siu_init_ports();
|
|
if (num <= 0)
|
|
return -ENODEV;
|
|
|
|
siu_uart_driver.nr = num;
|
|
retval = uart_register_driver(&siu_uart_driver);
|
|
if (retval)
|
|
return retval;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
port = &siu_uart_ports[i];
|
|
port->ops = &siu_uart_ops;
|
|
port->dev = dev;
|
|
|
|
retval = uart_add_one_port(&siu_uart_driver, port);
|
|
if (retval < 0) {
|
|
port->dev = NULL;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i == 0 && retval < 0) {
|
|
uart_unregister_driver(&siu_uart_driver);
|
|
return retval;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int siu_remove(struct device *dev)
|
|
{
|
|
struct uart_port *port;
|
|
int i;
|
|
|
|
for (i = 0; i < siu_uart_driver.nr; i++) {
|
|
port = &siu_uart_ports[i];
|
|
if (port->dev == dev) {
|
|
uart_remove_one_port(&siu_uart_driver, port);
|
|
port->dev = NULL;
|
|
}
|
|
}
|
|
|
|
uart_unregister_driver(&siu_uart_driver);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int siu_suspend(struct device *dev, pm_message_t state, u32 level)
|
|
{
|
|
struct uart_port *port;
|
|
int i;
|
|
|
|
if (level != SUSPEND_DISABLE)
|
|
return 0;
|
|
|
|
for (i = 0; i < siu_uart_driver.nr; i++) {
|
|
port = &siu_uart_ports[i];
|
|
if ((port->type == PORT_VR41XX_SIU ||
|
|
port->type == PORT_VR41XX_DSIU) && port->dev == dev)
|
|
uart_suspend_port(&siu_uart_driver, port);
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int siu_resume(struct device *dev, u32 level)
|
|
{
|
|
struct uart_port *port;
|
|
int i;
|
|
|
|
if (level != RESUME_ENABLE)
|
|
return 0;
|
|
|
|
for (i = 0; i < siu_uart_driver.nr; i++) {
|
|
port = &siu_uart_ports[i];
|
|
if ((port->type == PORT_VR41XX_SIU ||
|
|
port->type == PORT_VR41XX_DSIU) && port->dev == dev)
|
|
uart_resume_port(&siu_uart_driver, port);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_device *siu_platform_device;
|
|
|
|
static struct device_driver siu_device_driver = {
|
|
.name = "SIU",
|
|
.bus = &platform_bus_type,
|
|
.probe = siu_probe,
|
|
.remove = siu_remove,
|
|
.suspend = siu_suspend,
|
|
.resume = siu_resume,
|
|
};
|
|
|
|
static int __devinit vr41xx_siu_init(void)
|
|
{
|
|
int retval;
|
|
|
|
siu_platform_device = platform_device_register_simple("SIU", -1, NULL, 0);
|
|
if (IS_ERR(siu_platform_device))
|
|
return PTR_ERR(siu_platform_device);
|
|
|
|
retval = driver_register(&siu_device_driver);
|
|
if (retval < 0)
|
|
platform_device_unregister(siu_platform_device);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void __devexit vr41xx_siu_exit(void)
|
|
{
|
|
driver_unregister(&siu_device_driver);
|
|
|
|
platform_device_unregister(siu_platform_device);
|
|
}
|
|
|
|
module_init(vr41xx_siu_init);
|
|
module_exit(vr41xx_siu_exit);
|