235 lines
4.7 KiB
C
235 lines
4.7 KiB
C
#ifndef __ASM_SH_ATOMIC_H
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#define __ASM_SH_ATOMIC_H
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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*/
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typedef struct { volatile int counter; } atomic_t;
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#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) ((v)->counter = (i))
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#include <linux/compiler.h>
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#include <asm/system.h>
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/*
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* To get proper branch prediction for the main line, we must branch
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* forward to code at the end of this object's .text section, then
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* branch back to restart the operation.
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%2, %0 ! atomic_add \n"
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" add %1, %0 \n"
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" movco.l %0, @%2 \n"
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" bf 1b \n"
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: "=&z" (tmp)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v += i;
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local_irq_restore(flags);
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#endif
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%2, %0 ! atomic_sub \n"
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" sub %1, %0 \n"
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" movco.l %0, @%2 \n"
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" bf 1b \n"
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: "=&z" (tmp)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v -= i;
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local_irq_restore(flags);
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#endif
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}
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/*
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* SH-4A note:
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*
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* We basically get atomic_xxx_return() for free compared with
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* atomic_xxx(). movli.l/movco.l require r0 due to the instruction
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* encoding, so the retval is automatically set without having to
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* do any special work.
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*/
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long temp;
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#ifdef CONFIG_CPU_SH4A
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__asm__ __volatile__ (
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"1: movli.l @%2, %0 ! atomic_add_return \n"
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" add %1, %0 \n"
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" movco.l %0, @%2 \n"
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" bf 1b \n"
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" synco \n"
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: "=&z" (temp)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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temp = *(long *)v;
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temp += i;
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*(long *)v = temp;
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local_irq_restore(flags);
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#endif
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return temp;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long temp;
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#ifdef CONFIG_CPU_SH4A
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__asm__ __volatile__ (
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"1: movli.l @%2, %0 ! atomic_sub_return \n"
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" sub %1, %0 \n"
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" movco.l %0, @%2 \n"
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" bf 1b \n"
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" synco \n"
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: "=&z" (temp)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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temp = *(long *)v;
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temp -= i;
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*(long *)v = temp;
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local_irq_restore(flags);
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#endif
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return temp;
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}
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#define atomic_dec_return(v) atomic_sub_return(1,(v))
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#define atomic_inc_return(v) atomic_add_return(1,(v))
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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#define atomic_inc(v) atomic_add(1,(v))
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#define atomic_dec(v) atomic_sub(1,(v))
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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unsigned long flags;
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local_irq_save(flags);
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ret = v->counter;
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if (likely(ret == old))
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v->counter = new;
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local_irq_restore(flags);
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return ret;
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}
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static inline int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int ret;
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unsigned long flags;
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local_irq_save(flags);
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ret = v->counter;
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if (ret != u)
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v->counter += a;
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local_irq_restore(flags);
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return ret != u;
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}
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%2, %0 ! atomic_clear_mask \n"
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" and %1, %0 \n"
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" movco.l %0, @%2 \n"
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" bf 1b \n"
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: "=&z" (tmp)
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: "r" (~mask), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v &= ~mask;
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local_irq_restore(flags);
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#endif
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}
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static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%2, %0 ! atomic_set_mask \n"
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" or %1, %0 \n"
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" movco.l %0, @%2 \n"
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" bf 1b \n"
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: "=&z" (tmp)
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: "r" (mask), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v |= mask;
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local_irq_restore(flags);
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#endif
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}
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/* Atomic operations are already serializing on SH */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#include <asm-generic/atomic.h>
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#endif /* __ASM_SH_ATOMIC_H */
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