d84083268b
This patch is hdmi display support for exynos drm driver. There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv and some low level code is already in s5p-tv and even headers for register define are almost same. but in this patch, we decide not to consider separated common code with s5p-tv. Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc. 1. mixer. The piece of hardware responsible for mixing and blending multiple data inputs before passing it to an output device. The mixer is capable of handling up to three image layers. One is the output of VP. Other two are images in RGB format. The blending factor, and layers' priority are controlled by mixer's registers. The output is passed to HDMI. 2. vp (video processor). It is used for processing of NV12/NV21 data. An image stored in RAM is accessed by DMA. The output in YCbCr444 format is send to mixer. 3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes pixel data from mixer and transforms it into data frames. The output is send to HDMIPHY interface. 4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to HDMI connector. Basically, it contains a PLL that produces source clock for mixer, vp and hdmi. 5. ddc (display data channel). It is dedicated i2c channel to exchange display information as edid with display monitor. With plane support, exynos hdmi driver fully supports two mixer layes and vp layer. Also vp layer supports multi buffer plane pixel formats having non contigus memory spaces. In exynos drm driver, common drm_hdmi driver to interface with drm framework has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls them. mixer controls all overlay layers in both mixer and vp. Vblank interrupts for hdmi are handled by mixer internally because drm framework cannot support multiple irq id. And pipe number is used to check which display device irq happens. History v2: this version - drm plane feature support to handle overlay layers. - multi buffer plane pixel format support for vp layer. - vp layer support RFCv1: original - at https://lkml.org/lkml/2011/11/4/164 Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
143 lines
4.3 KiB
C
143 lines
4.3 KiB
C
/* exynos_drm.h
|
|
*
|
|
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
|
* Authors:
|
|
* Inki Dae <inki.dae@samsung.com>
|
|
* Joonyoung Shim <jy0922.shim@samsung.com>
|
|
* Seung-Woo Kim <sw0312.kim@samsung.com>
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef _EXYNOS_DRM_H_
|
|
#define _EXYNOS_DRM_H_
|
|
|
|
/**
|
|
* User-desired buffer creation information structure.
|
|
*
|
|
* @size: user-desired memory allocation size.
|
|
* - this size value would be page-aligned internally.
|
|
* @flags: user request for setting memory type or cache attributes.
|
|
* @handle: returned a handle to created gem object.
|
|
* - this handle will be set by gem module of kernel side.
|
|
*/
|
|
struct drm_exynos_gem_create {
|
|
uint64_t size;
|
|
unsigned int flags;
|
|
unsigned int handle;
|
|
};
|
|
|
|
/**
|
|
* A structure for getting buffer offset.
|
|
*
|
|
* @handle: a pointer to gem object created.
|
|
* @pad: just padding to be 64-bit aligned.
|
|
* @offset: relatived offset value of the memory region allocated.
|
|
* - this value should be set by user.
|
|
*/
|
|
struct drm_exynos_gem_map_off {
|
|
unsigned int handle;
|
|
unsigned int pad;
|
|
uint64_t offset;
|
|
};
|
|
|
|
/**
|
|
* A structure for mapping buffer.
|
|
*
|
|
* @handle: a handle to gem object created.
|
|
* @size: memory size to be mapped.
|
|
* @mapped: having user virtual address mmaped.
|
|
* - this variable would be filled by exynos gem module
|
|
* of kernel side with user virtual address which is allocated
|
|
* by do_mmap().
|
|
*/
|
|
struct drm_exynos_gem_mmap {
|
|
unsigned int handle;
|
|
unsigned int size;
|
|
uint64_t mapped;
|
|
};
|
|
|
|
struct drm_exynos_plane_set_zpos {
|
|
__u32 plane_id;
|
|
__s32 zpos;
|
|
};
|
|
|
|
#define DRM_EXYNOS_GEM_CREATE 0x00
|
|
#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
|
|
#define DRM_EXYNOS_GEM_MMAP 0x02
|
|
/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
|
|
#define DRM_EXYNOS_PLANE_SET_ZPOS 0x06
|
|
|
|
#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
|
|
|
|
#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
|
|
|
|
#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
|
|
|
|
#define DRM_IOCTL_EXYNOS_PLANE_SET_ZPOS DRM_IOWR(DRM_COMMAND_BASE + \
|
|
DRM_EXYNOS_PLANE_SET_ZPOS, struct drm_exynos_plane_set_zpos)
|
|
|
|
/**
|
|
* Platform Specific Structure for DRM based FIMD.
|
|
*
|
|
* @timing: default video mode for initializing
|
|
* @default_win: default window layer number to be used for UI.
|
|
* @bpp: default bit per pixel.
|
|
*/
|
|
struct exynos_drm_fimd_pdata {
|
|
struct fb_videomode timing;
|
|
u32 vidcon0;
|
|
u32 vidcon1;
|
|
unsigned int default_win;
|
|
unsigned int bpp;
|
|
};
|
|
|
|
/**
|
|
* Platform Specific Structure for DRM based HDMI.
|
|
*
|
|
* @hdmi_dev: device point to specific hdmi driver.
|
|
* @mixer_dev: device point to specific mixer driver.
|
|
*
|
|
* this structure is used for common hdmi driver and each device object
|
|
* would be used to access specific device driver(hdmi or mixer driver)
|
|
*/
|
|
struct exynos_drm_common_hdmi_pd {
|
|
struct device *hdmi_dev;
|
|
struct device *mixer_dev;
|
|
};
|
|
|
|
/**
|
|
* Platform Specific Structure for DRM based HDMI core.
|
|
*
|
|
* @timing: default video mode for initializing
|
|
* @default_win: default window layer number to be used for UI.
|
|
* @bpp: default bit per pixel.
|
|
*/
|
|
struct exynos_drm_hdmi_pdata {
|
|
struct fb_videomode timing;
|
|
unsigned int default_win;
|
|
unsigned int bpp;
|
|
};
|
|
|
|
#endif
|