![Linus Walleij](/assets/img/avatar_default.png)
The #ifdefs in the MMCI driver were erroneous and just masking a bug in the U300 generic GPIO implementation. This removes the ifdefs and fixes the U300 generic GPIO instead. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
877 lines
19 KiB
C
877 lines
19 KiB
C
/*
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* linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/highmem.h>
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#include <linux/log2.h>
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#include <linux/mmc/host.h>
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#include <linux/amba/bus.h>
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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#include <linux/amba/mmci.h>
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#include <linux/regulator/consumer.h>
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#include <asm/cacheflush.h>
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#include <asm/div64.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include "mmci.h"
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#define DRIVER_NAME "mmci-pl18x"
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#define DBG(host,fmt,args...) \
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pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
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static unsigned int fmax = 515633;
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/*
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* This must be called with host->lock held
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*/
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static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
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{
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u32 clk = 0;
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if (desired) {
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if (desired >= host->mclk) {
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clk = MCI_CLK_BYPASS;
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host->cclk = host->mclk;
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} else {
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clk = host->mclk / (2 * desired) - 1;
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if (clk >= 256)
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clk = 255;
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host->cclk = host->mclk / (2 * (clk + 1));
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}
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if (host->hw_designer == 0x80)
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clk |= MCI_FCEN; /* Bug fix in ST IP block */
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clk |= MCI_CLK_ENABLE;
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/* This hasn't proven to be worthwhile */
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/* clk |= MCI_CLK_PWRSAVE; */
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}
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if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
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clk |= MCI_WIDE_BUS;
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writel(clk, host->base + MMCICLOCK);
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}
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static void
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mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
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{
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writel(0, host->base + MMCICOMMAND);
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BUG_ON(host->data);
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host->mrq = NULL;
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host->cmd = NULL;
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if (mrq->data)
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mrq->data->bytes_xfered = host->data_xfered;
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/*
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* Need to drop the host lock here; mmc_request_done may call
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* back into the driver...
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*/
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spin_unlock(&host->lock);
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mmc_request_done(host->mmc, mrq);
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spin_lock(&host->lock);
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}
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static void mmci_stop_data(struct mmci_host *host)
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{
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writel(0, host->base + MMCIDATACTRL);
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writel(0, host->base + MMCIMASK1);
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host->data = NULL;
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}
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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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{
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unsigned int datactrl, timeout, irqmask;
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unsigned long long clks;
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void __iomem *base;
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int blksz_bits;
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DBG(host, "blksz %04x blks %04x flags %08x\n",
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data->blksz, data->blocks, data->flags);
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host->data = data;
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host->size = data->blksz;
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host->data_xfered = 0;
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mmci_init_sg(host, data);
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clks = (unsigned long long)data->timeout_ns * host->cclk;
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do_div(clks, 1000000000UL);
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timeout = data->timeout_clks + (unsigned int)clks;
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base = host->base;
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writel(timeout, base + MMCIDATATIMER);
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writel(host->size, base + MMCIDATALENGTH);
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blksz_bits = ffs(data->blksz) - 1;
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BUG_ON(1 << blksz_bits != data->blksz);
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datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
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if (data->flags & MMC_DATA_READ) {
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datactrl |= MCI_DPSM_DIRECTION;
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irqmask = MCI_RXFIFOHALFFULLMASK;
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/*
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* If we have less than a FIFOSIZE of bytes to transfer,
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* trigger a PIO interrupt as soon as any data is available.
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*/
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if (host->size < MCI_FIFOSIZE)
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irqmask |= MCI_RXDATAAVLBLMASK;
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} else {
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/*
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* We don't actually need to include "FIFO empty" here
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* since its implicit in "FIFO half empty".
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*/
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irqmask = MCI_TXFIFOHALFEMPTYMASK;
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}
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writel(datactrl, base + MMCIDATACTRL);
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writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
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writel(irqmask, base + MMCIMASK1);
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}
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static void
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mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
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{
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void __iomem *base = host->base;
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DBG(host, "op %02x arg %08x flags %08x\n",
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cmd->opcode, cmd->arg, cmd->flags);
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if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
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writel(0, base + MMCICOMMAND);
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udelay(1);
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}
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c |= cmd->opcode | MCI_CPSM_ENABLE;
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136)
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c |= MCI_CPSM_LONGRSP;
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c |= MCI_CPSM_RESPONSE;
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}
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if (/*interrupt*/0)
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c |= MCI_CPSM_INTERRUPT;
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host->cmd = cmd;
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writel(cmd->arg, base + MMCIARGUMENT);
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writel(c, base + MMCICOMMAND);
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}
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static void
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mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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unsigned int status)
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{
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if (status & MCI_DATABLOCKEND) {
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host->data_xfered += data->blksz;
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}
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if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
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if (status & MCI_DATACRCFAIL)
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data->error = -EILSEQ;
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else if (status & MCI_DATATIMEOUT)
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data->error = -ETIMEDOUT;
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else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
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data->error = -EIO;
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status |= MCI_DATAEND;
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/*
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* We hit an error condition. Ensure that any data
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* partially written to a page is properly coherent.
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*/
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if (host->sg_len && data->flags & MMC_DATA_READ)
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flush_dcache_page(sg_page(host->sg_ptr));
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}
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if (status & MCI_DATAEND) {
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mmci_stop_data(host);
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if (!data->stop) {
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mmci_request_end(host, data->mrq);
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} else {
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mmci_start_command(host, data->stop, 0);
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}
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}
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}
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static void
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mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
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unsigned int status)
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{
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void __iomem *base = host->base;
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host->cmd = NULL;
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cmd->resp[0] = readl(base + MMCIRESPONSE0);
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cmd->resp[1] = readl(base + MMCIRESPONSE1);
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cmd->resp[2] = readl(base + MMCIRESPONSE2);
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cmd->resp[3] = readl(base + MMCIRESPONSE3);
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if (status & MCI_CMDTIMEOUT) {
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cmd->error = -ETIMEDOUT;
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} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
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cmd->error = -EILSEQ;
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}
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if (!cmd->data || cmd->error) {
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if (host->data)
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mmci_stop_data(host);
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mmci_request_end(host, cmd->mrq);
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} else if (!(cmd->data->flags & MMC_DATA_READ)) {
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mmci_start_data(host, cmd->data);
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}
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}
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static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
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{
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void __iomem *base = host->base;
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char *ptr = buffer;
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u32 status;
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int host_remain = host->size;
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do {
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int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
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if (count > remain)
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count = remain;
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if (count <= 0)
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break;
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readsl(base + MMCIFIFO, ptr, count >> 2);
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ptr += count;
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remain -= count;
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host_remain -= count;
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if (remain == 0)
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break;
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status = readl(base + MMCISTATUS);
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} while (status & MCI_RXDATAAVLBL);
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return ptr - buffer;
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}
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static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
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{
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void __iomem *base = host->base;
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char *ptr = buffer;
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do {
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unsigned int count, maxcnt;
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maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
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count = min(remain, maxcnt);
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writesl(base + MMCIFIFO, ptr, count >> 2);
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ptr += count;
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remain -= count;
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if (remain == 0)
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break;
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status = readl(base + MMCISTATUS);
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} while (status & MCI_TXFIFOHALFEMPTY);
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return ptr - buffer;
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}
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/*
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* PIO data transfer IRQ handler.
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*/
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static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
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{
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struct mmci_host *host = dev_id;
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void __iomem *base = host->base;
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u32 status;
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status = readl(base + MMCISTATUS);
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DBG(host, "irq1 %08x\n", status);
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do {
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unsigned long flags;
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unsigned int remain, len;
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char *buffer;
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/*
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* For write, we only need to test the half-empty flag
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* here - if the FIFO is completely empty, then by
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* definition it is more than half empty.
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*
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* For read, check for data available.
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*/
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if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
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break;
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/*
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* Map the current scatter buffer.
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*/
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buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
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remain = host->sg_ptr->length - host->sg_off;
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len = 0;
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if (status & MCI_RXACTIVE)
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len = mmci_pio_read(host, buffer, remain);
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if (status & MCI_TXACTIVE)
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len = mmci_pio_write(host, buffer, remain, status);
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/*
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* Unmap the buffer.
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*/
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mmci_kunmap_atomic(host, buffer, &flags);
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host->sg_off += len;
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host->size -= len;
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remain -= len;
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if (remain)
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break;
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/*
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* If we were reading, and we have completed this
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* page, ensure that the data cache is coherent.
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*/
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if (status & MCI_RXACTIVE)
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flush_dcache_page(sg_page(host->sg_ptr));
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if (!mmci_next_sg(host))
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break;
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status = readl(base + MMCISTATUS);
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} while (1);
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/*
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* If we're nearing the end of the read, switch to
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* "any data available" mode.
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*/
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if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
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writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
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/*
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* If we run out of data, disable the data IRQs; this
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* prevents a race where the FIFO becomes empty before
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* the chip itself has disabled the data path, and
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* stops us racing with our data end IRQ.
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*/
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if (host->size == 0) {
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writel(0, base + MMCIMASK1);
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writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
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}
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return IRQ_HANDLED;
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}
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/*
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* Handle completion of command and data transfers.
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*/
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static irqreturn_t mmci_irq(int irq, void *dev_id)
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{
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struct mmci_host *host = dev_id;
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u32 status;
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int ret = 0;
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spin_lock(&host->lock);
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do {
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struct mmc_command *cmd;
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struct mmc_data *data;
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status = readl(host->base + MMCISTATUS);
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status &= readl(host->base + MMCIMASK0);
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writel(status, host->base + MMCICLEAR);
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DBG(host, "irq0 %08x\n", status);
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data = host->data;
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if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
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MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
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mmci_data_irq(host, data, status);
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cmd = host->cmd;
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if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
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mmci_cmd_irq(host, cmd, status);
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ret = 1;
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} while (status);
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spin_unlock(&host->lock);
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return IRQ_RETVAL(ret);
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}
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static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct mmci_host *host = mmc_priv(mmc);
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unsigned long flags;
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WARN_ON(host->mrq != NULL);
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if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
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printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
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mmc_hostname(mmc), mrq->data->blksz);
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mrq->cmd->error = -EINVAL;
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mmc_request_done(mmc, mrq);
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return;
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}
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spin_lock_irqsave(&host->lock, flags);
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host->mrq = mrq;
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if (mrq->data && mrq->data->flags & MMC_DATA_READ)
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mmci_start_data(host, mrq->data);
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mmci_start_command(host, mrq->cmd, 0);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct mmci_host *host = mmc_priv(mmc);
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u32 pwr = 0;
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unsigned long flags;
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switch (ios->power_mode) {
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case MMC_POWER_OFF:
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if(host->vcc &&
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regulator_is_enabled(host->vcc))
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regulator_disable(host->vcc);
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break;
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case MMC_POWER_UP:
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#ifdef CONFIG_REGULATOR
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if (host->vcc)
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/* This implicitly enables the regulator */
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mmc_regulator_set_ocr(host->vcc, ios->vdd);
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#endif
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/*
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* The translate_vdd function is not used if you have
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* an external regulator, or your design is really weird.
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* Using it would mean sending in power control BOTH using
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* a regulator AND the 4 MMCIPWR bits. If we don't have
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* a regulator, we might have some other platform specific
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* power control behind this translate function.
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*/
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if (!host->vcc && host->plat->translate_vdd)
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pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
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/* The ST version does not have this, fall through to POWER_ON */
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if (host->hw_designer != AMBA_VENDOR_ST) {
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pwr |= MCI_PWR_UP;
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break;
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}
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case MMC_POWER_ON:
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pwr |= MCI_PWR_ON;
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break;
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}
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
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if (host->hw_designer != AMBA_VENDOR_ST)
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pwr |= MCI_ROD;
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else {
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/*
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* The ST Micro variant use the ROD bit for something
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* else and only has OD (Open Drain).
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*/
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pwr |= MCI_OD;
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}
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}
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spin_lock_irqsave(&host->lock, flags);
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mmci_set_clkreg(host, ios->clock);
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if (host->pwr != pwr) {
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host->pwr = pwr;
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writel(pwr, host->base + MMCIPOWER);
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}
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static int mmci_get_ro(struct mmc_host *mmc)
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{
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struct mmci_host *host = mmc_priv(mmc);
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if (host->gpio_wp == -ENOSYS)
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return -ENOSYS;
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return gpio_get_value(host->gpio_wp);
|
|
}
|
|
|
|
static int mmci_get_cd(struct mmc_host *mmc)
|
|
{
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
unsigned int status;
|
|
|
|
if (host->gpio_cd == -ENOSYS)
|
|
status = host->plat->status(mmc_dev(host->mmc));
|
|
else
|
|
status = gpio_get_value(host->gpio_cd);
|
|
|
|
return !status;
|
|
}
|
|
|
|
static const struct mmc_host_ops mmci_ops = {
|
|
.request = mmci_request,
|
|
.set_ios = mmci_set_ios,
|
|
.get_ro = mmci_get_ro,
|
|
.get_cd = mmci_get_cd,
|
|
};
|
|
|
|
static void mmci_check_status(unsigned long data)
|
|
{
|
|
struct mmci_host *host = (struct mmci_host *)data;
|
|
unsigned int status = mmci_get_cd(host->mmc);
|
|
|
|
if (status ^ host->oldstat)
|
|
mmc_detect_change(host->mmc, 0);
|
|
|
|
host->oldstat = status;
|
|
mod_timer(&host->timer, jiffies + HZ);
|
|
}
|
|
|
|
static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
|
|
{
|
|
struct mmci_platform_data *plat = dev->dev.platform_data;
|
|
struct mmci_host *host;
|
|
struct mmc_host *mmc;
|
|
int ret;
|
|
|
|
/* must have platform data */
|
|
if (!plat) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
ret = amba_request_regions(dev, DRIVER_NAME);
|
|
if (ret)
|
|
goto out;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
|
|
if (!mmc) {
|
|
ret = -ENOMEM;
|
|
goto rel_regions;
|
|
}
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
|
|
host->gpio_wp = -ENOSYS;
|
|
host->gpio_cd = -ENOSYS;
|
|
|
|
host->hw_designer = amba_manf(dev);
|
|
host->hw_revision = amba_rev(dev);
|
|
DBG(host, "designer ID = 0x%02x\n", host->hw_designer);
|
|
DBG(host, "revision = 0x%01x\n", host->hw_revision);
|
|
|
|
host->clk = clk_get(&dev->dev, NULL);
|
|
if (IS_ERR(host->clk)) {
|
|
ret = PTR_ERR(host->clk);
|
|
host->clk = NULL;
|
|
goto host_free;
|
|
}
|
|
|
|
ret = clk_enable(host->clk);
|
|
if (ret)
|
|
goto clk_free;
|
|
|
|
host->plat = plat;
|
|
host->mclk = clk_get_rate(host->clk);
|
|
/*
|
|
* According to the spec, mclk is max 100 MHz,
|
|
* so we try to adjust the clock down to this,
|
|
* (if possible).
|
|
*/
|
|
if (host->mclk > 100000000) {
|
|
ret = clk_set_rate(host->clk, 100000000);
|
|
if (ret < 0)
|
|
goto clk_disable;
|
|
host->mclk = clk_get_rate(host->clk);
|
|
DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
|
|
}
|
|
host->base = ioremap(dev->res.start, resource_size(&dev->res));
|
|
if (!host->base) {
|
|
ret = -ENOMEM;
|
|
goto clk_disable;
|
|
}
|
|
|
|
mmc->ops = &mmci_ops;
|
|
mmc->f_min = (host->mclk + 511) / 512;
|
|
mmc->f_max = min(host->mclk, fmax);
|
|
#ifdef CONFIG_REGULATOR
|
|
/* If we're using the regulator framework, try to fetch a regulator */
|
|
host->vcc = regulator_get(&dev->dev, "vmmc");
|
|
if (IS_ERR(host->vcc))
|
|
host->vcc = NULL;
|
|
else {
|
|
int mask = mmc_regulator_get_ocrmask(host->vcc);
|
|
|
|
if (mask < 0)
|
|
dev_err(&dev->dev, "error getting OCR mask (%d)\n",
|
|
mask);
|
|
else {
|
|
host->mmc->ocr_avail = (u32) mask;
|
|
if (plat->ocr_mask)
|
|
dev_warn(&dev->dev,
|
|
"Provided ocr_mask/setpower will not be used "
|
|
"(using regulator instead)\n");
|
|
}
|
|
}
|
|
#endif
|
|
/* Fall back to platform data if no regulator is found */
|
|
if (host->vcc == NULL)
|
|
mmc->ocr_avail = plat->ocr_mask;
|
|
mmc->caps = plat->capabilities;
|
|
|
|
/*
|
|
* We can do SGIO
|
|
*/
|
|
mmc->max_hw_segs = 16;
|
|
mmc->max_phys_segs = NR_SG;
|
|
|
|
/*
|
|
* Since we only have a 16-bit data length register, we must
|
|
* ensure that we don't exceed 2^16-1 bytes in a single request.
|
|
*/
|
|
mmc->max_req_size = 65535;
|
|
|
|
/*
|
|
* Set the maximum segment size. Since we aren't doing DMA
|
|
* (yet) we are only limited by the data length register.
|
|
*/
|
|
mmc->max_seg_size = mmc->max_req_size;
|
|
|
|
/*
|
|
* Block size can be up to 2048 bytes, but must be a power of two.
|
|
*/
|
|
mmc->max_blk_size = 2048;
|
|
|
|
/*
|
|
* No limit on the number of blocks transferred.
|
|
*/
|
|
mmc->max_blk_count = mmc->max_req_size;
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
writel(0, host->base + MMCIMASK1);
|
|
writel(0xfff, host->base + MMCICLEAR);
|
|
|
|
if (gpio_is_valid(plat->gpio_cd)) {
|
|
ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
|
|
if (ret == 0)
|
|
ret = gpio_direction_input(plat->gpio_cd);
|
|
if (ret == 0)
|
|
host->gpio_cd = plat->gpio_cd;
|
|
else if (ret != -ENOSYS)
|
|
goto err_gpio_cd;
|
|
}
|
|
if (gpio_is_valid(plat->gpio_wp)) {
|
|
ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
|
|
if (ret == 0)
|
|
ret = gpio_direction_input(plat->gpio_wp);
|
|
if (ret == 0)
|
|
host->gpio_wp = plat->gpio_wp;
|
|
else if (ret != -ENOSYS)
|
|
goto err_gpio_wp;
|
|
}
|
|
|
|
ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
|
|
if (ret)
|
|
goto unmap;
|
|
|
|
ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
|
|
if (ret)
|
|
goto irq0_free;
|
|
|
|
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
|
|
|
amba_set_drvdata(dev, mmc);
|
|
host->oldstat = mmci_get_cd(host->mmc);
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
|
|
mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
|
|
(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
|
|
|
|
init_timer(&host->timer);
|
|
host->timer.data = (unsigned long)host;
|
|
host->timer.function = mmci_check_status;
|
|
host->timer.expires = jiffies + HZ;
|
|
add_timer(&host->timer);
|
|
|
|
return 0;
|
|
|
|
irq0_free:
|
|
free_irq(dev->irq[0], host);
|
|
unmap:
|
|
if (host->gpio_wp != -ENOSYS)
|
|
gpio_free(host->gpio_wp);
|
|
err_gpio_wp:
|
|
if (host->gpio_cd != -ENOSYS)
|
|
gpio_free(host->gpio_cd);
|
|
err_gpio_cd:
|
|
iounmap(host->base);
|
|
clk_disable:
|
|
clk_disable(host->clk);
|
|
clk_free:
|
|
clk_put(host->clk);
|
|
host_free:
|
|
mmc_free_host(mmc);
|
|
rel_regions:
|
|
amba_release_regions(dev);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit mmci_remove(struct amba_device *dev)
|
|
{
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
|
|
amba_set_drvdata(dev, NULL);
|
|
|
|
if (mmc) {
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
del_timer_sync(&host->timer);
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
writel(0, host->base + MMCIMASK1);
|
|
|
|
writel(0, host->base + MMCICOMMAND);
|
|
writel(0, host->base + MMCIDATACTRL);
|
|
|
|
free_irq(dev->irq[0], host);
|
|
free_irq(dev->irq[1], host);
|
|
|
|
if (host->gpio_wp != -ENOSYS)
|
|
gpio_free(host->gpio_wp);
|
|
if (host->gpio_cd != -ENOSYS)
|
|
gpio_free(host->gpio_cd);
|
|
|
|
iounmap(host->base);
|
|
clk_disable(host->clk);
|
|
clk_put(host->clk);
|
|
|
|
if (regulator_is_enabled(host->vcc))
|
|
regulator_disable(host->vcc);
|
|
regulator_put(host->vcc);
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
amba_release_regions(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int mmci_suspend(struct amba_device *dev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc) {
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
ret = mmc_suspend_host(mmc, state);
|
|
if (ret == 0)
|
|
writel(0, host->base + MMCIMASK0);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mmci_resume(struct amba_device *dev)
|
|
{
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc) {
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
|
|
|
ret = mmc_resume_host(mmc);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define mmci_suspend NULL
|
|
#define mmci_resume NULL
|
|
#endif
|
|
|
|
static struct amba_id mmci_ids[] = {
|
|
{
|
|
.id = 0x00041180,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{
|
|
.id = 0x00041181,
|
|
.mask = 0x000fffff,
|
|
},
|
|
/* ST Micro variants */
|
|
{
|
|
.id = 0x00180180,
|
|
.mask = 0x00ffffff,
|
|
},
|
|
{
|
|
.id = 0x00280180,
|
|
.mask = 0x00ffffff,
|
|
},
|
|
{ 0, 0 },
|
|
};
|
|
|
|
static struct amba_driver mmci_driver = {
|
|
.drv = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
.probe = mmci_probe,
|
|
.remove = __devexit_p(mmci_remove),
|
|
.suspend = mmci_suspend,
|
|
.resume = mmci_resume,
|
|
.id_table = mmci_ids,
|
|
};
|
|
|
|
static int __init mmci_init(void)
|
|
{
|
|
return amba_driver_register(&mmci_driver);
|
|
}
|
|
|
|
static void __exit mmci_exit(void)
|
|
{
|
|
amba_driver_unregister(&mmci_driver);
|
|
}
|
|
|
|
module_init(mmci_init);
|
|
module_exit(mmci_exit);
|
|
module_param(fmax, uint, 0444);
|
|
|
|
MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
|
|
MODULE_LICENSE("GPL");
|