![Joe Perches](/assets/img/avatar_default.png)
Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Pierre Ossman <pierre@ossman.eu>
1170 lines
30 KiB
C
1170 lines
30 KiB
C
/*
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* linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
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*
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* Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
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* Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
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*
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* derived from pxamci.c by Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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#include <mach/mmc.h>
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#include <mach/imx-dma.h>
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#include "imxmmc.h"
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#define DRIVER_NAME "imx-mmc"
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#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
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INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
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INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
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struct imxmci_host {
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struct mmc_host *mmc;
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spinlock_t lock;
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struct resource *res;
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void __iomem *base;
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int irq;
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imx_dmach_t dma;
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volatile unsigned int imask;
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unsigned int power_mode;
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unsigned int present;
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struct imxmmc_platform_data *pdata;
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struct mmc_request *req;
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struct mmc_command *cmd;
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struct mmc_data *data;
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struct timer_list timer;
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struct tasklet_struct tasklet;
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unsigned int status_reg;
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unsigned long pending_events;
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/* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
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u16 *data_ptr;
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unsigned int data_cnt;
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atomic_t stuck_timeout;
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unsigned int dma_nents;
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unsigned int dma_size;
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unsigned int dma_dir;
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int dma_allocated;
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unsigned char actual_bus_width;
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int prev_cmd_code;
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struct clk *clk;
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};
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#define IMXMCI_PEND_IRQ_b 0
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#define IMXMCI_PEND_DMA_END_b 1
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#define IMXMCI_PEND_DMA_ERR_b 2
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#define IMXMCI_PEND_WAIT_RESP_b 3
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#define IMXMCI_PEND_DMA_DATA_b 4
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#define IMXMCI_PEND_CPU_DATA_b 5
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#define IMXMCI_PEND_CARD_XCHG_b 6
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#define IMXMCI_PEND_SET_INIT_b 7
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#define IMXMCI_PEND_STARTED_b 8
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#define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
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#define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
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#define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
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#define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
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#define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
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#define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
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#define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
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#define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
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#define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
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static void imxmci_stop_clock(struct imxmci_host *host)
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{
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int i = 0;
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u16 reg;
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
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while (i < 0x1000) {
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if (!(i & 0x7f)) {
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg | STR_STP_CLK_STOP_CLK,
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host->base + MMC_REG_STR_STP_CLK);
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}
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reg = readw(host->base + MMC_REG_STATUS);
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if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
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/* Check twice before cut */
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reg = readw(host->base + MMC_REG_STATUS);
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if (!(reg & STATUS_CARD_BUS_CLK_RUN))
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return;
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}
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i++;
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}
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dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
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}
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static int imxmci_start_clock(struct imxmci_host *host)
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{
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unsigned int trials = 0;
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unsigned int delay_limit = 128;
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unsigned long flags;
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u16 reg;
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
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clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
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/*
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* Command start of the clock, this usually succeeds in less
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* then 6 delay loops, but during card detection (low clockrate)
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* it takes up to 5000 delay loops and sometimes fails for the first time
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*/
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
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do {
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unsigned int delay = delay_limit;
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while (delay--) {
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reg = readw(host->base + MMC_REG_STATUS);
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if (reg & STATUS_CARD_BUS_CLK_RUN)
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/* Check twice before cut */
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reg = readw(host->base + MMC_REG_STATUS);
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if (reg & STATUS_CARD_BUS_CLK_RUN)
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return 0;
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if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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return 0;
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}
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local_irq_save(flags);
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/*
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* Ensure, that request is not doubled under all possible circumstances.
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* It is possible, that cock running state is missed, because some other
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* IRQ or schedule delays this function execution and the clocks has
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* been already stopped by other means (response processing, SDHC HW)
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*/
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if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg | STR_STP_CLK_START_CLK,
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host->base + MMC_REG_STR_STP_CLK);
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}
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local_irq_restore(flags);
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} while (++trials < 256);
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dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
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return -1;
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}
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static void imxmci_softreset(struct imxmci_host *host)
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{
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int i;
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/* reset sequence */
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writew(0x08, host->base + MMC_REG_STR_STP_CLK);
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writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
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for (i = 0; i < 8; i++)
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writew(0x05, host->base + MMC_REG_STR_STP_CLK);
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writew(0xff, host->base + MMC_REG_RES_TO);
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writew(512, host->base + MMC_REG_BLK_LEN);
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writew(1, host->base + MMC_REG_NOB);
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}
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static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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unsigned int *pstat, unsigned int stat_mask,
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int timeout, const char *where)
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{
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int loops = 0;
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while (!(*pstat & stat_mask)) {
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loops += 2;
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if (loops >= timeout) {
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dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
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where, *pstat, stat_mask);
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return -1;
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}
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udelay(2);
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*pstat |= readw(host->base + MMC_REG_STATUS);
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}
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if (!loops)
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return 0;
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/* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
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if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
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dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
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loops, where, *pstat, stat_mask);
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return loops;
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}
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static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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{
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unsigned int nob = data->blocks;
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unsigned int blksz = data->blksz;
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unsigned int datasz = nob * blksz;
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int i;
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if (data->flags & MMC_DATA_STREAM)
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nob = 0xffff;
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host->data = data;
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data->bytes_xfered = 0;
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writew(nob, host->base + MMC_REG_NOB);
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writew(blksz, host->base + MMC_REG_BLK_LEN);
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/*
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* DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
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* We are in big troubles for non-512 byte transfers according to note in the paragraph
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* 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
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* The situation is even more complex in reality. The SDHC in not able to handle wll
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* partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
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* This is required for SCR read at least.
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*/
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if (datasz < 512) {
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host->dma_size = datasz;
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if (data->flags & MMC_DATA_READ) {
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host->dma_dir = DMA_FROM_DEVICE;
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/* Hack to enable read SCR */
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writew(1, host->base + MMC_REG_NOB);
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writew(512, host->base + MMC_REG_BLK_LEN);
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} else {
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host->dma_dir = DMA_TO_DEVICE;
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}
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/* Convert back to virtual address */
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host->data_ptr = (u16 *)sg_virt(data->sg);
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host->data_cnt = 0;
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clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
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set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
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return;
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}
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if (data->flags & MMC_DATA_READ) {
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host->dma_dir = DMA_FROM_DEVICE;
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host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, host->dma_dir);
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imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
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host->res->start + MMC_REG_BUFFER_ACCESS,
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DMA_MODE_READ);
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/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
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CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
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} else {
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host->dma_dir = DMA_TO_DEVICE;
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host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, host->dma_dir);
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imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
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host->res->start + MMC_REG_BUFFER_ACCESS,
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DMA_MODE_WRITE);
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/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
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CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
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}
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#if 1 /* This code is there only for consistency checking and can be disabled in future */
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host->dma_size = 0;
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for (i = 0; i < host->dma_nents; i++)
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host->dma_size += data->sg[i].length;
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if (datasz > host->dma_size) {
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dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
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datasz, host->dma_size);
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}
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#endif
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host->dma_size = datasz;
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wmb();
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set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
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clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
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/* start DMA engine for read, write is delayed after initial response */
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if (host->dma_dir == DMA_FROM_DEVICE)
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imx_dma_enable(host->dma);
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}
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static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
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{
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unsigned long flags;
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u32 imask;
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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/* Ensure, that clock are stopped else command programming and start fails */
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imxmci_stop_clock(host);
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if (cmd->flags & MMC_RSP_BUSY)
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cmdat |= CMD_DAT_CONT_BUSY;
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switch (mmc_resp_type(cmd)) {
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case MMC_RSP_R1: /* short CRC, OPCODE */
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case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
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cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
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break;
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case MMC_RSP_R2: /* long 136 bit + CRC */
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cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
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break;
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case MMC_RSP_R3: /* short */
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cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
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break;
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default:
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break;
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}
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if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
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cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
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if (host->actual_bus_width == MMC_BUS_WIDTH_4)
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cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
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writew(cmd->opcode, host->base + MMC_REG_CMD);
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writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
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writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
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writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
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atomic_set(&host->stuck_timeout, 0);
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set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
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imask = IMXMCI_INT_MASK_DEFAULT;
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imask &= ~INT_MASK_END_CMD_RES;
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if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
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/* imask &= ~INT_MASK_BUF_READY; */
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imask &= ~INT_MASK_DATA_TRAN;
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if (cmdat & CMD_DAT_CONT_WRITE)
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imask &= ~INT_MASK_WRITE_OP_DONE;
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if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
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imask &= ~INT_MASK_BUF_READY;
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}
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spin_lock_irqsave(&host->lock, flags);
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host->imask = imask;
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writew(host->imask, host->base + MMC_REG_INT_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
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cmd->opcode, cmd->opcode, imask);
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imxmci_start_clock(host);
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}
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static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
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IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
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host->imask = IMXMCI_INT_MASK_DEFAULT;
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writew(host->imask, host->base + MMC_REG_INT_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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if (req && req->cmd)
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host->prev_cmd_code = req->cmd->opcode;
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host->req = NULL;
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host->cmd = NULL;
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host->data = NULL;
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mmc_request_done(host->mmc, req);
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}
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static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
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{
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struct mmc_data *data = host->data;
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int data_error;
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if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
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imx_dma_disable(host->dma);
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
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host->dma_dir);
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}
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if (stat & STATUS_ERR_MASK) {
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dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
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if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
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data->error = -EILSEQ;
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else if (stat & STATUS_TIME_OUT_READ)
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data->error = -ETIMEDOUT;
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else
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data->error = -EIO;
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} else {
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data->bytes_xfered = host->dma_size;
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}
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data_error = data->error;
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host->data = NULL;
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return data_error;
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}
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static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
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{
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struct mmc_command *cmd = host->cmd;
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int i;
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u32 a, b, c;
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struct mmc_data *data = host->data;
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if (!cmd)
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return 0;
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host->cmd = NULL;
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if (stat & STATUS_TIME_OUT_RESP) {
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dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
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cmd->error = -ETIMEDOUT;
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} else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
|
|
dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
|
|
cmd->error = -EILSEQ;
|
|
}
|
|
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
if (cmd->flags & MMC_RSP_136) {
|
|
for (i = 0; i < 4; i++) {
|
|
a = readw(host->base + MMC_REG_RES_FIFO);
|
|
b = readw(host->base + MMC_REG_RES_FIFO);
|
|
cmd->resp[i] = a << 16 | b;
|
|
}
|
|
} else {
|
|
a = readw(host->base + MMC_REG_RES_FIFO);
|
|
b = readw(host->base + MMC_REG_RES_FIFO);
|
|
c = readw(host->base + MMC_REG_RES_FIFO);
|
|
cmd->resp[0] = a << 24 | b << 8 | c >> 8;
|
|
}
|
|
}
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
|
|
cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
|
|
|
|
if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
|
|
if (host->req->data->flags & MMC_DATA_WRITE) {
|
|
|
|
/* Wait for FIFO to be empty before starting DMA write */
|
|
|
|
stat = readw(host->base + MMC_REG_STATUS);
|
|
if (imxmci_busy_wait_for_status(host, &stat,
|
|
STATUS_APPL_BUFF_FE,
|
|
40, "imxmci_cmd_done DMA WR") < 0) {
|
|
cmd->error = -EIO;
|
|
imxmci_finish_data(host, stat);
|
|
if (host->req)
|
|
imxmci_finish_request(host, host->req);
|
|
dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
|
|
stat);
|
|
return 0;
|
|
}
|
|
|
|
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
|
|
imx_dma_enable(host->dma);
|
|
}
|
|
} else {
|
|
struct mmc_request *req;
|
|
imxmci_stop_clock(host);
|
|
req = host->req;
|
|
|
|
if (data)
|
|
imxmci_finish_data(host, stat);
|
|
|
|
if (req)
|
|
imxmci_finish_request(host, req);
|
|
else
|
|
dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
|
|
{
|
|
struct mmc_data *data = host->data;
|
|
int data_error;
|
|
|
|
if (!data)
|
|
return 0;
|
|
|
|
data_error = imxmci_finish_data(host, stat);
|
|
|
|
if (host->req->stop) {
|
|
imxmci_stop_clock(host);
|
|
imxmci_start_cmd(host, host->req->stop, 0);
|
|
} else {
|
|
struct mmc_request *req;
|
|
req = host->req;
|
|
if (req)
|
|
imxmci_finish_request(host, req);
|
|
else
|
|
dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
|
|
{
|
|
int i;
|
|
int burst_len;
|
|
int trans_done = 0;
|
|
unsigned int stat = *pstat;
|
|
|
|
if (host->actual_bus_width != MMC_BUS_WIDTH_4)
|
|
burst_len = 16;
|
|
else
|
|
burst_len = 64;
|
|
|
|
/* This is unfortunately required */
|
|
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
|
|
stat);
|
|
|
|
udelay(20); /* required for clocks < 8MHz*/
|
|
|
|
if (host->dma_dir == DMA_FROM_DEVICE) {
|
|
imxmci_busy_wait_for_status(host, &stat,
|
|
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
|
|
STATUS_TIME_OUT_READ,
|
|
50, "imxmci_cpu_driven_data read");
|
|
|
|
while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
|
|
!(stat & STATUS_TIME_OUT_READ) &&
|
|
(host->data_cnt < 512)) {
|
|
|
|
udelay(20); /* required for clocks < 8MHz*/
|
|
|
|
for (i = burst_len; i >= 2 ; i -= 2) {
|
|
u16 data;
|
|
data = readw(host->base + MMC_REG_BUFFER_ACCESS);
|
|
udelay(10); /* required for clocks < 8MHz*/
|
|
if (host->data_cnt+2 <= host->dma_size) {
|
|
*(host->data_ptr++) = data;
|
|
} else {
|
|
if (host->data_cnt < host->dma_size)
|
|
*(u8 *)(host->data_ptr) = data;
|
|
}
|
|
host->data_cnt += 2;
|
|
}
|
|
|
|
stat = readw(host->base + MMC_REG_STATUS);
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
|
|
host->data_cnt, burst_len, stat);
|
|
}
|
|
|
|
if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
|
|
trans_done = 1;
|
|
|
|
if (host->dma_size & 0x1ff)
|
|
stat &= ~STATUS_CRC_READ_ERR;
|
|
|
|
if (stat & STATUS_TIME_OUT_READ) {
|
|
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
|
|
stat);
|
|
trans_done = -1;
|
|
}
|
|
|
|
} else {
|
|
imxmci_busy_wait_for_status(host, &stat,
|
|
STATUS_APPL_BUFF_FE,
|
|
20, "imxmci_cpu_driven_data write");
|
|
|
|
while ((stat & STATUS_APPL_BUFF_FE) &&
|
|
(host->data_cnt < host->dma_size)) {
|
|
if (burst_len >= host->dma_size - host->data_cnt) {
|
|
burst_len = host->dma_size - host->data_cnt;
|
|
host->data_cnt = host->dma_size;
|
|
trans_done = 1;
|
|
} else {
|
|
host->data_cnt += burst_len;
|
|
}
|
|
|
|
for (i = burst_len; i > 0 ; i -= 2)
|
|
writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
|
|
|
|
stat = readw(host->base + MMC_REG_STATUS);
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
|
|
burst_len, stat);
|
|
}
|
|
}
|
|
|
|
*pstat = stat;
|
|
|
|
return trans_done;
|
|
}
|
|
|
|
static void imxmci_dma_irq(int dma, void *devid)
|
|
{
|
|
struct imxmci_host *host = devid;
|
|
u32 stat = readw(host->base + MMC_REG_STATUS);
|
|
|
|
atomic_set(&host->stuck_timeout, 0);
|
|
host->status_reg = stat;
|
|
set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
|
|
tasklet_schedule(&host->tasklet);
|
|
}
|
|
|
|
static irqreturn_t imxmci_irq(int irq, void *devid)
|
|
{
|
|
struct imxmci_host *host = devid;
|
|
u32 stat = readw(host->base + MMC_REG_STATUS);
|
|
int handled = 1;
|
|
|
|
writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
|
|
host->base + MMC_REG_INT_MASK);
|
|
|
|
atomic_set(&host->stuck_timeout, 0);
|
|
host->status_reg = stat;
|
|
set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
|
|
set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
static void imxmci_tasklet_fnc(unsigned long data)
|
|
{
|
|
struct imxmci_host *host = (struct imxmci_host *)data;
|
|
u32 stat;
|
|
unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
|
|
int timeout = 0;
|
|
|
|
if (atomic_read(&host->stuck_timeout) > 4) {
|
|
char *what;
|
|
timeout = 1;
|
|
stat = readw(host->base + MMC_REG_STATUS);
|
|
host->status_reg = stat;
|
|
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
|
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
|
|
what = "RESP+DMA";
|
|
else
|
|
what = "RESP";
|
|
else
|
|
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
|
|
if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
|
|
what = "DATA";
|
|
else
|
|
what = "DMA";
|
|
else
|
|
what = "???";
|
|
|
|
dev_err(mmc_dev(host->mmc),
|
|
"%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
|
|
what, stat,
|
|
readw(host->base + MMC_REG_INT_MASK));
|
|
dev_err(mmc_dev(host->mmc),
|
|
"CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
|
|
readw(host->base + MMC_REG_CMD_DAT_CONT),
|
|
readw(host->base + MMC_REG_BLK_LEN),
|
|
readw(host->base + MMC_REG_NOB),
|
|
CCR(host->dma));
|
|
dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
|
|
host->cmd ? host->cmd->opcode : 0,
|
|
host->prev_cmd_code,
|
|
1 << host->actual_bus_width, host->dma_size);
|
|
}
|
|
|
|
if (!host->present || timeout)
|
|
host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
|
|
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
|
|
|
|
if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
|
|
clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
|
|
|
|
stat = readw(host->base + MMC_REG_STATUS);
|
|
/*
|
|
* This is not required in theory, but there is chance to miss some flag
|
|
* which clears automatically by mask write, FreeScale original code keeps
|
|
* stat from IRQ time so do I
|
|
*/
|
|
stat |= host->status_reg;
|
|
|
|
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
|
|
stat &= ~STATUS_CRC_READ_ERR;
|
|
|
|
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
|
|
imxmci_busy_wait_for_status(host, &stat,
|
|
STATUS_END_CMD_RESP | STATUS_ERR_MASK,
|
|
20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
|
|
}
|
|
|
|
if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
|
|
if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
|
imxmci_cmd_done(host, stat);
|
|
if (host->data && (stat & STATUS_ERR_MASK))
|
|
imxmci_data_done(host, stat);
|
|
}
|
|
|
|
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
|
|
stat |= readw(host->base + MMC_REG_STATUS);
|
|
if (imxmci_cpu_driven_data(host, &stat)) {
|
|
if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
|
|
imxmci_cmd_done(host, stat);
|
|
atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
|
|
&host->pending_events);
|
|
imxmci_data_done(host, stat);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
|
|
!test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
|
|
|
|
stat = readw(host->base + MMC_REG_STATUS);
|
|
/* Same as above */
|
|
stat |= host->status_reg;
|
|
|
|
if (host->dma_dir == DMA_TO_DEVICE)
|
|
data_dir_mask = STATUS_WRITE_OP_DONE;
|
|
else
|
|
data_dir_mask = STATUS_DATA_TRANS_DONE;
|
|
|
|
if (stat & data_dir_mask) {
|
|
clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
|
|
imxmci_data_done(host, stat);
|
|
}
|
|
}
|
|
|
|
if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
|
|
|
|
if (host->cmd)
|
|
imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
|
|
|
|
if (host->data)
|
|
imxmci_data_done(host, STATUS_TIME_OUT_READ |
|
|
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
|
|
|
|
if (host->req)
|
|
imxmci_finish_request(host, host->req);
|
|
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(100));
|
|
|
|
}
|
|
}
|
|
|
|
static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
|
|
{
|
|
struct imxmci_host *host = mmc_priv(mmc);
|
|
unsigned int cmdat;
|
|
|
|
WARN_ON(host->req != NULL);
|
|
|
|
host->req = req;
|
|
|
|
cmdat = 0;
|
|
|
|
if (req->data) {
|
|
imxmci_setup_data(host, req->data);
|
|
|
|
cmdat |= CMD_DAT_CONT_DATA_ENABLE;
|
|
|
|
if (req->data->flags & MMC_DATA_WRITE)
|
|
cmdat |= CMD_DAT_CONT_WRITE;
|
|
|
|
if (req->data->flags & MMC_DATA_STREAM)
|
|
cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
|
|
}
|
|
|
|
imxmci_start_cmd(host, req->cmd, cmdat);
|
|
}
|
|
|
|
#define CLK_RATE 19200000
|
|
|
|
static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct imxmci_host *host = mmc_priv(mmc);
|
|
int prescaler;
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4) {
|
|
host->actual_bus_width = MMC_BUS_WIDTH_4;
|
|
imx_gpio_mode(PB11_PF_SD_DAT3);
|
|
BLR(host->dma) = 0; /* burst 64 byte read/write */
|
|
} else {
|
|
host->actual_bus_width = MMC_BUS_WIDTH_1;
|
|
imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
|
|
BLR(host->dma) = 16; /* burst 16 byte read/write */
|
|
}
|
|
|
|
if (host->power_mode != ios->power_mode) {
|
|
switch (ios->power_mode) {
|
|
case MMC_POWER_OFF:
|
|
break;
|
|
case MMC_POWER_UP:
|
|
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
|
|
break;
|
|
case MMC_POWER_ON:
|
|
break;
|
|
}
|
|
host->power_mode = ios->power_mode;
|
|
}
|
|
|
|
if (ios->clock) {
|
|
unsigned int clk;
|
|
u16 reg;
|
|
|
|
/* The prescaler is 5 for PERCLK2 equal to 96MHz
|
|
* then 96MHz / 5 = 19.2 MHz
|
|
*/
|
|
clk = clk_get_rate(host->clk);
|
|
prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
|
|
switch (prescaler) {
|
|
case 0:
|
|
case 1: prescaler = 0;
|
|
break;
|
|
case 2: prescaler = 1;
|
|
break;
|
|
case 3: prescaler = 2;
|
|
break;
|
|
case 4: prescaler = 4;
|
|
break;
|
|
default:
|
|
case 5: prescaler = 5;
|
|
break;
|
|
}
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
|
|
clk, prescaler);
|
|
|
|
for (clk = 0; clk < 8; clk++) {
|
|
int x;
|
|
x = CLK_RATE / (1 << clk);
|
|
if (x <= ios->clock)
|
|
break;
|
|
}
|
|
|
|
/* enable controller */
|
|
reg = readw(host->base + MMC_REG_STR_STP_CLK);
|
|
writew(reg | STR_STP_CLK_ENABLE,
|
|
host->base + MMC_REG_STR_STP_CLK);
|
|
|
|
imxmci_stop_clock(host);
|
|
writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
|
|
/*
|
|
* Under my understanding, clock should not be started there, because it would
|
|
* initiate SDHC sequencer and send last or random command into card
|
|
*/
|
|
/* imxmci_start_clock(host); */
|
|
|
|
dev_dbg(mmc_dev(host->mmc),
|
|
"MMC_CLK_RATE: 0x%08x\n",
|
|
readw(host->base + MMC_REG_CLK_RATE));
|
|
} else {
|
|
imxmci_stop_clock(host);
|
|
}
|
|
}
|
|
|
|
static int imxmci_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct imxmci_host *host = mmc_priv(mmc);
|
|
|
|
if (host->pdata && host->pdata->get_ro)
|
|
return !!host->pdata->get_ro(mmc_dev(mmc));
|
|
/*
|
|
* Board doesn't support read only detection; let the mmc core
|
|
* decide what to do.
|
|
*/
|
|
return -ENOSYS;
|
|
}
|
|
|
|
|
|
static const struct mmc_host_ops imxmci_ops = {
|
|
.request = imxmci_request,
|
|
.set_ios = imxmci_set_ios,
|
|
.get_ro = imxmci_get_ro,
|
|
};
|
|
|
|
static void imxmci_check_status(unsigned long data)
|
|
{
|
|
struct imxmci_host *host = (struct imxmci_host *)data;
|
|
|
|
if (host->pdata && host->pdata->card_present &&
|
|
host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
|
|
host->present ^= 1;
|
|
dev_info(mmc_dev(host->mmc), "card %s\n",
|
|
host->present ? "inserted" : "removed");
|
|
|
|
set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
|
|
tasklet_schedule(&host->tasklet);
|
|
}
|
|
|
|
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
|
|
test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
|
|
atomic_inc(&host->stuck_timeout);
|
|
if (atomic_read(&host->stuck_timeout) > 4)
|
|
tasklet_schedule(&host->tasklet);
|
|
} else {
|
|
atomic_set(&host->stuck_timeout, 0);
|
|
|
|
}
|
|
|
|
mod_timer(&host->timer, jiffies + (HZ>>1));
|
|
}
|
|
|
|
static int __init imxmci_probe(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc;
|
|
struct imxmci_host *host = NULL;
|
|
struct resource *r;
|
|
int ret = 0, irq;
|
|
u16 rev_no;
|
|
|
|
printk(KERN_INFO "i.MX mmc driver\n");
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!r || irq < 0)
|
|
return -ENXIO;
|
|
|
|
r = request_mem_region(r->start, resource_size(r), pdev->name);
|
|
if (!r)
|
|
return -EBUSY;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
|
|
if (!mmc) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
mmc->ops = &imxmci_ops;
|
|
mmc->f_min = 150000;
|
|
mmc->f_max = CLK_RATE/2;
|
|
mmc->ocr_avail = MMC_VDD_32_33;
|
|
mmc->caps = MMC_CAP_4_BIT_DATA;
|
|
|
|
/* MMC core transfer sizes tunable parameters */
|
|
mmc->max_hw_segs = 64;
|
|
mmc->max_phys_segs = 64;
|
|
mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */
|
|
mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */
|
|
mmc->max_blk_size = 2048;
|
|
mmc->max_blk_count = 65535;
|
|
|
|
host = mmc_priv(mmc);
|
|
host->base = ioremap(r->start, resource_size(r));
|
|
if (!host->base) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
host->mmc = mmc;
|
|
host->dma_allocated = 0;
|
|
host->pdata = pdev->dev.platform_data;
|
|
if (!host->pdata)
|
|
dev_warn(&pdev->dev, "No platform data provided!\n");
|
|
|
|
spin_lock_init(&host->lock);
|
|
host->res = r;
|
|
host->irq = irq;
|
|
|
|
host->clk = clk_get(&pdev->dev, "perclk2");
|
|
if (IS_ERR(host->clk)) {
|
|
ret = PTR_ERR(host->clk);
|
|
goto out;
|
|
}
|
|
clk_enable(host->clk);
|
|
|
|
imx_gpio_mode(PB8_PF_SD_DAT0);
|
|
imx_gpio_mode(PB9_PF_SD_DAT1);
|
|
imx_gpio_mode(PB10_PF_SD_DAT2);
|
|
/* Configured as GPIO with pull-up to ensure right MCC card mode */
|
|
/* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
|
|
imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
|
|
/* imx_gpio_mode(PB11_PF_SD_DAT3); */
|
|
imx_gpio_mode(PB12_PF_SD_CLK);
|
|
imx_gpio_mode(PB13_PF_SD_CMD);
|
|
|
|
imxmci_softreset(host);
|
|
|
|
rev_no = readw(host->base + MMC_REG_REV_NO);
|
|
if (rev_no != 0x390) {
|
|
dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
|
|
readw(host->base + MMC_REG_REV_NO));
|
|
goto out;
|
|
}
|
|
|
|
/* recommended in data sheet */
|
|
writew(0x2db4, host->base + MMC_REG_READ_TO);
|
|
|
|
host->imask = IMXMCI_INT_MASK_DEFAULT;
|
|
writew(host->imask, host->base + MMC_REG_INT_MASK);
|
|
|
|
host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
|
|
if(host->dma < 0) {
|
|
dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
host->dma_allocated = 1;
|
|
imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
|
|
RSSR(host->dma) = DMA_REQ_SDHC;
|
|
|
|
tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
|
|
host->status_reg=0;
|
|
host->pending_events=0;
|
|
|
|
ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
|
|
if (ret)
|
|
goto out;
|
|
|
|
if (host->pdata && host->pdata->card_present)
|
|
host->present = host->pdata->card_present(mmc_dev(mmc));
|
|
else /* if there is no way to detect assume that card is present */
|
|
host->present = 1;
|
|
|
|
init_timer(&host->timer);
|
|
host->timer.data = (unsigned long)host;
|
|
host->timer.function = imxmci_check_status;
|
|
add_timer(&host->timer);
|
|
mod_timer(&host->timer, jiffies + (HZ >> 1));
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
if (host) {
|
|
if (host->dma_allocated) {
|
|
imx_dma_free(host->dma);
|
|
host->dma_allocated = 0;
|
|
}
|
|
if (host->clk) {
|
|
clk_disable(host->clk);
|
|
clk_put(host->clk);
|
|
}
|
|
if (host->base)
|
|
iounmap(host->base);
|
|
}
|
|
if (mmc)
|
|
mmc_free_host(mmc);
|
|
release_mem_region(r->start, resource_size(r));
|
|
return ret;
|
|
}
|
|
|
|
static int __exit imxmci_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (mmc) {
|
|
struct imxmci_host *host = mmc_priv(mmc);
|
|
|
|
tasklet_disable(&host->tasklet);
|
|
|
|
del_timer_sync(&host->timer);
|
|
mmc_remove_host(mmc);
|
|
|
|
free_irq(host->irq, host);
|
|
iounmap(host->base);
|
|
if (host->dma_allocated) {
|
|
imx_dma_free(host->dma);
|
|
host->dma_allocated = 0;
|
|
}
|
|
|
|
tasklet_kill(&host->tasklet);
|
|
|
|
clk_disable(host->clk);
|
|
clk_put(host->clk);
|
|
|
|
release_mem_region(host->res->start, resource_size(host->res));
|
|
|
|
mmc_free_host(mmc);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc)
|
|
ret = mmc_suspend_host(mmc, state);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int imxmci_resume(struct platform_device *dev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
struct imxmci_host *host;
|
|
int ret = 0;
|
|
|
|
if (mmc) {
|
|
host = mmc_priv(mmc);
|
|
if (host)
|
|
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
|
|
ret = mmc_resume_host(mmc);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define imxmci_suspend NULL
|
|
#define imxmci_resume NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct platform_driver imxmci_driver = {
|
|
.remove = __exit_p(imxmci_remove),
|
|
.suspend = imxmci_suspend,
|
|
.resume = imxmci_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
}
|
|
};
|
|
|
|
static int __init imxmci_init(void)
|
|
{
|
|
return platform_driver_probe(&imxmci_driver, imxmci_probe);
|
|
}
|
|
|
|
static void __exit imxmci_exit(void)
|
|
{
|
|
platform_driver_unregister(&imxmci_driver);
|
|
}
|
|
|
|
module_init(imxmci_init);
|
|
module_exit(imxmci_exit);
|
|
|
|
MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
|
|
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:imx-mmc");
|