8a336b0a4b
Background: We've found that MCEs (specifically DRAM SBEs) tend to come in bunches, especially when we are trying really hard to stress the system out. The current MCE poller uses a static interval which does not care whether it has or has not found MCEs recently. Description: This patch makes the MCE poller adjust the polling interval dynamically. If we find an MCE, poll 2x faster (down to 10 ms). When we stop finding MCEs, poll 2x slower (up to check_interval seconds). The check_interval tunable becomes the max polling interval. The "Machine check events logged" printk() is rate limited to the check_interval, which should be identical behavior to the old functionality. Result: If you start to take a lot of correctable errors (not exceptions), you log them faster and more accurately (less chance of overflowing the MCA registers). If you don't take a lot of errors, you will see no change. Alternatives: I considered simply reducing the polling interval to 10 ms immediately and keeping it there as long as we continue to find errors. This felt a bit heavy handed, but does perform significantly better for the default check_interval of 5 minutes (we're using a few seconds when testing for DRAM errors). I could be convinced to go with this, if anyone felt it was not too aggressive. Testing: I used an error-injecting DIMM to create lots of correctable DRAM errors and verified that the polling interval accelerates. The printk() only happens once per check_interval seconds. Patch: This patch is against 2.6.21-rc7. Signed-Off-By: Tim Hockin <thockin@google.com> Signed-off-by: Andi Kleen <ak@suse.de>
76 lines
2.7 KiB
Text
76 lines
2.7 KiB
Text
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Configurable sysfs parameters for the x86-64 machine check code.
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Machine checks report internal hardware error conditions detected
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by the CPU. Uncorrected errors typically cause a machine check
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(often with panic), corrected ones cause a machine check log entry.
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Machine checks are organized in banks (normally associated with
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a hardware subsystem) and subevents in a bank. The exact meaning
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of the banks and subevent is CPU specific.
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mcelog knows how to decode them.
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When you see the "Machine check errors logged" message in the system
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log then mcelog should run to collect and decode machine check entries
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from /dev/mcelog. Normally mcelog should be run regularly from a cronjob.
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Each CPU has a directory in /sys/devices/system/machinecheck/machinecheckN
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(N = CPU number)
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The directory contains some configurable entries:
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Entries:
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bankNctl
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(N bank number)
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64bit Hex bitmask enabling/disabling specific subevents for bank N
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When a bit in the bitmask is zero then the respective
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subevent will not be reported.
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By default all events are enabled.
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Note that BIOS maintain another mask to disable specific events
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per bank. This is not visible here
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The following entries appear for each CPU, but they are truly shared
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between all CPUs.
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check_interval
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How often to poll for corrected machine check errors, in seconds
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(Note output is hexademical). Default 5 minutes. When the poller
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finds MCEs it triggers an exponential speedup (poll more often) on
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the polling interval. When the poller stops finding MCEs, it
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triggers an exponential backoff (poll less often) on the polling
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interval. The check_interval variable is both the initial and
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maximum polling interval.
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tolerant
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Tolerance level. When a machine check exception occurs for a non
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corrected machine check the kernel can take different actions.
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Since machine check exceptions can happen any time it is sometimes
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risky for the kernel to kill a process because it defies
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normal kernel locking rules. The tolerance level configures
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how hard the kernel tries to recover even at some risk of deadlock.
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0: always panic,
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1: panic if deadlock possible,
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2: try to avoid panic,
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3: never panic or exit (for testing only)
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Default: 1
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Note this only makes a difference if the CPU allows recovery
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from a machine check exception. Current x86 CPUs generally do not.
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trigger
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Program to run when a machine check event is detected.
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This is an alternative to running mcelog regularly from cron
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and allows to detect events faster.
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TBD document entries for AMD threshold interrupt configuration
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For more details about the x86 machine check architecture
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see the Intel and AMD architecture manuals from their developer websites.
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For more details about the architecture see
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see http://one.firstfloor.org/~andi/mce.pdf
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