b1bf7d4d1b
Lots of gpio changes, both to core code and drivers. Changes do touch architecture code to remove the need for separate arm/gpio.h includes in most architectures. Some new drivers are added, and a number of gpio drivers are converted to use irq_domains for gpio inputs used as interrupts. Device tree support has been amended to allow multiple gpio_chips to use the same device tree node. Remaining changes are primarily bug fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPvpFBAAoJEEFnBt12D9kB50EP/0q2co+Ddlz4DWM07TLMgTw8 eCSi79+oB85RcE+0FlAo/SJu9VlYDKSLT3wMbIyycfJi3cUtOb+hay0j+wxcn4bz G2qXj2Het5rX6hFI2tSCvJfDqMwU0wEygn9a6a/bw3VGSOIVmMTmRswrbbBcFzVu 8xobviN7LANLEZyhd4Ip5YfrcWH9ABmmhZX7ihn1AJubVL47xGo0uds9ZFX1sAKB Zyr80+BeUK7mhZ74UUfQHtS+x24JD62OLM9eaQN0/BBAqBewQJlxhMakPbTGmcuO Vy3CPmZiWw6tdVWgKvxE7cIXLI4YbB2B6w2TRJBBkFAlz4RsO2bFU/ibEv1vg9YE oxAUelMj0INdY4iRT135fDJTIGauWon22Tqd2MVtun4r6fwcL0BgFYN6yCMtEqbx bpYkKTi6tdyE7k2Ph+carCIuw9SwOk/4pm1xCWC0k6YdAnRE0zykCLvAuAabpmzs i/H1jcp/F4KSYldEoDlGYG4lFZiISthxOy9l6/d4GrBj723attrmztolMfrpFLF6 XPTf7HODQFmZ6n7mBIjCg4hoqydAYyKcW7lROc7DKkEXIWOeeeA+EoTytkwPLLz5 CBLoZfDoqUT8xa2vv4MZ/+G9chSDi5vMryqEYi9tXMbVEZW31xqh6hxk0xPMcY13 qVAaRlcz49AQjWq/0vR4 =U6hj -----END PGP SIGNATURE----- Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6 Pull GPIO driver changes from Grant Likely: "Lots of gpio changes, both to core code and drivers. Changes do touch architecture code to remove the need for separate arm/gpio.h includes in most architectures. Some new drivers are added, and a number of gpio drivers are converted to use irq_domains for gpio inputs used as interrupts. Device tree support has been amended to allow multiple gpio_chips to use the same device tree node. Remaining changes are primarily bug fixes." * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: (33 commits) gpio/generic: initialize basic_mmio_gpio shadow variables properly gpiolib: Remove 'const' from data argument of gpiochip_find() gpio/rc5t583: add gpio driver for RICOH PMIC RC5T583 gpiolib: quiet gpiochip_add boot message noise gpio: mpc8xxx: Prevent NULL pointer deref in demux handler gpio/lpc32xx: Add device tree support gpio: Adjust of_xlate API to support multiple GPIO chips gpiolib: Implement devm_gpio_request_one() gpio-mcp23s08: dbg_show: fix pullup configuration display Add support for TCA6424A gpio/omap: (re)fix wakeups on level-triggered GPIOs gpio/omap: fix broken context restore for non-OFF mode transitions gpio/omap: fix missing check in *_runtime_suspend() gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume() gpio/omap: remove suspend/resume callbacks gpio/omap: remove retrigger variable in gpio_irq_handler gpio/omap: remove saved_wakeup field from struct gpio_bank gpio/omap: remove suspend_wakeup field from struct gpio_bank gpio/omap: remove saved_fallingdetect, saved_risingdetect gpio/omap: remove virtual_irq_start variable ... Conflicts: drivers/gpio/gpio-samsung.c
358 lines
9.1 KiB
C
358 lines
9.1 KiB
C
/*
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* Core driver interface to access RICOH_RC5T583 power management chip.
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*
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* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
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* Author: Laxman dewangan <ldewangan@nvidia.com>
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*
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* Based on code
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* Copyright (C) 2011 RICOH COMPANY,LTD
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef __LINUX_MFD_RC5T583_H
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#define __LINUX_MFD_RC5T583_H
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <linux/regmap.h>
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#define RC5T583_MAX_REGS 0xF8
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/* Maximum number of main interrupts */
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#define MAX_MAIN_INTERRUPT 5
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#define RC5T583_MAX_GPEDGE_REG 2
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#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
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/* Interrupt enable register */
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#define RC5T583_INT_EN_SYS1 0x19
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#define RC5T583_INT_EN_SYS2 0x1D
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#define RC5T583_INT_EN_DCDC 0x41
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#define RC5T583_INT_EN_RTC 0xED
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#define RC5T583_INT_EN_ADC1 0x90
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#define RC5T583_INT_EN_ADC2 0x91
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#define RC5T583_INT_EN_ADC3 0x92
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/* Interrupt status registers (monitor regs in Ricoh)*/
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#define RC5T583_INTC_INTPOL 0xAD
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#define RC5T583_INTC_INTEN 0xAE
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#define RC5T583_INTC_INTMON 0xAF
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#define RC5T583_INT_MON_GRP 0xAF
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#define RC5T583_INT_MON_SYS1 0x1B
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#define RC5T583_INT_MON_SYS2 0x1F
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#define RC5T583_INT_MON_DCDC 0x43
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#define RC5T583_INT_MON_RTC 0xEE
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/* Interrupt clearing registers */
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#define RC5T583_INT_IR_SYS1 0x1A
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#define RC5T583_INT_IR_SYS2 0x1E
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#define RC5T583_INT_IR_DCDC 0x42
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#define RC5T583_INT_IR_RTC 0xEE
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#define RC5T583_INT_IR_ADCL 0x94
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#define RC5T583_INT_IR_ADCH 0x95
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#define RC5T583_INT_IR_ADCEND 0x96
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#define RC5T583_INT_IR_GPIOR 0xA9
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#define RC5T583_INT_IR_GPIOF 0xAA
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/* Sleep sequence registers */
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#define RC5T583_SLPSEQ1 0x21
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#define RC5T583_SLPSEQ2 0x22
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#define RC5T583_SLPSEQ3 0x23
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#define RC5T583_SLPSEQ4 0x24
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#define RC5T583_SLPSEQ5 0x25
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#define RC5T583_SLPSEQ6 0x26
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#define RC5T583_SLPSEQ7 0x27
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#define RC5T583_SLPSEQ8 0x28
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#define RC5T583_SLPSEQ9 0x29
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#define RC5T583_SLPSEQ10 0x2A
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#define RC5T583_SLPSEQ11 0x2B
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/* Regulator registers */
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#define RC5T583_REG_DC0CTL 0x30
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#define RC5T583_REG_DC0DAC 0x31
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#define RC5T583_REG_DC0LATCTL 0x32
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#define RC5T583_REG_SR0CTL 0x33
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#define RC5T583_REG_DC1CTL 0x34
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#define RC5T583_REG_DC1DAC 0x35
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#define RC5T583_REG_DC1LATCTL 0x36
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#define RC5T583_REG_SR1CTL 0x37
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#define RC5T583_REG_DC2CTL 0x38
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#define RC5T583_REG_DC2DAC 0x39
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#define RC5T583_REG_DC2LATCTL 0x3A
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#define RC5T583_REG_SR2CTL 0x3B
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#define RC5T583_REG_DC3CTL 0x3C
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#define RC5T583_REG_DC3DAC 0x3D
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#define RC5T583_REG_DC3LATCTL 0x3E
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#define RC5T583_REG_SR3CTL 0x3F
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#define RC5T583_REG_LDOEN1 0x50
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#define RC5T583_REG_LDOEN2 0x51
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#define RC5T583_REG_LDODIS1 0x52
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#define RC5T583_REG_LDODIS2 0x53
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#define RC5T583_REG_LDO0DAC 0x54
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#define RC5T583_REG_LDO1DAC 0x55
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#define RC5T583_REG_LDO2DAC 0x56
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#define RC5T583_REG_LDO3DAC 0x57
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#define RC5T583_REG_LDO4DAC 0x58
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#define RC5T583_REG_LDO5DAC 0x59
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#define RC5T583_REG_LDO6DAC 0x5A
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#define RC5T583_REG_LDO7DAC 0x5B
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#define RC5T583_REG_LDO8DAC 0x5C
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#define RC5T583_REG_LDO9DAC 0x5D
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#define RC5T583_REG_DC0DAC_DS 0x60
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#define RC5T583_REG_DC1DAC_DS 0x61
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#define RC5T583_REG_DC2DAC_DS 0x62
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#define RC5T583_REG_DC3DAC_DS 0x63
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#define RC5T583_REG_LDO0DAC_DS 0x64
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#define RC5T583_REG_LDO1DAC_DS 0x65
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#define RC5T583_REG_LDO2DAC_DS 0x66
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#define RC5T583_REG_LDO3DAC_DS 0x67
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#define RC5T583_REG_LDO4DAC_DS 0x68
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#define RC5T583_REG_LDO5DAC_DS 0x69
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#define RC5T583_REG_LDO6DAC_DS 0x6A
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#define RC5T583_REG_LDO7DAC_DS 0x6B
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#define RC5T583_REG_LDO8DAC_DS 0x6C
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#define RC5T583_REG_LDO9DAC_DS 0x6D
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/* GPIO register base address */
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#define RC5T583_GPIO_IOSEL 0xA0
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#define RC5T583_GPIO_PDEN 0xA1
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#define RC5T583_GPIO_IOOUT 0xA2
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#define RC5T583_GPIO_PGSEL 0xA3
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#define RC5T583_GPIO_GPINV 0xA4
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#define RC5T583_GPIO_GPDEB 0xA5
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#define RC5T583_GPIO_GPEDGE1 0xA6
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#define RC5T583_GPIO_GPEDGE2 0xA7
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#define RC5T583_GPIO_EN_INT 0xA8
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#define RC5T583_GPIO_MON_IOIN 0xAB
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#define RC5T583_GPIO_GPOFUNC 0xAC
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/* RICOH_RC5T583 IRQ definitions */
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enum {
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RC5T583_IRQ_ONKEY,
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RC5T583_IRQ_ACOK,
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RC5T583_IRQ_LIDOPEN,
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RC5T583_IRQ_PREOT,
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RC5T583_IRQ_CLKSTP,
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RC5T583_IRQ_ONKEY_OFF,
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RC5T583_IRQ_WD,
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RC5T583_IRQ_EN_PWRREQ1,
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RC5T583_IRQ_EN_PWRREQ2,
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RC5T583_IRQ_PRE_VINDET,
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RC5T583_IRQ_DC0LIM,
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RC5T583_IRQ_DC1LIM,
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RC5T583_IRQ_DC2LIM,
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RC5T583_IRQ_DC3LIM,
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RC5T583_IRQ_CTC,
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RC5T583_IRQ_YALE,
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RC5T583_IRQ_DALE,
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RC5T583_IRQ_WALE,
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RC5T583_IRQ_AIN1L,
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RC5T583_IRQ_AIN2L,
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RC5T583_IRQ_AIN3L,
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RC5T583_IRQ_VBATL,
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RC5T583_IRQ_VIN3L,
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RC5T583_IRQ_VIN8L,
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RC5T583_IRQ_AIN1H,
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RC5T583_IRQ_AIN2H,
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RC5T583_IRQ_AIN3H,
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RC5T583_IRQ_VBATH,
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RC5T583_IRQ_VIN3H,
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RC5T583_IRQ_VIN8H,
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RC5T583_IRQ_ADCEND,
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RC5T583_IRQ_GPIO0,
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RC5T583_IRQ_GPIO1,
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RC5T583_IRQ_GPIO2,
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RC5T583_IRQ_GPIO3,
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RC5T583_IRQ_GPIO4,
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RC5T583_IRQ_GPIO5,
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RC5T583_IRQ_GPIO6,
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RC5T583_IRQ_GPIO7,
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/* Should be last entry */
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RC5T583_MAX_IRQS,
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};
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/* Ricoh583 gpio definitions */
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enum {
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RC5T583_GPIO0,
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RC5T583_GPIO1,
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RC5T583_GPIO2,
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RC5T583_GPIO3,
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RC5T583_GPIO4,
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RC5T583_GPIO5,
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RC5T583_GPIO6,
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RC5T583_GPIO7,
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/* Should be last entry */
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RC5T583_MAX_GPIO,
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};
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enum {
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RC5T583_DS_NONE,
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RC5T583_DS_DC0,
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RC5T583_DS_DC1,
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RC5T583_DS_DC2,
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RC5T583_DS_DC3,
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RC5T583_DS_LDO0,
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RC5T583_DS_LDO1,
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RC5T583_DS_LDO2,
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RC5T583_DS_LDO3,
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RC5T583_DS_LDO4,
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RC5T583_DS_LDO5,
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RC5T583_DS_LDO6,
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RC5T583_DS_LDO7,
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RC5T583_DS_LDO8,
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RC5T583_DS_LDO9,
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RC5T583_DS_PSO0,
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RC5T583_DS_PSO1,
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RC5T583_DS_PSO2,
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RC5T583_DS_PSO3,
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RC5T583_DS_PSO4,
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RC5T583_DS_PSO5,
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RC5T583_DS_PSO6,
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RC5T583_DS_PSO7,
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/* Should be last entry */
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RC5T583_DS_MAX,
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};
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/*
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* Ricoh pmic RC5T583 supports sleep through two external controls.
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* The output of gpios and regulator can be enable/disable through
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* this external signals.
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*/
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enum {
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RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
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RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
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};
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enum {
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RC5T583_REGULATOR_DC0,
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RC5T583_REGULATOR_DC1,
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RC5T583_REGULATOR_DC2,
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RC5T583_REGULATOR_DC3,
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RC5T583_REGULATOR_LDO0,
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RC5T583_REGULATOR_LDO1,
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RC5T583_REGULATOR_LDO2,
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RC5T583_REGULATOR_LDO3,
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RC5T583_REGULATOR_LDO4,
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RC5T583_REGULATOR_LDO5,
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RC5T583_REGULATOR_LDO6,
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RC5T583_REGULATOR_LDO7,
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RC5T583_REGULATOR_LDO8,
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RC5T583_REGULATOR_LDO9,
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/* Should be last entry */
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RC5T583_REGULATOR_MAX,
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};
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struct rc5t583 {
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struct device *dev;
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struct regmap *regmap;
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int chip_irq;
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int irq_base;
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struct mutex irq_lock;
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unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
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/* For main interrupt bits in INTC */
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uint8_t intc_inten_reg;
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/* For group interrupt bits and address */
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uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
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/* For gpio edge */
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uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
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};
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/*
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* rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
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* The board specific data is provided through this structure.
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* @irq_base: Irq base number on which this device registers their interrupts.
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* @gpio_base: GPIO base from which gpio of this device will start.
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* @enable_shutdown: Enable shutdown through the input pin "shutdown".
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* @regulator_deepsleep_slot: The slot number on which device goes to sleep
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* in device sleep mode.
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* @regulator_ext_pwr_control: External power request regulator control. The
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* regulator output enable/disable is controlled by the external
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* power request input state.
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* @reg_init_data: Regulator init data.
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*/
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struct rc5t583_platform_data {
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int irq_base;
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int gpio_base;
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bool enable_shutdown;
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int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
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unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
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struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
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};
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static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
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{
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struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
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return regmap_write(rc5t583->regmap, reg, val);
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}
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static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
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{
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struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
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unsigned int ival;
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int ret;
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ret = regmap_read(rc5t583->regmap, reg, &ival);
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if (!ret)
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*val = (uint8_t)ival;
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return ret;
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}
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static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
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unsigned int bit_mask)
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{
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struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
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return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
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}
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static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
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unsigned int bit_mask)
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{
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struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
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return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
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}
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static inline int rc5t583_update(struct device *dev, unsigned int reg,
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unsigned int val, unsigned int mask)
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{
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struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
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return regmap_update_bits(rc5t583->regmap, reg, mask, val);
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}
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int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
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int ext_pwr_req, int deepsleep_slot_nr);
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int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
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int rc5t583_irq_exit(struct rc5t583 *rc5t583);
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#endif
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