![Rusty Russell](/assets/img/avatar_default.png)
This has been obsolescent for a while; time for the final push. In adjacent context, replaced old cpus_* with cpumask_*. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: David S. Miller <davem@davemloft.net> (arch/sparc) Acked-by: Chris Metcalf <cmetcalf@tilera.com> (arch/tile) Cc: user-mode-linux-devel@lists.sourceforge.net Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: Richard Kuo <rkuo@codeaurora.org> Cc: linux-hexagon@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Helge Deller <deller@gmx.de> Cc: sparclinux@vger.kernel.org
1468 lines
37 KiB
C
1468 lines
37 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2004 Mips Technologies, Inc
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* Copyright (C) 2008 Kevin D. Kissell
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*/
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#include <linux/clockchips.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/ftrace.h>
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#include <linux/slab.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <linux/atomic.h>
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#include <asm/hardirq.h>
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#include <asm/hazards.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheflush.h>
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#include <asm/time.h>
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#include <asm/addrspace.h>
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#include <asm/smtc.h>
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#include <asm/smtc_proc.h>
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/*
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* SMTC Kernel needs to manipulate low-level CPU interrupt mask
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* in do_IRQ. These are passed in setup_irq_smtc() and stored
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* in this table.
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*/
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unsigned long irq_hwmask[NR_IRQS];
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#define LOCK_MT_PRA() \
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local_irq_save(flags); \
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mtflags = dmt()
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#define UNLOCK_MT_PRA() \
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emt(mtflags); \
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local_irq_restore(flags)
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#define LOCK_CORE_PRA() \
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local_irq_save(flags); \
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mtflags = dvpe()
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#define UNLOCK_CORE_PRA() \
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evpe(mtflags); \
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local_irq_restore(flags)
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/*
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* Data structures purely associated with SMTC parallelism
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*/
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/*
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* Table for tracking ASIDs whose lifetime is prolonged.
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*/
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asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
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/*
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* Number of InterProcessor Interrupt (IPI) message buffers to allocate
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*/
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#define IPIBUF_PER_CPU 4
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struct smtc_ipi_q IPIQ[NR_CPUS];
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static struct smtc_ipi_q freeIPIq;
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/* Forward declarations */
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void ipi_decode(struct smtc_ipi *);
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static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
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static void setup_cross_vpe_interrupts(unsigned int nvpe);
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void init_smtc_stats(void);
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/* Global SMTC Status */
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unsigned int smtc_status;
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/* Boot command line configuration overrides */
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static int vpe0limit;
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static int ipibuffers;
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static int nostlb;
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static int asidmask;
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unsigned long smtc_asid_mask = 0xff;
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static int __init vpe0tcs(char *str)
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{
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get_option(&str, &vpe0limit);
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return 1;
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}
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static int __init ipibufs(char *str)
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{
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get_option(&str, &ipibuffers);
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return 1;
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}
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static int __init stlb_disable(char *s)
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{
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nostlb = 1;
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return 1;
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}
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static int __init asidmask_set(char *str)
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{
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get_option(&str, &asidmask);
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switch (asidmask) {
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case 0x1:
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case 0x3:
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case 0x7:
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case 0xf:
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case 0x1f:
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case 0x3f:
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case 0x7f:
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case 0xff:
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smtc_asid_mask = (unsigned long)asidmask;
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break;
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default:
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printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
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}
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return 1;
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}
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__setup("vpe0tcs=", vpe0tcs);
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__setup("ipibufs=", ipibufs);
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__setup("nostlb", stlb_disable);
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__setup("asidmask=", asidmask_set);
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
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static int hang_trig;
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static int __init hangtrig_enable(char *s)
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{
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hang_trig = 1;
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return 1;
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}
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__setup("hangtrig", hangtrig_enable);
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#define DEFAULT_BLOCKED_IPI_LIMIT 32
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static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
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static int __init tintq(char *str)
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{
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get_option(&str, &timerq_limit);
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return 1;
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}
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__setup("tintq=", tintq);
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static int imstuckcount[2][8];
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/* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
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static int vpemask[2][8] = {
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{0, 0, 1, 0, 0, 0, 0, 1},
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{0, 0, 0, 0, 0, 0, 0, 1}
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};
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int tcnoprog[NR_CPUS];
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static atomic_t idle_hook_initialized = ATOMIC_INIT(0);
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static int clock_hang_reported[NR_CPUS];
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#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
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/*
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* Configure shared TLB - VPC configuration bit must be set by caller
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*/
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static void smtc_configure_tlb(void)
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{
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int i, tlbsiz, vpes;
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unsigned long mvpconf0;
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unsigned long config1val;
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/* Set up ASID preservation table */
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for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
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for(i = 0; i < MAX_SMTC_ASIDS; i++) {
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smtc_live_asid[vpes][i] = 0;
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}
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}
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mvpconf0 = read_c0_mvpconf0();
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if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
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>> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
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/* If we have multiple VPEs, try to share the TLB */
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if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
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/*
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* If TLB sizing is programmable, shared TLB
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* size is the total available complement.
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* Otherwise, we have to take the sum of all
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* static VPE TLB entries.
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*/
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if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
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>> MVPCONF0_PTLBE_SHIFT)) == 0) {
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/*
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* If there's more than one VPE, there had better
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* be more than one TC, because we need one to bind
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* to each VPE in turn to be able to read
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* its configuration state!
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*/
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settc(1);
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/* Stop the TC from doing anything foolish */
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write_tc_c0_tchalt(TCHALT_H);
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mips_ihb();
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/* No need to un-Halt - that happens later anyway */
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for (i=0; i < vpes; i++) {
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write_tc_c0_tcbind(i);
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/*
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* To be 100% sure we're really getting the right
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* information, we exit the configuration state
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* and do an IHB after each rebinding.
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*/
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write_c0_mvpcontrol(
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read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
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mips_ihb();
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/*
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* Only count if the MMU Type indicated is TLB
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*/
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if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
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config1val = read_vpe_c0_config1();
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tlbsiz += ((config1val >> 25) & 0x3f) + 1;
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}
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/* Put core back in configuration state */
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write_c0_mvpcontrol(
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read_c0_mvpcontrol() | MVPCONTROL_VPC );
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mips_ihb();
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}
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}
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write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
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ehb();
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/*
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* Setup kernel data structures to use software total,
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* rather than read the per-VPE Config1 value. The values
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* for "CPU 0" gets copied to all the other CPUs as part
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* of their initialization in smtc_cpu_setup().
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*/
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/* MIPS32 limits TLB indices to 64 */
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if (tlbsiz > 64)
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tlbsiz = 64;
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cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
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smtc_status |= SMTC_TLB_SHARED;
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local_flush_tlb_all();
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printk("TLB of %d entry pairs shared by %d VPEs\n",
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tlbsiz, vpes);
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} else {
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printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
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}
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}
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}
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/*
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* Incrementally build the CPU map out of constituent MIPS MT cores,
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* using the specified available VPEs and TCs. Plaform code needs
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* to ensure that each MIPS MT core invokes this routine on reset,
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* one at a time(!).
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*
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* This version of the build_cpu_map and prepare_cpus routines assumes
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* that *all* TCs of a MIPS MT core will be used for Linux, and that
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* they will be spread across *all* available VPEs (to minimise the
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* loss of efficiency due to exception service serialization).
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* An improved version would pick up configuration information and
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* possibly leave some TCs/VPEs as "slave" processors.
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*
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* Use c0_MVPConf0 to find out how many TCs are available, setting up
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* cpu_possible_mask and the logical/physical mappings.
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*/
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int __init smtc_build_cpu_map(int start_cpu_slot)
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{
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int i, ntcs;
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/*
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* The CPU map isn't actually used for anything at this point,
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* so it's not clear what else we should do apart from set
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* everything up so that "logical" = "physical".
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*/
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ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
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for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
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set_cpu_possible(i, true);
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__cpu_number_map[i] = i;
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__cpu_logical_map[i] = i;
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}
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* Initialize map of CPUs with FPUs */
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cpus_clear(mt_fpu_cpumask);
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#endif
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/* One of those TC's is the one booting, and not a secondary... */
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printk("%i available secondary CPU TC(s)\n", i - 1);
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return i;
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}
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/*
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* Common setup before any secondaries are started
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* Make sure all CPU's are in a sensible state before we boot any of the
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* secondaries.
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*
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* For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
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* as possible across the available VPEs.
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*/
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static void smtc_tc_setup(int vpe, int tc, int cpu)
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{
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settc(tc);
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write_tc_c0_tchalt(TCHALT_H);
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mips_ihb();
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write_tc_c0_tcstatus((read_tc_c0_tcstatus()
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& ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
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| TCSTATUS_A);
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/*
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* TCContext gets an offset from the base of the IPIQ array
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* to be used in low-level code to detect the presence of
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* an active IPI queue
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*/
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write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
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/* Bind tc to vpe */
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write_tc_c0_tcbind(vpe);
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/* In general, all TCs should have the same cpu_data indications */
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memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
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/* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
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if (cpu_data[0].cputype == CPU_34K ||
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cpu_data[0].cputype == CPU_1004K)
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cpu_data[cpu].options &= ~MIPS_CPU_FPU;
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cpu_data[cpu].vpe_id = vpe;
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cpu_data[cpu].tc_id = tc;
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/* Multi-core SMTC hasn't been tested, but be prepared */
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cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
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}
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/*
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* Tweak to get Count registes in as close a sync as possible.
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* Value seems good for 34K-class cores.
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*/
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#define CP0_SKEW 8
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void smtc_prepare_cpus(int cpus)
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{
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int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
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unsigned long flags;
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unsigned long val;
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int nipi;
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struct smtc_ipi *pipi;
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/* disable interrupts so we can disable MT */
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local_irq_save(flags);
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/* disable MT so we can configure */
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dvpe();
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dmt();
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spin_lock_init(&freeIPIq.lock);
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/*
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* We probably don't have as many VPEs as we do SMP "CPUs",
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* but it's possible - and in any case we'll never use more!
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*/
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for (i=0; i<NR_CPUS; i++) {
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IPIQ[i].head = IPIQ[i].tail = NULL;
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spin_lock_init(&IPIQ[i].lock);
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IPIQ[i].depth = 0;
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IPIQ[i].resched_flag = 0; /* No reschedules queued initially */
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}
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/* cpu_data index starts at zero */
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cpu = 0;
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cpu_data[cpu].vpe_id = 0;
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cpu_data[cpu].tc_id = 0;
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cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
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cpu++;
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/* Report on boot-time options */
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mips_mt_set_cpuoptions();
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if (vpelimit > 0)
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printk("Limit of %d VPEs set\n", vpelimit);
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if (tclimit > 0)
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printk("Limit of %d TCs set\n", tclimit);
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if (nostlb) {
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printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
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}
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if (asidmask)
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printk("ASID mask value override to 0x%x\n", asidmask);
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/* Temporary */
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#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
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if (hang_trig)
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printk("Logic Analyser Trigger on suspected TC hang\n");
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#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
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/* Put MVPE's into 'configuration state' */
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write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
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val = read_c0_mvpconf0();
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nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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if (vpelimit > 0 && nvpe > vpelimit)
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nvpe = vpelimit;
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ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
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if (ntc > NR_CPUS)
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ntc = NR_CPUS;
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if (tclimit > 0 && ntc > tclimit)
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ntc = tclimit;
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slop = ntc % nvpe;
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for (i = 0; i < nvpe; i++) {
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tcpervpe[i] = ntc / nvpe;
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if (slop) {
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if((slop - i) > 0) tcpervpe[i]++;
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}
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}
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/* Handle command line override for VPE0 */
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if (vpe0limit > ntc) vpe0limit = ntc;
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if (vpe0limit > 0) {
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int slopslop;
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if (vpe0limit < tcpervpe[0]) {
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/* Reducing TC count - distribute to others */
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slop = tcpervpe[0] - vpe0limit;
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slopslop = slop % (nvpe - 1);
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tcpervpe[0] = vpe0limit;
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for (i = 1; i < nvpe; i++) {
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tcpervpe[i] += slop / (nvpe - 1);
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if(slopslop && ((slopslop - (i - 1) > 0)))
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tcpervpe[i]++;
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}
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} else if (vpe0limit > tcpervpe[0]) {
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/* Increasing TC count - steal from others */
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slop = vpe0limit - tcpervpe[0];
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slopslop = slop % (nvpe - 1);
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tcpervpe[0] = vpe0limit;
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for (i = 1; i < nvpe; i++) {
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tcpervpe[i] -= slop / (nvpe - 1);
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if(slopslop && ((slopslop - (i - 1) > 0)))
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tcpervpe[i]--;
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}
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}
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}
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/* Set up shared TLB */
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smtc_configure_tlb();
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for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
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if (tcpervpe[vpe] == 0)
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continue;
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if (vpe != 0)
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printk(", ");
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printk("VPE %d: TC", vpe);
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for (i = 0; i < tcpervpe[vpe]; i++) {
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/*
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* TC 0 is bound to VPE 0 at reset,
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* and is presumably executing this
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|
* code. Leave it alone!
|
|
*/
|
|
if (tc != 0) {
|
|
smtc_tc_setup(vpe, tc, cpu);
|
|
cpu++;
|
|
}
|
|
printk(" %d", tc);
|
|
tc++;
|
|
}
|
|
if (vpe != 0) {
|
|
/*
|
|
* Allow this VPE to control others.
|
|
*/
|
|
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
|
|
VPECONF0_MVP);
|
|
|
|
/*
|
|
* Clear any stale software interrupts from VPE's Cause
|
|
*/
|
|
write_vpe_c0_cause(0);
|
|
|
|
/*
|
|
* Clear ERL/EXL of VPEs other than 0
|
|
* and set restricted interrupt enable/mask.
|
|
*/
|
|
write_vpe_c0_status((read_vpe_c0_status()
|
|
& ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
|
|
| (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
|
|
| ST0_IE));
|
|
/*
|
|
* set config to be the same as vpe0,
|
|
* particularly kseg0 coherency alg
|
|
*/
|
|
write_vpe_c0_config(read_c0_config());
|
|
/* Clear any pending timer interrupt */
|
|
write_vpe_c0_compare(0);
|
|
/* Propagate Config7 */
|
|
write_vpe_c0_config7(read_c0_config7());
|
|
write_vpe_c0_count(read_c0_count() + CP0_SKEW);
|
|
ehb();
|
|
}
|
|
/* enable multi-threading within VPE */
|
|
write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
|
|
/* enable the VPE */
|
|
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
|
|
}
|
|
|
|
/*
|
|
* Pull any physically present but unused TCs out of circulation.
|
|
*/
|
|
while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
|
|
set_cpu_possible(tc, false);
|
|
set_cpu_present(tc, false);
|
|
tc++;
|
|
}
|
|
|
|
/* release config state */
|
|
write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
|
|
|
|
printk("\n");
|
|
|
|
/* Set up coprocessor affinity CPU mask(s) */
|
|
|
|
#ifdef CONFIG_MIPS_MT_FPAFF
|
|
for (tc = 0; tc < ntc; tc++) {
|
|
if (cpu_data[tc].options & MIPS_CPU_FPU)
|
|
cpu_set(tc, mt_fpu_cpumask);
|
|
}
|
|
#endif
|
|
|
|
/* set up ipi interrupts... */
|
|
|
|
/* If we have multiple VPEs running, set up the cross-VPE interrupt */
|
|
|
|
setup_cross_vpe_interrupts(nvpe);
|
|
|
|
/* Set up queue of free IPI "messages". */
|
|
nipi = NR_CPUS * IPIBUF_PER_CPU;
|
|
if (ipibuffers > 0)
|
|
nipi = ipibuffers;
|
|
|
|
pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
|
|
if (pipi == NULL)
|
|
panic("kmalloc of IPI message buffers failed");
|
|
else
|
|
printk("IPI buffer pool of %d buffers\n", nipi);
|
|
for (i = 0; i < nipi; i++) {
|
|
smtc_ipi_nq(&freeIPIq, pipi);
|
|
pipi++;
|
|
}
|
|
|
|
/* Arm multithreading and enable other VPEs - but all TCs are Halted */
|
|
emt(EMT_ENABLE);
|
|
evpe(EVPE_ENABLE);
|
|
local_irq_restore(flags);
|
|
/* Initialize SMTC /proc statistics/diagnostics */
|
|
init_smtc_stats();
|
|
}
|
|
|
|
|
|
/*
|
|
* Setup the PC, SP, and GP of a secondary processor and start it
|
|
* running!
|
|
* smp_bootstrap is the place to resume from
|
|
* __KSTK_TOS(idle) is apparently the stack pointer
|
|
* (unsigned long)idle->thread_info the gp
|
|
*
|
|
*/
|
|
void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
|
|
{
|
|
extern u32 kernelsp[NR_CPUS];
|
|
unsigned long flags;
|
|
int mtflags;
|
|
|
|
LOCK_MT_PRA();
|
|
if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
|
|
dvpe();
|
|
}
|
|
settc(cpu_data[cpu].tc_id);
|
|
|
|
/* pc */
|
|
write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
|
|
|
|
/* stack pointer */
|
|
kernelsp[cpu] = __KSTK_TOS(idle);
|
|
write_tc_gpr_sp(__KSTK_TOS(idle));
|
|
|
|
/* global pointer */
|
|
write_tc_gpr_gp((unsigned long)task_thread_info(idle));
|
|
|
|
smtc_status |= SMTC_MTC_ACTIVE;
|
|
write_tc_c0_tchalt(0);
|
|
if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
|
|
evpe(EVPE_ENABLE);
|
|
}
|
|
UNLOCK_MT_PRA();
|
|
}
|
|
|
|
void smtc_init_secondary(void)
|
|
{
|
|
local_irq_enable();
|
|
}
|
|
|
|
void smtc_smp_finish(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
/*
|
|
* Lowest-numbered CPU per VPE starts a clock tick.
|
|
* Like per_cpu_trap_init() hack, this assumes that
|
|
* SMTC init code assigns TCs consdecutively and
|
|
* in ascending order across available VPEs.
|
|
*/
|
|
if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
|
|
write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
|
|
|
|
printk("TC %d going on-line as CPU %d\n",
|
|
cpu_data[smp_processor_id()].tc_id, smp_processor_id());
|
|
}
|
|
|
|
void smtc_cpus_done(void)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Support for SMTC-optimized driver IRQ registration
|
|
*/
|
|
|
|
/*
|
|
* SMTC Kernel needs to manipulate low-level CPU interrupt mask
|
|
* in do_IRQ. These are passed in setup_irq_smtc() and stored
|
|
* in this table.
|
|
*/
|
|
|
|
int setup_irq_smtc(unsigned int irq, struct irqaction * new,
|
|
unsigned long hwmask)
|
|
{
|
|
#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
|
|
unsigned int vpe = current_cpu_data.vpe_id;
|
|
|
|
vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
|
|
#endif
|
|
irq_hwmask[irq] = hwmask;
|
|
|
|
return setup_irq(irq, new);
|
|
}
|
|
|
|
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
|
|
/*
|
|
* Support for IRQ affinity to TCs
|
|
*/
|
|
|
|
void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
|
|
{
|
|
/*
|
|
* If a "fast path" cache of quickly decodable affinity state
|
|
* is maintained, this is where it gets done, on a call up
|
|
* from the platform affinity code.
|
|
*/
|
|
}
|
|
|
|
void smtc_forward_irq(struct irq_data *d)
|
|
{
|
|
unsigned int irq = d->irq;
|
|
int target;
|
|
|
|
/*
|
|
* OK wise guy, now figure out how to get the IRQ
|
|
* to be serviced on an authorized "CPU".
|
|
*
|
|
* Ideally, to handle the situation where an IRQ has multiple
|
|
* eligible CPUS, we would maintain state per IRQ that would
|
|
* allow a fair distribution of service requests. Since the
|
|
* expected use model is any-or-only-one, for simplicity
|
|
* and efficiency, we just pick the easiest one to find.
|
|
*/
|
|
|
|
target = cpumask_first(d->affinity);
|
|
|
|
/*
|
|
* We depend on the platform code to have correctly processed
|
|
* IRQ affinity change requests to ensure that the IRQ affinity
|
|
* mask has been purged of bits corresponding to nonexistent and
|
|
* offline "CPUs", and to TCs bound to VPEs other than the VPE
|
|
* connected to the physical interrupt input for the interrupt
|
|
* in question. Otherwise we have a nasty problem with interrupt
|
|
* mask management. This is best handled in non-performance-critical
|
|
* platform IRQ affinity setting code, to minimize interrupt-time
|
|
* checks.
|
|
*/
|
|
|
|
/* If no one is eligible, service locally */
|
|
if (target >= NR_CPUS)
|
|
do_IRQ_no_affinity(irq);
|
|
else
|
|
smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
|
|
}
|
|
|
|
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
|
|
|
|
/*
|
|
* IPI model for SMTC is tricky, because interrupts aren't TC-specific.
|
|
* Within a VPE one TC can interrupt another by different approaches.
|
|
* The easiest to get right would probably be to make all TCs except
|
|
* the target IXMT and set a software interrupt, but an IXMT-based
|
|
* scheme requires that a handler must run before a new IPI could
|
|
* be sent, which would break the "broadcast" loops in MIPS MT.
|
|
* A more gonzo approach within a VPE is to halt the TC, extract
|
|
* its Restart, Status, and a couple of GPRs, and program the Restart
|
|
* address to emulate an interrupt.
|
|
*
|
|
* Within a VPE, one can be confident that the target TC isn't in
|
|
* a critical EXL state when halted, since the write to the Halt
|
|
* register could not have issued on the writing thread if the
|
|
* halting thread had EXL set. So k0 and k1 of the target TC
|
|
* can be used by the injection code. Across VPEs, one can't
|
|
* be certain that the target TC isn't in a critical exception
|
|
* state. So we try a two-step process of sending a software
|
|
* interrupt to the target VPE, which either handles the event
|
|
* itself (if it was the target) or injects the event within
|
|
* the VPE.
|
|
*/
|
|
|
|
static void smtc_ipi_qdump(void)
|
|
{
|
|
int i;
|
|
struct smtc_ipi *temp;
|
|
|
|
for (i = 0; i < NR_CPUS ;i++) {
|
|
pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
|
|
i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
|
|
IPIQ[i].depth);
|
|
temp = IPIQ[i].head;
|
|
|
|
while (temp != IPIQ[i].tail) {
|
|
pr_debug("%d %d %d: ", temp->type, temp->dest,
|
|
(int)temp->arg);
|
|
#ifdef SMTC_IPI_DEBUG
|
|
pr_debug("%u %lu\n", temp->sender, temp->stamp);
|
|
#else
|
|
pr_debug("\n");
|
|
#endif
|
|
temp = temp->flink;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The standard atomic.h primitives don't quite do what we want
|
|
* here: We need an atomic add-and-return-previous-value (which
|
|
* could be done with atomic_add_return and a decrement) and an
|
|
* atomic set/zero-and-return-previous-value (which can't really
|
|
* be done with the atomic.h primitives). And since this is
|
|
* MIPS MT, we can assume that we have LL/SC.
|
|
*/
|
|
static inline int atomic_postincrement(atomic_t *v)
|
|
{
|
|
unsigned long result;
|
|
|
|
unsigned long temp;
|
|
|
|
__asm__ __volatile__(
|
|
"1: ll %0, %2 \n"
|
|
" addu %1, %0, 1 \n"
|
|
" sc %1, %2 \n"
|
|
" beqz %1, 1b \n"
|
|
__WEAK_LLSC_MB
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "m" (v->counter)
|
|
: "memory");
|
|
|
|
return result;
|
|
}
|
|
|
|
void smtc_send_ipi(int cpu, int type, unsigned int action)
|
|
{
|
|
int tcstatus;
|
|
struct smtc_ipi *pipi;
|
|
unsigned long flags;
|
|
int mtflags;
|
|
unsigned long tcrestart;
|
|
extern void r4k_wait_irqoff(void), __pastwait(void);
|
|
int set_resched_flag = (type == LINUX_SMP_IPI &&
|
|
action == SMP_RESCHEDULE_YOURSELF);
|
|
|
|
if (cpu == smp_processor_id()) {
|
|
printk("Cannot Send IPI to self!\n");
|
|
return;
|
|
}
|
|
if (set_resched_flag && IPIQ[cpu].resched_flag != 0)
|
|
return; /* There is a reschedule queued already */
|
|
|
|
/* Set up a descriptor, to be delivered either promptly or queued */
|
|
pipi = smtc_ipi_dq(&freeIPIq);
|
|
if (pipi == NULL) {
|
|
bust_spinlocks(1);
|
|
mips_mt_regdump(dvpe());
|
|
panic("IPI Msg. Buffers Depleted");
|
|
}
|
|
pipi->type = type;
|
|
pipi->arg = (void *)action;
|
|
pipi->dest = cpu;
|
|
if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
|
|
/* If not on same VPE, enqueue and send cross-VPE interrupt */
|
|
IPIQ[cpu].resched_flag |= set_resched_flag;
|
|
smtc_ipi_nq(&IPIQ[cpu], pipi);
|
|
LOCK_CORE_PRA();
|
|
settc(cpu_data[cpu].tc_id);
|
|
write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
|
|
UNLOCK_CORE_PRA();
|
|
} else {
|
|
/*
|
|
* Not sufficient to do a LOCK_MT_PRA (dmt) here,
|
|
* since ASID shootdown on the other VPE may
|
|
* collide with this operation.
|
|
*/
|
|
LOCK_CORE_PRA();
|
|
settc(cpu_data[cpu].tc_id);
|
|
/* Halt the targeted TC */
|
|
write_tc_c0_tchalt(TCHALT_H);
|
|
mips_ihb();
|
|
|
|
/*
|
|
* Inspect TCStatus - if IXMT is set, we have to queue
|
|
* a message. Otherwise, we set up the "interrupt"
|
|
* of the other TC
|
|
*/
|
|
tcstatus = read_tc_c0_tcstatus();
|
|
|
|
if ((tcstatus & TCSTATUS_IXMT) != 0) {
|
|
/*
|
|
* If we're in the the irq-off version of the wait
|
|
* loop, we need to force exit from the wait and
|
|
* do a direct post of the IPI.
|
|
*/
|
|
if (cpu_wait == r4k_wait_irqoff) {
|
|
tcrestart = read_tc_c0_tcrestart();
|
|
if (tcrestart >= (unsigned long)r4k_wait_irqoff
|
|
&& tcrestart < (unsigned long)__pastwait) {
|
|
write_tc_c0_tcrestart(__pastwait);
|
|
tcstatus &= ~TCSTATUS_IXMT;
|
|
write_tc_c0_tcstatus(tcstatus);
|
|
goto postdirect;
|
|
}
|
|
}
|
|
/*
|
|
* Otherwise we queue the message for the target TC
|
|
* to pick up when he does a local_irq_restore()
|
|
*/
|
|
write_tc_c0_tchalt(0);
|
|
UNLOCK_CORE_PRA();
|
|
IPIQ[cpu].resched_flag |= set_resched_flag;
|
|
smtc_ipi_nq(&IPIQ[cpu], pipi);
|
|
} else {
|
|
postdirect:
|
|
post_direct_ipi(cpu, pipi);
|
|
write_tc_c0_tchalt(0);
|
|
UNLOCK_CORE_PRA();
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Send IPI message to Halted TC, TargTC/TargVPE already having been set
|
|
*/
|
|
static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
|
|
{
|
|
struct pt_regs *kstack;
|
|
unsigned long tcstatus;
|
|
unsigned long tcrestart;
|
|
extern u32 kernelsp[NR_CPUS];
|
|
extern void __smtc_ipi_vector(void);
|
|
//printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
|
|
|
|
/* Extract Status, EPC from halted TC */
|
|
tcstatus = read_tc_c0_tcstatus();
|
|
tcrestart = read_tc_c0_tcrestart();
|
|
/* If TCRestart indicates a WAIT instruction, advance the PC */
|
|
if ((tcrestart & 0x80000000)
|
|
&& ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
|
|
tcrestart += 4;
|
|
}
|
|
/*
|
|
* Save on TC's future kernel stack
|
|
*
|
|
* CU bit of Status is indicator that TC was
|
|
* already running on a kernel stack...
|
|
*/
|
|
if (tcstatus & ST0_CU0) {
|
|
/* Note that this "- 1" is pointer arithmetic */
|
|
kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
|
|
} else {
|
|
kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
|
|
}
|
|
|
|
kstack->cp0_epc = (long)tcrestart;
|
|
/* Save TCStatus */
|
|
kstack->cp0_tcstatus = tcstatus;
|
|
/* Pass token of operation to be performed kernel stack pad area */
|
|
kstack->pad0[4] = (unsigned long)pipi;
|
|
/* Pass address of function to be called likewise */
|
|
kstack->pad0[5] = (unsigned long)&ipi_decode;
|
|
/* Set interrupt exempt and kernel mode */
|
|
tcstatus |= TCSTATUS_IXMT;
|
|
tcstatus &= ~TCSTATUS_TKSU;
|
|
write_tc_c0_tcstatus(tcstatus);
|
|
ehb();
|
|
/* Set TC Restart address to be SMTC IPI vector */
|
|
write_tc_c0_tcrestart(__smtc_ipi_vector);
|
|
}
|
|
|
|
static void ipi_resched_interrupt(void)
|
|
{
|
|
scheduler_ipi();
|
|
}
|
|
|
|
static void ipi_call_interrupt(void)
|
|
{
|
|
/* Invoke generic function invocation code in smp.c */
|
|
smp_call_function_interrupt();
|
|
}
|
|
|
|
DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
|
|
|
|
static void __irq_entry smtc_clock_tick_interrupt(void)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
struct clock_event_device *cd;
|
|
int irq = MIPS_CPU_IRQ_BASE + 1;
|
|
|
|
irq_enter();
|
|
kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
|
|
cd = &per_cpu(mips_clockevent_device, cpu);
|
|
cd->event_handler(cd);
|
|
irq_exit();
|
|
}
|
|
|
|
void ipi_decode(struct smtc_ipi *pipi)
|
|
{
|
|
void *arg_copy = pipi->arg;
|
|
int type_copy = pipi->type;
|
|
|
|
smtc_ipi_nq(&freeIPIq, pipi);
|
|
|
|
switch (type_copy) {
|
|
case SMTC_CLOCK_TICK:
|
|
smtc_clock_tick_interrupt();
|
|
break;
|
|
|
|
case LINUX_SMP_IPI:
|
|
switch ((int)arg_copy) {
|
|
case SMP_RESCHEDULE_YOURSELF:
|
|
ipi_resched_interrupt();
|
|
break;
|
|
case SMP_CALL_FUNCTION:
|
|
ipi_call_interrupt();
|
|
break;
|
|
default:
|
|
printk("Impossible SMTC IPI Argument %p\n", arg_copy);
|
|
break;
|
|
}
|
|
break;
|
|
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
|
|
case IRQ_AFFINITY_IPI:
|
|
/*
|
|
* Accept a "forwarded" interrupt that was initially
|
|
* taken by a TC who doesn't have affinity for the IRQ.
|
|
*/
|
|
do_IRQ_no_affinity((int)arg_copy);
|
|
break;
|
|
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
|
|
default:
|
|
printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Similar to smtc_ipi_replay(), but invoked from context restore,
|
|
* so it reuses the current exception frame rather than set up a
|
|
* new one with self_ipi.
|
|
*/
|
|
|
|
void deferred_smtc_ipi(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
/*
|
|
* Test is not atomic, but much faster than a dequeue,
|
|
* and the vast majority of invocations will have a null queue.
|
|
* If irq_disabled when this was called, then any IPIs queued
|
|
* after we test last will be taken on the next irq_enable/restore.
|
|
* If interrupts were enabled, then any IPIs added after the
|
|
* last test will be taken directly.
|
|
*/
|
|
|
|
while (IPIQ[cpu].head != NULL) {
|
|
struct smtc_ipi_q *q = &IPIQ[cpu];
|
|
struct smtc_ipi *pipi;
|
|
unsigned long flags;
|
|
|
|
/*
|
|
* It may be possible we'll come in with interrupts
|
|
* already enabled.
|
|
*/
|
|
local_irq_save(flags);
|
|
spin_lock(&q->lock);
|
|
pipi = __smtc_ipi_dq(q);
|
|
spin_unlock(&q->lock);
|
|
if (pipi != NULL) {
|
|
if (pipi->type == LINUX_SMP_IPI &&
|
|
(int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
|
|
IPIQ[cpu].resched_flag = 0;
|
|
ipi_decode(pipi);
|
|
}
|
|
/*
|
|
* The use of the __raw_local restore isn't
|
|
* as obviously necessary here as in smtc_ipi_replay(),
|
|
* but it's more efficient, given that we're already
|
|
* running down the IPI queue.
|
|
*/
|
|
__arch_local_irq_restore(flags);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Cross-VPE interrupts in the SMTC prototype use "software interrupts"
|
|
* set via cross-VPE MTTR manipulation of the Cause register. It would be
|
|
* in some regards preferable to have external logic for "doorbell" hardware
|
|
* interrupts.
|
|
*/
|
|
|
|
static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
|
|
|
|
static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
|
|
{
|
|
int my_vpe = cpu_data[smp_processor_id()].vpe_id;
|
|
int my_tc = cpu_data[smp_processor_id()].tc_id;
|
|
int cpu;
|
|
struct smtc_ipi *pipi;
|
|
unsigned long tcstatus;
|
|
int sent;
|
|
unsigned long flags;
|
|
unsigned int mtflags;
|
|
unsigned int vpflags;
|
|
|
|
/*
|
|
* So long as cross-VPE interrupts are done via
|
|
* MFTR/MTTR read-modify-writes of Cause, we need
|
|
* to stop other VPEs whenever the local VPE does
|
|
* anything similar.
|
|
*/
|
|
local_irq_save(flags);
|
|
vpflags = dvpe();
|
|
clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
|
|
set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
|
|
irq_enable_hazard();
|
|
evpe(vpflags);
|
|
local_irq_restore(flags);
|
|
|
|
/*
|
|
* Cross-VPE Interrupt handler: Try to directly deliver IPIs
|
|
* queued for TCs on this VPE other than the current one.
|
|
* Return-from-interrupt should cause us to drain the queue
|
|
* for the current TC, so we ought not to have to do it explicitly here.
|
|
*/
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu_data[cpu].vpe_id != my_vpe)
|
|
continue;
|
|
|
|
pipi = smtc_ipi_dq(&IPIQ[cpu]);
|
|
if (pipi != NULL) {
|
|
if (cpu_data[cpu].tc_id != my_tc) {
|
|
sent = 0;
|
|
LOCK_MT_PRA();
|
|
settc(cpu_data[cpu].tc_id);
|
|
write_tc_c0_tchalt(TCHALT_H);
|
|
mips_ihb();
|
|
tcstatus = read_tc_c0_tcstatus();
|
|
if ((tcstatus & TCSTATUS_IXMT) == 0) {
|
|
post_direct_ipi(cpu, pipi);
|
|
sent = 1;
|
|
}
|
|
write_tc_c0_tchalt(0);
|
|
UNLOCK_MT_PRA();
|
|
if (!sent) {
|
|
smtc_ipi_req(&IPIQ[cpu], pipi);
|
|
}
|
|
} else {
|
|
/*
|
|
* ipi_decode() should be called
|
|
* with interrupts off
|
|
*/
|
|
local_irq_save(flags);
|
|
if (pipi->type == LINUX_SMP_IPI &&
|
|
(int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
|
|
IPIQ[cpu].resched_flag = 0;
|
|
ipi_decode(pipi);
|
|
local_irq_restore(flags);
|
|
}
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void ipi_irq_dispatch(void)
|
|
{
|
|
do_IRQ(cpu_ipi_irq);
|
|
}
|
|
|
|
static struct irqaction irq_ipi = {
|
|
.handler = ipi_interrupt,
|
|
.flags = IRQF_PERCPU,
|
|
.name = "SMTC_IPI"
|
|
};
|
|
|
|
static void setup_cross_vpe_interrupts(unsigned int nvpe)
|
|
{
|
|
if (nvpe < 1)
|
|
return;
|
|
|
|
if (!cpu_has_vint)
|
|
panic("SMTC Kernel requires Vectored Interrupt support");
|
|
|
|
set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
|
|
|
|
setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
|
|
|
|
irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
|
|
}
|
|
|
|
/*
|
|
* SMTC-specific hacks invoked from elsewhere in the kernel.
|
|
*/
|
|
|
|
/*
|
|
* smtc_ipi_replay is called from raw_local_irq_restore
|
|
*/
|
|
|
|
void smtc_ipi_replay(void)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
/*
|
|
* To the extent that we've ever turned interrupts off,
|
|
* we may have accumulated deferred IPIs. This is subtle.
|
|
* we should be OK: If we pick up something and dispatch
|
|
* it here, that's great. If we see nothing, but concurrent
|
|
* with this operation, another TC sends us an IPI, IXMT
|
|
* is clear, and we'll handle it as a real pseudo-interrupt
|
|
* and not a pseudo-pseudo interrupt. The important thing
|
|
* is to do the last check for queued message *after* the
|
|
* re-enabling of interrupts.
|
|
*/
|
|
while (IPIQ[cpu].head != NULL) {
|
|
struct smtc_ipi_q *q = &IPIQ[cpu];
|
|
struct smtc_ipi *pipi;
|
|
unsigned long flags;
|
|
|
|
/*
|
|
* It's just possible we'll come in with interrupts
|
|
* already enabled.
|
|
*/
|
|
local_irq_save(flags);
|
|
|
|
spin_lock(&q->lock);
|
|
pipi = __smtc_ipi_dq(q);
|
|
spin_unlock(&q->lock);
|
|
/*
|
|
** But use a raw restore here to avoid recursion.
|
|
*/
|
|
__arch_local_irq_restore(flags);
|
|
|
|
if (pipi) {
|
|
self_ipi(pipi);
|
|
smtc_cpu_stats[cpu].selfipis++;
|
|
}
|
|
}
|
|
}
|
|
|
|
EXPORT_SYMBOL(smtc_ipi_replay);
|
|
|
|
void smtc_idle_loop_hook(void)
|
|
{
|
|
#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
|
|
int im;
|
|
int flags;
|
|
int mtflags;
|
|
int bit;
|
|
int vpe;
|
|
int tc;
|
|
int hook_ntcs;
|
|
/*
|
|
* printk within DMT-protected regions can deadlock,
|
|
* so buffer diagnostic messages for later output.
|
|
*/
|
|
char *pdb_msg;
|
|
char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
|
|
|
|
if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
|
|
if (atomic_add_return(1, &idle_hook_initialized) == 1) {
|
|
int mvpconf0;
|
|
/* Tedious stuff to just do once */
|
|
mvpconf0 = read_c0_mvpconf0();
|
|
hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
|
|
if (hook_ntcs > NR_CPUS)
|
|
hook_ntcs = NR_CPUS;
|
|
for (tc = 0; tc < hook_ntcs; tc++) {
|
|
tcnoprog[tc] = 0;
|
|
clock_hang_reported[tc] = 0;
|
|
}
|
|
for (vpe = 0; vpe < 2; vpe++)
|
|
for (im = 0; im < 8; im++)
|
|
imstuckcount[vpe][im] = 0;
|
|
printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
|
|
atomic_set(&idle_hook_initialized, 1000);
|
|
} else {
|
|
/* Someone else is initializing in parallel - let 'em finish */
|
|
while (atomic_read(&idle_hook_initialized) < 1000)
|
|
;
|
|
}
|
|
}
|
|
|
|
/* Have we stupidly left IXMT set somewhere? */
|
|
if (read_c0_tcstatus() & 0x400) {
|
|
write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
|
|
ehb();
|
|
printk("Dangling IXMT in cpu_idle()\n");
|
|
}
|
|
|
|
/* Have we stupidly left an IM bit turned off? */
|
|
#define IM_LIMIT 2000
|
|
local_irq_save(flags);
|
|
mtflags = dmt();
|
|
pdb_msg = &id_ho_db_msg[0];
|
|
im = read_c0_status();
|
|
vpe = current_cpu_data.vpe_id;
|
|
for (bit = 0; bit < 8; bit++) {
|
|
/*
|
|
* In current prototype, I/O interrupts
|
|
* are masked for VPE > 0
|
|
*/
|
|
if (vpemask[vpe][bit]) {
|
|
if (!(im & (0x100 << bit)))
|
|
imstuckcount[vpe][bit]++;
|
|
else
|
|
imstuckcount[vpe][bit] = 0;
|
|
if (imstuckcount[vpe][bit] > IM_LIMIT) {
|
|
set_c0_status(0x100 << bit);
|
|
ehb();
|
|
imstuckcount[vpe][bit] = 0;
|
|
pdb_msg += sprintf(pdb_msg,
|
|
"Dangling IM %d fixed for VPE %d\n", bit,
|
|
vpe);
|
|
}
|
|
}
|
|
}
|
|
|
|
emt(mtflags);
|
|
local_irq_restore(flags);
|
|
if (pdb_msg != &id_ho_db_msg[0])
|
|
printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
|
|
#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
|
|
|
|
smtc_ipi_replay();
|
|
}
|
|
|
|
void smtc_soft_dump(void)
|
|
{
|
|
int i;
|
|
|
|
printk("Counter Interrupts taken per CPU (TC)\n");
|
|
for (i=0; i < NR_CPUS; i++) {
|
|
printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
|
|
}
|
|
printk("Self-IPI invocations:\n");
|
|
for (i=0; i < NR_CPUS; i++) {
|
|
printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
|
|
}
|
|
smtc_ipi_qdump();
|
|
printk("%d Recoveries of \"stolen\" FPU\n",
|
|
atomic_read(&smtc_fpu_recoveries));
|
|
}
|
|
|
|
|
|
/*
|
|
* TLB management routines special to SMTC
|
|
*/
|
|
|
|
void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
|
|
{
|
|
unsigned long flags, mtflags, tcstat, prevhalt, asid;
|
|
int tlb, i;
|
|
|
|
/*
|
|
* It would be nice to be able to use a spinlock here,
|
|
* but this is invoked from within TLB flush routines
|
|
* that protect themselves with DVPE, so if a lock is
|
|
* held by another TC, it'll never be freed.
|
|
*
|
|
* DVPE/DMT must not be done with interrupts enabled,
|
|
* so even so most callers will already have disabled
|
|
* them, let's be really careful...
|
|
*/
|
|
|
|
local_irq_save(flags);
|
|
if (smtc_status & SMTC_TLB_SHARED) {
|
|
mtflags = dvpe();
|
|
tlb = 0;
|
|
} else {
|
|
mtflags = dmt();
|
|
tlb = cpu_data[cpu].vpe_id;
|
|
}
|
|
asid = asid_cache(cpu);
|
|
|
|
do {
|
|
if (!((asid += ASID_INC) & ASID_MASK) ) {
|
|
if (cpu_has_vtag_icache)
|
|
flush_icache_all();
|
|
/* Traverse all online CPUs (hack requires contiguous range) */
|
|
for_each_online_cpu(i) {
|
|
/*
|
|
* We don't need to worry about our own CPU, nor those of
|
|
* CPUs who don't share our TLB.
|
|
*/
|
|
if ((i != smp_processor_id()) &&
|
|
((smtc_status & SMTC_TLB_SHARED) ||
|
|
(cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
|
|
settc(cpu_data[i].tc_id);
|
|
prevhalt = read_tc_c0_tchalt() & TCHALT_H;
|
|
if (!prevhalt) {
|
|
write_tc_c0_tchalt(TCHALT_H);
|
|
mips_ihb();
|
|
}
|
|
tcstat = read_tc_c0_tcstatus();
|
|
smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
|
|
if (!prevhalt)
|
|
write_tc_c0_tchalt(0);
|
|
}
|
|
}
|
|
if (!asid) /* fix version if needed */
|
|
asid = ASID_FIRST_VERSION;
|
|
local_flush_tlb_all(); /* start new asid cycle */
|
|
}
|
|
} while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
|
|
|
|
/*
|
|
* SMTC shares the TLB within VPEs and possibly across all VPEs.
|
|
*/
|
|
for_each_online_cpu(i) {
|
|
if ((smtc_status & SMTC_TLB_SHARED) ||
|
|
(cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
|
|
cpu_context(i, mm) = asid_cache(i) = asid;
|
|
}
|
|
|
|
if (smtc_status & SMTC_TLB_SHARED)
|
|
evpe(mtflags);
|
|
else
|
|
emt(mtflags);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/*
|
|
* Invoked from macros defined in mmu_context.h
|
|
* which must already have disabled interrupts
|
|
* and done a DVPE or DMT as appropriate.
|
|
*/
|
|
|
|
void smtc_flush_tlb_asid(unsigned long asid)
|
|
{
|
|
int entry;
|
|
unsigned long ehi;
|
|
|
|
entry = read_c0_wired();
|
|
|
|
/* Traverse all non-wired entries */
|
|
while (entry < current_cpu_data.tlbsize) {
|
|
write_c0_index(entry);
|
|
ehb();
|
|
tlb_read();
|
|
ehb();
|
|
ehi = read_c0_entryhi();
|
|
if ((ehi & ASID_MASK) == asid) {
|
|
/*
|
|
* Invalidate only entries with specified ASID,
|
|
* makiing sure all entries differ.
|
|
*/
|
|
write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
|
|
write_c0_entrylo0(0);
|
|
write_c0_entrylo1(0);
|
|
mtc0_tlbw_hazard();
|
|
tlb_write_indexed();
|
|
}
|
|
entry++;
|
|
}
|
|
write_c0_index(PARKED_INDEX);
|
|
tlbw_use_hazard();
|
|
}
|
|
|
|
/*
|
|
* Support for single-threading cache flush operations.
|
|
*/
|
|
|
|
static int halt_state_save[NR_CPUS];
|
|
|
|
/*
|
|
* To really, really be sure that nothing is being done
|
|
* by other TCs, halt them all. This code assumes that
|
|
* a DVPE has already been done, so while their Halted
|
|
* state is theoretically architecturally unstable, in
|
|
* practice, it's not going to change while we're looking
|
|
* at it.
|
|
*/
|
|
|
|
void smtc_cflush_lockdown(void)
|
|
{
|
|
int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id()) {
|
|
settc(cpu_data[cpu].tc_id);
|
|
halt_state_save[cpu] = read_tc_c0_tchalt();
|
|
write_tc_c0_tchalt(TCHALT_H);
|
|
}
|
|
}
|
|
mips_ihb();
|
|
}
|
|
|
|
/* It would be cheating to change the cpu_online states during a flush! */
|
|
|
|
void smtc_cflush_release(void)
|
|
{
|
|
int cpu;
|
|
|
|
/*
|
|
* Start with a hazard barrier to ensure
|
|
* that all CACHE ops have played through.
|
|
*/
|
|
mips_ihb();
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id()) {
|
|
settc(cpu_data[cpu].tc_id);
|
|
write_tc_c0_tchalt(halt_state_save[cpu]);
|
|
}
|
|
}
|
|
mips_ihb();
|
|
}
|