![Linus Torvalds](/assets/img/avatar_default.png)
Pull MIPS updates from Ralf Baechle: "The whole series has been sitting in -next for quite a while with no complaints. The last change to the series was before the weekend the removal of an SPI patch which Grant - even though previously acked by himself - appeared to raise objections. So I removed it until the situation is clarified. Other than that all the patches have the acks from their respective maintainers, all MIPS and x86 defconfigs are building fine and I'm not aware of any problems introduced by this series. Among the key features for this patch series is a sizable patchset for Lantiq which among other things introduces support for Lantiq's flagship product, the FALCON SOC. It also means that the opensource developers behind this patchset have overtaken Lantiq's competing inhouse development team that was working behind closed doors. Less noteworthy the ath79 patchset which adds support for a few more chip variants, cleanups and fixes. Finally the usual dose of tweaking of generic code." Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where printk spelling fixes clashed with file move and eventual removal of the printk. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits) MIPS: lantiq: remove orphaned code MIPS: Remove all -Wall and almost all -Werror usage from arch/mips. MIPS: lantiq: implement support for FALCON soc MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc MTD: MIPS: lantiq: implement OF support watchdog: MIPS: lantiq: implement OF support and minor fixes SERIAL: MIPS: lantiq: implement OF support GPIO: MIPS: lantiq: convert gpio-stp-xway to OF GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder MIPS: pci: convert lantiq driver to OF MIPS: lantiq: convert dma to platform driver MIPS: lantiq: implement support for clkdev api MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq() OF: MIPS: lantiq: implement irq_domain support OF: MIPS: lantiq: implement OF support MIPS: lantiq: drop mips_machine support OF: PCI: const usage needed by MIPS MIPS: Cavium: Remove smp_reserve_lock. MIPS: Move cache setup to setup_arch(). ...
381 lines
8.8 KiB
C
381 lines
8.8 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2000, 2001 Kanoj Sarcar
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* Copyright (C) 2000, 2001 Ralf Baechle
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* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
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*/
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/ftrace.h>
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#include <linux/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/r4k-timer.h>
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#include <asm/setup.h>
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
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int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
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EXPORT_SYMBOL(__cpu_number_map);
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int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
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EXPORT_SYMBOL(__cpu_logical_map);
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/* Number of TCs (or siblings in Intel speak) per CPU core */
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int smp_num_siblings = 1;
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EXPORT_SYMBOL(smp_num_siblings);
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/* representing the TCs (or siblings in Intel speak) of each logical CPU */
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_sibling_map);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
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cpu_set(cpu, cpu_sibling_setup_map);
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if (smp_num_siblings > 1) {
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for_each_cpu_mask(i, cpu_sibling_setup_map) {
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if (cpu_data[cpu].core == cpu_data[i].core) {
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cpu_set(i, cpu_sibling_map[cpu]);
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cpu_set(cpu, cpu_sibling_map[i]);
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}
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}
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} else
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cpu_set(cpu, cpu_sibling_map[cpu]);
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}
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struct plat_smp_ops *mp_ops;
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__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
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{
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if (mp_ops)
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printk(KERN_WARNING "Overriding previously set SMP ops\n");
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mp_ops = ops;
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}
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/*
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* First C code run on the secondary CPUs after being started up by
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* the master.
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*/
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asmlinkage __cpuinit void start_secondary(void)
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{
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unsigned int cpu;
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Only do cpu_probe for first TC of CPU */
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if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
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#endif /* CONFIG_MIPS_MT_SMTC */
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cpu_probe();
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cpu_report();
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per_cpu_trap_init(false);
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mips_clockevent_init();
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mp_ops->init_secondary();
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/*
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* XXX parity protection should be folded in here when it's converted
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* to an option instead of something based on .cputype
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*/
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calibrate_delay();
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preempt_disable();
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cpu = smp_processor_id();
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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notify_cpu_starting(cpu);
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mp_ops->smp_finish();
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set_cpu_sibling_map(cpu);
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cpu_set(cpu, cpu_callin_map);
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synchronise_count_slave();
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cpu_idle();
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}
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/*
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* Call into both interrupt handlers, as we share the IPI for them
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*/
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void __irq_entry smp_call_function_interrupt(void)
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{
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irq_enter();
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generic_smp_call_function_single_interrupt();
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generic_smp_call_function_interrupt();
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irq_exit();
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}
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static void stop_this_cpu(void *dummy)
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{
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/*
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* Remove this CPU:
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*/
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set_cpu_online(smp_processor_id(), false);
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for (;;) {
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if (cpu_wait)
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(*cpu_wait)(); /* Wait if available. */
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}
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}
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void smp_send_stop(void)
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{
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smp_call_function(stop_this_cpu, NULL, 0);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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mp_ops->cpus_done();
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synchronise_count_master();
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}
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/* called from main before smp_init() */
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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init_new_context(current, &init_mm);
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current_thread_info()->cpu = 0;
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mp_ops->prepare_cpus(max_cpus);
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set_cpu_sibling_map(0);
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#ifndef CONFIG_HOTPLUG_CPU
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init_cpu_present(cpu_possible_mask);
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#endif
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}
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/* preload SMP state for boot cpu */
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void __devinit smp_prepare_boot_cpu(void)
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{
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set_cpu_possible(0, true);
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set_cpu_online(0, true);
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cpu_set(0, cpu_callin_map);
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}
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int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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mp_ops->boot_secondary(cpu, tidle);
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/*
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* Trust is futile. We should really have timeouts ...
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*/
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while (!cpu_isset(cpu, cpu_callin_map))
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udelay(100);
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set_cpu_online(cpu, true);
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return 0;
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}
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/* Not really SMP stuff ... */
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int setup_profiling_timer(unsigned int multiplier)
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{
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return 0;
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}
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static void flush_tlb_all_ipi(void *info)
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{
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local_flush_tlb_all();
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(flush_tlb_all_ipi, NULL, 1);
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}
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static void flush_tlb_mm_ipi(void *mm)
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{
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local_flush_tlb_mm((struct mm_struct *)mm);
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}
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/*
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* Special Variant of smp_call_function for use by TLB functions:
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*
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* o No return value
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* o collapses to normal function call on UP kernels
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* o collapses to normal function call on systems with a single shared
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* primary cache.
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* o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core.
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*/
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static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
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{
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#ifndef CONFIG_MIPS_MT_SMTC
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smp_call_function(func, info, 1);
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#endif
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}
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static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
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{
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preempt_disable();
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smp_on_other_tlbs(func, info);
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func(info);
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preempt_enable();
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}
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/*
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* The following tlb flush calls are invoked when old translations are
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* being torn down, or pte attributes are changing. For single threaded
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* address spaces, a new context is obtained on the current cpu, and tlb
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* context on other cpus are invalidated to force a new context allocation
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* at switch_mm time, should the mm ever be used on other cpus. For
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* multithreaded address spaces, intercpu interrupts have to be sent.
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* Another case where intercpu interrupts are required is when the target
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* mm might be active on another cpu (eg debuggers doing the flushes on
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* behalf of debugees, kswapd stealing pages from another process etc).
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* Kanoj 07/00.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
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} else {
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != smp_processor_id() && cpu_context(cpu, mm))
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cpu_context(cpu, mm) = 0;
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}
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}
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local_flush_tlb_mm(mm);
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preempt_enable();
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}
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struct flush_tlb_data {
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struct vm_area_struct *vma;
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unsigned long addr1;
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unsigned long addr2;
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};
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static void flush_tlb_range_ipi(void *info)
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{
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struct flush_tlb_data *fd = info;
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local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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struct flush_tlb_data fd = {
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.vma = vma,
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.addr1 = start,
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.addr2 = end,
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};
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smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
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} else {
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != smp_processor_id() && cpu_context(cpu, mm))
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cpu_context(cpu, mm) = 0;
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}
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}
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local_flush_tlb_range(vma, start, end);
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preempt_enable();
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}
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static void flush_tlb_kernel_range_ipi(void *info)
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{
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struct flush_tlb_data *fd = info;
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local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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struct flush_tlb_data fd = {
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.addr1 = start,
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.addr2 = end,
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};
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on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
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}
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static void flush_tlb_page_ipi(void *info)
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{
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struct flush_tlb_data *fd = info;
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local_flush_tlb_page(fd->vma, fd->addr1);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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preempt_disable();
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if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
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struct flush_tlb_data fd = {
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.vma = vma,
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.addr1 = page,
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};
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smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
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} else {
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
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cpu_context(cpu, vma->vm_mm) = 0;
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}
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}
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local_flush_tlb_page(vma, page);
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preempt_enable();
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}
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static void flush_tlb_one_ipi(void *info)
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{
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unsigned long vaddr = (unsigned long) info;
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local_flush_tlb_one(vaddr);
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}
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void flush_tlb_one(unsigned long vaddr)
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{
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smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
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}
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EXPORT_SYMBOL(flush_tlb_page);
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EXPORT_SYMBOL(flush_tlb_one);
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