![Yong Zhang](/assets/img/avatar_default.png)
Since commit [e58aa3d2
: genirq: Run irq handlers with interrupts disabled], We run all interrupt handlers with interrupts disabled and we even check and yell when an interrupt handler returns with interrupts enabled (see commit [b738a50a
: genirq: Warn when handler enables interrupts]). So now this flag is a NOOP and can be removed. [ralf@linux-mips.org: Fixed up conflicts in arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and arch/mips/kernel/perf_event.c.] Signed-off-by: Yong Zhang <yong.zhang0@gmail.com> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2835/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
217 lines
5 KiB
C
217 lines
5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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#include <asm/cevt-r4k.h>
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/*
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* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
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* of these routines with SMTC-specific variants.
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*/
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#ifndef CONFIG_MIPS_MT_SMTC
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned int cnt;
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int res;
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
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return res;
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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void mips_set_clock_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Nothing to do ... */
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}
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DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
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int cp0_timer_irq_installed;
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#ifndef CONFIG_MIPS_MT_SMTC
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irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
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{
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const int r2 = cpu_has_mips_r2;
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struct clock_event_device *cd;
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int cpu = smp_processor_id();
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/*
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* Suckage alert:
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* Before R2 of the architecture there was no way to see if a
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* performance counter interrupt was pending, so we have to run
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* the performance counter interrupt handler anyway.
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*/
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if (handle_perf_irq(r2))
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goto out;
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/*
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* The same applies to performance counter interrupts. But with the
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* above we now know that the reason we got here must be a timer
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* interrupt. Being the paranoiacs we are we check anyway.
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*/
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if (!r2 || (read_c0_cause() & (1 << 30))) {
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/* Clear Count/Compare Interrupt */
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write_c0_compare(read_c0_compare());
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->event_handler(cd);
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}
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out:
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return IRQ_HANDLED;
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}
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#endif /* Not CONFIG_MIPS_MT_SMTC */
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struct irqaction c0_compare_irqaction = {
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.handler = c0_compare_interrupt,
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.flags = IRQF_PERCPU | IRQF_TIMER,
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.name = "timer",
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};
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void mips_event_handler(struct clock_event_device *dev)
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{
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}
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/*
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* FIXME: This doesn't hold for the relocated E9000 compare interrupt.
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*/
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static int c0_compare_int_pending(void)
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{
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return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
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}
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/*
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* Compare interrupt can be routed and latched outside the core,
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* so wait up to worst case number of cycle counter ticks for timer interrupt
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* changes to propagate to the cause register.
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*/
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#define COMPARE_INT_SEEN_TICKS 50
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int c0_compare_int_usable(void)
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{
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unsigned int delta;
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unsigned int cnt;
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/*
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* IP7 already pending? Try to clear it by acking the timer.
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*/
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if (c0_compare_int_pending()) {
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cnt = read_c0_count();
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (!c0_compare_int_pending())
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break;
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if (c0_compare_int_pending())
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return 0;
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}
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for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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}
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while ((int)(read_c0_count() - cnt) <= 0)
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; /* Wait for expiry */
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (c0_compare_int_pending())
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break;
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if (!c0_compare_int_pending())
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return 0;
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cnt = read_c0_count();
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (!c0_compare_int_pending())
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break;
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if (c0_compare_int_pending())
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return 0;
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/*
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* Feels like a real count / compare timer.
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*/
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return 1;
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}
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#ifndef CONFIG_MIPS_MT_SMTC
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int __cpuinit r4k_clockevent_init(void)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq;
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if (!cpu_has_counter || !mips_hpt_frequency)
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return -ENXIO;
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if (!c0_compare_int_usable())
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return -ENXIO;
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/*
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* With vectored interrupts things are getting platform specific.
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* get_c0_compare_int is a hook to allow a platform to return the
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* interrupt number of it's liking.
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*/
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irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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if (get_c0_compare_int)
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irq = get_c0_compare_int();
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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cd->features = CLOCK_EVT_FEAT_ONESHOT;
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clockevent_set_clock(cd, mips_hpt_frequency);
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/* Calculate the min / max delta */
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = mips_next_event;
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cd->set_mode = mips_set_clock_mode;
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cd->event_handler = mips_event_handler;
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clockevents_register_device(cd);
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if (cp0_timer_irq_installed)
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return 0;
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cp0_timer_irq_installed = 1;
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setup_irq(irq, &c0_compare_irqaction);
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return 0;
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}
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#endif /* Not CONFIG_MIPS_MT_SMTC */
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