![Thomas Gleixner](/assets/img/avatar_default.png)
Convert locks which cannot be sleeping locks in preempt-rt to raw_spinlocks. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Ingo Molnar <mingo@elte.hu>
734 lines
17 KiB
C
734 lines
17 KiB
C
/*
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* icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
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*
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* Copyright (C) 2001-2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <source@mvista.com>
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* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <source@mvista.com>
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* - New creation, NEC VR4122 and VR4131 are supported.
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* - Added support for NEC VR4111 and VR4121.
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*
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* Yoichi Yuasa <yuasa@linux-mips.org>
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* - Coped with INTASSIGN of NEC VR4133.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/vr41xx/irq.h>
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#include <asm/vr41xx/vr41xx.h>
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static void __iomem *icu1_base;
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static void __iomem *icu2_base;
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static unsigned char sysint1_assign[16] = {
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
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static unsigned char sysint2_assign[16] = {
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2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
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#define ICU1_TYPE1_BASE 0x0b000080UL
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#define ICU2_TYPE1_BASE 0x0b000200UL
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#define ICU1_TYPE2_BASE 0x0f000080UL
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#define ICU2_TYPE2_BASE 0x0f0000a0UL
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#define ICU1_SIZE 0x20
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#define ICU2_SIZE 0x1c
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#define SYSINT1REG 0x00
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#define PIUINTREG 0x02
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#define INTASSIGN0 0x04
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#define INTASSIGN1 0x06
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#define GIUINTLREG 0x08
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#define DSIUINTREG 0x0a
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#define MSYSINT1REG 0x0c
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#define MPIUINTREG 0x0e
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#define MAIUINTREG 0x10
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#define MKIUINTREG 0x12
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#define MMACINTREG 0x12
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#define MGIUINTLREG 0x14
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#define MDSIUINTREG 0x16
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#define NMIREG 0x18
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#define SOFTREG 0x1a
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#define INTASSIGN2 0x1c
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#define INTASSIGN3 0x1e
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#define SYSINT2REG 0x00
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#define GIUINTHREG 0x02
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#define FIRINTREG 0x04
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#define MSYSINT2REG 0x06
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#define MGIUINTHREG 0x08
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#define MFIRINTREG 0x0a
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#define PCIINTREG 0x0c
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#define PCIINT0 0x0001
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#define SCUINTREG 0x0e
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#define SCUINT0 0x0001
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#define CSIINTREG 0x10
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#define MPCIINTREG 0x12
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#define MSCUINTREG 0x14
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#define MCSIINTREG 0x16
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#define BCUINTREG 0x18
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#define BCUINTR 0x0001
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#define MBCUINTREG 0x1a
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#define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
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#define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
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#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
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#define icu1_read(offset) readw(icu1_base + (offset))
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#define icu1_write(offset, value) writew((value), icu1_base + (offset))
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#define icu2_read(offset) readw(icu2_base + (offset))
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#define icu2_write(offset, value) writew((value), icu2_base + (offset))
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#define INTASSIGN_MAX 4
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#define INTASSIGN_MASK 0x0007
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static inline uint16_t icu1_set(uint8_t offset, uint16_t set)
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{
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uint16_t data;
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data = icu1_read(offset);
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data |= set;
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icu1_write(offset, data);
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return data;
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}
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static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)
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{
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uint16_t data;
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data = icu1_read(offset);
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data &= ~clear;
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icu1_write(offset, data);
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return data;
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}
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static inline uint16_t icu2_set(uint8_t offset, uint16_t set)
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{
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uint16_t data;
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data = icu2_read(offset);
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data |= set;
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icu2_write(offset, data);
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return data;
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}
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static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
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{
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uint16_t data;
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data = icu2_read(offset);
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data &= ~clear;
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icu2_write(offset, data);
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return data;
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}
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void vr41xx_enable_piuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + PIU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_set(MPIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_piuint);
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void vr41xx_disable_piuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + PIU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_clear(MPIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_piuint);
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void vr41xx_enable_aiuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + AIU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_set(MAIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_aiuint);
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void vr41xx_disable_aiuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + AIU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_clear(MAIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_aiuint);
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void vr41xx_enable_kiuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + KIU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_set(MKIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_kiuint);
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void vr41xx_disable_kiuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + KIU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_clear(MKIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_kiuint);
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void vr41xx_enable_macint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_set(MMACINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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EXPORT_SYMBOL(vr41xx_enable_macint);
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void vr41xx_disable_macint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_clear(MMACINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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EXPORT_SYMBOL(vr41xx_disable_macint);
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void vr41xx_enable_dsiuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + DSIU_IRQ;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_set(MDSIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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EXPORT_SYMBOL(vr41xx_enable_dsiuint);
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void vr41xx_disable_dsiuint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + DSIU_IRQ;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu1_clear(MDSIUINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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EXPORT_SYMBOL(vr41xx_disable_dsiuint);
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void vr41xx_enable_firint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + FIR_IRQ;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_set(MFIRINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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EXPORT_SYMBOL(vr41xx_enable_firint);
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void vr41xx_disable_firint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + FIR_IRQ;
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unsigned long flags;
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_clear(MFIRINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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EXPORT_SYMBOL(vr41xx_disable_firint);
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void vr41xx_enable_pciint(void)
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{
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struct irq_desc *desc = irq_desc + PCI_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_write(MPCIINTREG, PCIINT0);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_pciint);
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void vr41xx_disable_pciint(void)
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{
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struct irq_desc *desc = irq_desc + PCI_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_write(MPCIINTREG, 0);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_pciint);
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void vr41xx_enable_scuint(void)
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{
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struct irq_desc *desc = irq_desc + SCU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_write(MSCUINTREG, SCUINT0);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_scuint);
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void vr41xx_disable_scuint(void)
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{
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struct irq_desc *desc = irq_desc + SCU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_write(MSCUINTREG, 0);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_scuint);
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void vr41xx_enable_csiint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + CSI_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_set(MCSIINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_csiint);
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void vr41xx_disable_csiint(uint16_t mask)
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{
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struct irq_desc *desc = irq_desc + CSI_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_clear(MCSIINTREG, mask);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_csiint);
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void vr41xx_enable_bcuint(void)
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{
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struct irq_desc *desc = irq_desc + BCU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_write(MBCUINTREG, BCUINTR);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_enable_bcuint);
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void vr41xx_disable_bcuint(void)
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{
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struct irq_desc *desc = irq_desc + BCU_IRQ;
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unsigned long flags;
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if (current_cpu_type() == CPU_VR4122 ||
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current_cpu_type() == CPU_VR4131 ||
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current_cpu_type() == CPU_VR4133) {
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raw_spin_lock_irqsave(&desc->lock, flags);
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icu2_write(MBCUINTREG, 0);
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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}
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}
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EXPORT_SYMBOL(vr41xx_disable_bcuint);
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static void disable_sysint1_irq(unsigned int irq)
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{
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icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
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}
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static void enable_sysint1_irq(unsigned int irq)
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{
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icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
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}
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static struct irq_chip sysint1_irq_type = {
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.name = "SYSINT1",
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.ack = disable_sysint1_irq,
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.mask = disable_sysint1_irq,
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.mask_ack = disable_sysint1_irq,
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.unmask = enable_sysint1_irq,
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};
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static void disable_sysint2_irq(unsigned int irq)
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{
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icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
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}
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static void enable_sysint2_irq(unsigned int irq)
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{
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icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
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}
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static struct irq_chip sysint2_irq_type = {
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.name = "SYSINT2",
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.ack = disable_sysint2_irq,
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.mask = disable_sysint2_irq,
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.mask_ack = disable_sysint2_irq,
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.unmask = enable_sysint2_irq,
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};
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static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
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{
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struct irq_desc *desc = irq_desc + irq;
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uint16_t intassign0, intassign1;
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unsigned int pin;
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pin = SYSINT1_IRQ_TO_PIN(irq);
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raw_spin_lock_irq(&desc->lock);
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intassign0 = icu1_read(INTASSIGN0);
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intassign1 = icu1_read(INTASSIGN1);
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switch (pin) {
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case 0:
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intassign0 &= ~INTASSIGN_MASK;
|
|
intassign0 |= (uint16_t)assign;
|
|
break;
|
|
case 1:
|
|
intassign0 &= ~(INTASSIGN_MASK << 3);
|
|
intassign0 |= (uint16_t)assign << 3;
|
|
break;
|
|
case 2:
|
|
intassign0 &= ~(INTASSIGN_MASK << 6);
|
|
intassign0 |= (uint16_t)assign << 6;
|
|
break;
|
|
case 3:
|
|
intassign0 &= ~(INTASSIGN_MASK << 9);
|
|
intassign0 |= (uint16_t)assign << 9;
|
|
break;
|
|
case 8:
|
|
intassign0 &= ~(INTASSIGN_MASK << 12);
|
|
intassign0 |= (uint16_t)assign << 12;
|
|
break;
|
|
case 9:
|
|
intassign1 &= ~INTASSIGN_MASK;
|
|
intassign1 |= (uint16_t)assign;
|
|
break;
|
|
case 11:
|
|
intassign1 &= ~(INTASSIGN_MASK << 6);
|
|
intassign1 |= (uint16_t)assign << 6;
|
|
break;
|
|
case 12:
|
|
intassign1 &= ~(INTASSIGN_MASK << 9);
|
|
intassign1 |= (uint16_t)assign << 9;
|
|
break;
|
|
default:
|
|
raw_spin_unlock_irq(&desc->lock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
sysint1_assign[pin] = assign;
|
|
icu1_write(INTASSIGN0, intassign0);
|
|
icu1_write(INTASSIGN1, intassign1);
|
|
|
|
raw_spin_unlock_irq(&desc->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
|
|
{
|
|
struct irq_desc *desc = irq_desc + irq;
|
|
uint16_t intassign2, intassign3;
|
|
unsigned int pin;
|
|
|
|
pin = SYSINT2_IRQ_TO_PIN(irq);
|
|
|
|
raw_spin_lock_irq(&desc->lock);
|
|
|
|
intassign2 = icu1_read(INTASSIGN2);
|
|
intassign3 = icu1_read(INTASSIGN3);
|
|
|
|
switch (pin) {
|
|
case 0:
|
|
intassign2 &= ~INTASSIGN_MASK;
|
|
intassign2 |= (uint16_t)assign;
|
|
break;
|
|
case 1:
|
|
intassign2 &= ~(INTASSIGN_MASK << 3);
|
|
intassign2 |= (uint16_t)assign << 3;
|
|
break;
|
|
case 3:
|
|
intassign2 &= ~(INTASSIGN_MASK << 6);
|
|
intassign2 |= (uint16_t)assign << 6;
|
|
break;
|
|
case 4:
|
|
intassign2 &= ~(INTASSIGN_MASK << 9);
|
|
intassign2 |= (uint16_t)assign << 9;
|
|
break;
|
|
case 5:
|
|
intassign2 &= ~(INTASSIGN_MASK << 12);
|
|
intassign2 |= (uint16_t)assign << 12;
|
|
break;
|
|
case 6:
|
|
intassign3 &= ~INTASSIGN_MASK;
|
|
intassign3 |= (uint16_t)assign;
|
|
break;
|
|
case 7:
|
|
intassign3 &= ~(INTASSIGN_MASK << 3);
|
|
intassign3 |= (uint16_t)assign << 3;
|
|
break;
|
|
case 8:
|
|
intassign3 &= ~(INTASSIGN_MASK << 6);
|
|
intassign3 |= (uint16_t)assign << 6;
|
|
break;
|
|
case 9:
|
|
intassign3 &= ~(INTASSIGN_MASK << 9);
|
|
intassign3 |= (uint16_t)assign << 9;
|
|
break;
|
|
case 10:
|
|
intassign3 &= ~(INTASSIGN_MASK << 12);
|
|
intassign3 |= (uint16_t)assign << 12;
|
|
break;
|
|
default:
|
|
raw_spin_unlock_irq(&desc->lock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
sysint2_assign[pin] = assign;
|
|
icu1_write(INTASSIGN2, intassign2);
|
|
icu1_write(INTASSIGN3, intassign3);
|
|
|
|
raw_spin_unlock_irq(&desc->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
|
|
{
|
|
int retval = -EINVAL;
|
|
|
|
if (current_cpu_type() != CPU_VR4133)
|
|
return -EINVAL;
|
|
|
|
if (intassign > INTASSIGN_MAX)
|
|
return -EINVAL;
|
|
|
|
if (irq >= SYSINT1_IRQ_BASE && irq <= SYSINT1_IRQ_LAST)
|
|
retval = set_sysint1_assign(irq, intassign);
|
|
else if (irq >= SYSINT2_IRQ_BASE && irq <= SYSINT2_IRQ_LAST)
|
|
retval = set_sysint2_assign(irq, intassign);
|
|
|
|
return retval;
|
|
}
|
|
|
|
EXPORT_SYMBOL(vr41xx_set_intassign);
|
|
|
|
static int icu_get_irq(unsigned int irq)
|
|
{
|
|
uint16_t pend1, pend2;
|
|
uint16_t mask1, mask2;
|
|
int i;
|
|
|
|
pend1 = icu1_read(SYSINT1REG);
|
|
mask1 = icu1_read(MSYSINT1REG);
|
|
|
|
pend2 = icu2_read(SYSINT2REG);
|
|
mask2 = icu2_read(MSYSINT2REG);
|
|
|
|
mask1 &= pend1;
|
|
mask2 &= pend2;
|
|
|
|
if (mask1) {
|
|
for (i = 0; i < 16; i++) {
|
|
if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i)))
|
|
return SYSINT1_IRQ(i);
|
|
}
|
|
}
|
|
|
|
if (mask2) {
|
|
for (i = 0; i < 16; i++) {
|
|
if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i)))
|
|
return SYSINT2_IRQ(i);
|
|
}
|
|
}
|
|
|
|
printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
|
|
|
|
atomic_inc(&irq_err_count);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int __init vr41xx_icu_init(void)
|
|
{
|
|
unsigned long icu1_start, icu2_start;
|
|
int i;
|
|
|
|
switch (current_cpu_type()) {
|
|
case CPU_VR4111:
|
|
case CPU_VR4121:
|
|
icu1_start = ICU1_TYPE1_BASE;
|
|
icu2_start = ICU2_TYPE1_BASE;
|
|
break;
|
|
case CPU_VR4122:
|
|
case CPU_VR4131:
|
|
case CPU_VR4133:
|
|
icu1_start = ICU1_TYPE2_BASE;
|
|
icu2_start = ICU2_TYPE2_BASE;
|
|
break;
|
|
default:
|
|
printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
|
|
return -EBUSY;
|
|
|
|
if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
|
|
release_mem_region(icu1_start, ICU1_SIZE);
|
|
return -EBUSY;
|
|
}
|
|
|
|
icu1_base = ioremap(icu1_start, ICU1_SIZE);
|
|
if (icu1_base == NULL) {
|
|
release_mem_region(icu1_start, ICU1_SIZE);
|
|
release_mem_region(icu2_start, ICU2_SIZE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
icu2_base = ioremap(icu2_start, ICU2_SIZE);
|
|
if (icu2_base == NULL) {
|
|
iounmap(icu1_base);
|
|
release_mem_region(icu1_start, ICU1_SIZE);
|
|
release_mem_region(icu2_start, ICU2_SIZE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
icu1_write(MSYSINT1REG, 0);
|
|
icu1_write(MGIUINTLREG, 0xffff);
|
|
|
|
icu2_write(MSYSINT2REG, 0);
|
|
icu2_write(MGIUINTHREG, 0xffff);
|
|
|
|
for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
|
|
set_irq_chip_and_handler(i, &sysint1_irq_type,
|
|
handle_level_irq);
|
|
|
|
for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
|
|
set_irq_chip_and_handler(i, &sysint2_irq_type,
|
|
handle_level_irq);
|
|
|
|
cascade_irq(INT0_IRQ, icu_get_irq);
|
|
cascade_irq(INT1_IRQ, icu_get_irq);
|
|
cascade_irq(INT2_IRQ, icu_get_irq);
|
|
cascade_irq(INT3_IRQ, icu_get_irq);
|
|
cascade_irq(INT4_IRQ, icu_get_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
core_initcall(vr41xx_icu_init);
|