![Ian Molton](/assets/img/avatar_default.png)
This patch abstracts out the CNF area code from tmio_mmc which is not present in all hardware that can use this driver. This is required so that we can support non-toshiba based hardware. ASIC3 support by Philipp Zabel Signed-off-by: Ian Molton <ian@mnementh.co.uk> Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
976 lines
24 KiB
C
976 lines
24 KiB
C
/*
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* driver/mfd/asic3.c
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*
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* Compaq ASIC3 support.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright 2001 Compaq Computer Corporation.
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* Copyright 2004-2005 Phil Blundell
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* Copyright 2007-2008 OpenedHand Ltd.
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*
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* Authors: Phil Blundell <pb@handhelds.org>,
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* Samuel Ortiz <sameo@openedhand.com>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/asic3.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/ds1wm.h>
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#include <linux/mfd/tmio.h>
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enum {
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ASIC3_CLOCK_SPI,
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ASIC3_CLOCK_OWM,
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ASIC3_CLOCK_PWM0,
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ASIC3_CLOCK_PWM1,
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ASIC3_CLOCK_LED0,
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ASIC3_CLOCK_LED1,
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ASIC3_CLOCK_LED2,
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ASIC3_CLOCK_SD_HOST,
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ASIC3_CLOCK_SD_BUS,
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ASIC3_CLOCK_SMBUS,
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ASIC3_CLOCK_EX0,
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ASIC3_CLOCK_EX1,
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};
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struct asic3_clk {
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int enabled;
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unsigned int cdex;
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unsigned long rate;
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};
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#define INIT_CDEX(_name, _rate) \
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[ASIC3_CLOCK_##_name] = { \
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.cdex = CLOCK_CDEX_##_name, \
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.rate = _rate, \
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}
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struct asic3_clk asic3_clk_init[] __initdata = {
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INIT_CDEX(SPI, 0),
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INIT_CDEX(OWM, 5000000),
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INIT_CDEX(PWM0, 0),
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INIT_CDEX(PWM1, 0),
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INIT_CDEX(LED0, 0),
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INIT_CDEX(LED1, 0),
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INIT_CDEX(LED2, 0),
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INIT_CDEX(SD_HOST, 24576000),
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INIT_CDEX(SD_BUS, 12288000),
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INIT_CDEX(SMBUS, 0),
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INIT_CDEX(EX0, 32768),
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INIT_CDEX(EX1, 24576000),
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};
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struct asic3 {
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void __iomem *mapping;
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unsigned int bus_shift;
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unsigned int irq_nr;
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unsigned int irq_base;
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spinlock_t lock;
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u16 irq_bothedge[4];
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struct gpio_chip gpio;
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struct device *dev;
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void __iomem *tmio_cnf;
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struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
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};
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static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
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static inline void asic3_write_register(struct asic3 *asic,
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unsigned int reg, u32 value)
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{
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iowrite16(value, asic->mapping +
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(reg >> asic->bus_shift));
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}
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static inline u32 asic3_read_register(struct asic3 *asic,
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unsigned int reg)
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{
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return ioread16(asic->mapping +
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(reg >> asic->bus_shift));
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}
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void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, reg);
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if (set)
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val |= bits;
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else
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val &= ~bits;
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asic3_write_register(asic, reg, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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/* IRQs */
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#define MAX_ASIC_ISR_LOOPS 20
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#define ASIC3_GPIO_BASE_INCR \
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(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
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static void asic3_irq_flip_edge(struct asic3 *asic,
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u32 base, int bit)
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{
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u16 edge;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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edge = asic3_read_register(asic,
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base + ASIC3_GPIO_EDGE_TRIGGER);
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edge ^= bit;
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asic3_write_register(asic,
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base + ASIC3_GPIO_EDGE_TRIGGER, edge);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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int iter, i;
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unsigned long flags;
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struct asic3 *asic;
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desc->chip->ack(irq);
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asic = desc->handler_data;
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for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
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u32 status;
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int bank;
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spin_lock_irqsave(&asic->lock, flags);
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status = asic3_read_register(asic,
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ASIC3_OFFSET(INTR, P_INT_STAT));
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spin_unlock_irqrestore(&asic->lock, flags);
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/* Check all ten register bits */
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if ((status & 0x3ff) == 0)
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break;
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/* Handle GPIO IRQs */
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for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
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if (status & (1 << bank)) {
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unsigned long base, istat;
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base = ASIC3_GPIO_A_BASE
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+ bank * ASIC3_GPIO_BASE_INCR;
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spin_lock_irqsave(&asic->lock, flags);
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istat = asic3_read_register(asic,
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base +
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ASIC3_GPIO_INT_STATUS);
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/* Clearing IntStatus */
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asic3_write_register(asic,
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base +
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ASIC3_GPIO_INT_STATUS, 0);
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spin_unlock_irqrestore(&asic->lock, flags);
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for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
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int bit = (1 << i);
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unsigned int irqnr;
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if (!(istat & bit))
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continue;
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irqnr = asic->irq_base +
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(ASIC3_GPIOS_PER_BANK * bank)
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+ i;
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desc = irq_to_desc(irqnr);
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desc->handle_irq(irqnr, desc);
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if (asic->irq_bothedge[bank] & bit)
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asic3_irq_flip_edge(asic, base,
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bit);
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}
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}
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}
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/* Handle remaining IRQs in the status register */
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for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
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/* They start at bit 4 and go up */
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if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
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desc = irq_to_desc(asic->irq_base + i);
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desc->handle_irq(asic->irq_base + i,
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desc);
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}
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}
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}
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if (iter >= MAX_ASIC_ISR_LOOPS)
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dev_err(asic->dev, "interrupt processing overrun\n");
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}
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static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
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{
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int n;
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n = (irq - asic->irq_base) >> 4;
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return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
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}
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static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
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{
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return (irq - asic->irq_base) & 0xf;
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}
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static void asic3_mask_gpio_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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u32 val, bank, index;
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unsigned long flags;
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bank = asic3_irq_to_bank(asic, irq);
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index = asic3_irq_to_index(asic, irq);
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spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
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val |= 1 << index;
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asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_mask_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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int regval;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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regval = asic3_read_register(asic,
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK);
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regval &= ~(ASIC3_INTMASK_MASK0 <<
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(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
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asic3_write_register(asic,
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK,
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regval);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_unmask_gpio_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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u32 val, bank, index;
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unsigned long flags;
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bank = asic3_irq_to_bank(asic, irq);
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index = asic3_irq_to_index(asic, irq);
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spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
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val &= ~(1 << index);
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asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_unmask_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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int regval;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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regval = asic3_read_register(asic,
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK);
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regval |= (ASIC3_INTMASK_MASK0 <<
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(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
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asic3_write_register(asic,
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ASIC3_INTR_BASE +
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ASIC3_INTR_INT_MASK,
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regval);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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u32 bank, index;
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u16 trigger, level, edge, bit;
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unsigned long flags;
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bank = asic3_irq_to_bank(asic, irq);
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index = asic3_irq_to_index(asic, irq);
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bit = 1<<index;
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spin_lock_irqsave(&asic->lock, flags);
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level = asic3_read_register(asic,
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bank + ASIC3_GPIO_LEVEL_TRIGGER);
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edge = asic3_read_register(asic,
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bank + ASIC3_GPIO_EDGE_TRIGGER);
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trigger = asic3_read_register(asic,
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bank + ASIC3_GPIO_TRIGGER_TYPE);
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asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
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if (type == IRQ_TYPE_EDGE_RISING) {
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trigger |= bit;
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edge |= bit;
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} else if (type == IRQ_TYPE_EDGE_FALLING) {
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trigger |= bit;
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edge &= ~bit;
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} else if (type == IRQ_TYPE_EDGE_BOTH) {
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trigger |= bit;
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if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
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edge &= ~bit;
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else
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edge |= bit;
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asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
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} else if (type == IRQ_TYPE_LEVEL_LOW) {
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trigger &= ~bit;
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level &= ~bit;
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} else if (type == IRQ_TYPE_LEVEL_HIGH) {
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trigger &= ~bit;
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level |= bit;
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} else {
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/*
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* if type == IRQ_TYPE_NONE, we should mask interrupts, but
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* be careful to not unmask them if mask was also called.
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* Probably need internal state for mask.
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*/
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dev_notice(asic->dev, "irq type not changed\n");
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}
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asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
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level);
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asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
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edge);
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asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
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trigger);
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spin_unlock_irqrestore(&asic->lock, flags);
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return 0;
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}
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static struct irq_chip asic3_gpio_irq_chip = {
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.name = "ASIC3-GPIO",
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.ack = asic3_mask_gpio_irq,
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.mask = asic3_mask_gpio_irq,
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.unmask = asic3_unmask_gpio_irq,
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.set_type = asic3_gpio_irq_type,
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};
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static struct irq_chip asic3_irq_chip = {
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.name = "ASIC3",
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.ack = asic3_mask_irq,
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.mask = asic3_mask_irq,
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.unmask = asic3_unmask_irq,
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};
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static int __init asic3_irq_probe(struct platform_device *pdev)
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{
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struct asic3 *asic = platform_get_drvdata(pdev);
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unsigned long clksel = 0;
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unsigned int irq, irq_base;
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int ret;
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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return ret;
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asic->irq_nr = ret;
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/* turn on clock to IRQ controller */
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clksel |= CLOCK_SEL_CX;
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asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
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clksel);
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irq_base = asic->irq_base;
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for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
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if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
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set_irq_chip(irq, &asic3_gpio_irq_chip);
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else
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set_irq_chip(irq, &asic3_irq_chip);
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set_irq_chip_data(irq, asic);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
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ASIC3_INTMASK_GINTMASK);
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set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
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set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
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set_irq_data(asic->irq_nr, asic);
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return 0;
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}
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static void asic3_irq_remove(struct platform_device *pdev)
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{
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struct asic3 *asic = platform_get_drvdata(pdev);
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unsigned int irq, irq_base;
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irq_base = asic->irq_base;
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for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
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set_irq_flags(irq, 0);
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set_irq_handler(irq, NULL);
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set_irq_chip(irq, NULL);
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set_irq_chip_data(irq, NULL);
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}
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set_irq_chained_handler(asic->irq_nr, NULL);
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}
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/* GPIOs */
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static int asic3_gpio_direction(struct gpio_chip *chip,
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unsigned offset, int out)
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{
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u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
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unsigned int gpio_base;
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unsigned long flags;
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struct asic3 *asic;
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asic = container_of(chip, struct asic3, gpio);
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gpio_base = ASIC3_GPIO_TO_BASE(offset);
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if (gpio_base > ASIC3_GPIO_D_BASE) {
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dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
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gpio_base, offset);
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return -EINVAL;
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}
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spin_lock_irqsave(&asic->lock, flags);
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out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
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/* Input is 0, Output is 1 */
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if (out)
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out_reg |= mask;
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else
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out_reg &= ~mask;
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asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
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spin_unlock_irqrestore(&asic->lock, flags);
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return 0;
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}
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static int asic3_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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return asic3_gpio_direction(chip, offset, 0);
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}
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static int asic3_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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return asic3_gpio_direction(chip, offset, 1);
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}
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static int asic3_gpio_get(struct gpio_chip *chip,
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unsigned offset)
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{
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unsigned int gpio_base;
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u32 mask = ASIC3_GPIO_TO_MASK(offset);
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struct asic3 *asic;
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asic = container_of(chip, struct asic3, gpio);
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gpio_base = ASIC3_GPIO_TO_BASE(offset);
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if (gpio_base > ASIC3_GPIO_D_BASE) {
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dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
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gpio_base, offset);
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return -EINVAL;
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}
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return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
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}
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static void asic3_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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u32 mask, out_reg;
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unsigned int gpio_base;
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unsigned long flags;
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|
struct asic3 *asic;
|
|
|
|
asic = container_of(chip, struct asic3, gpio);
|
|
gpio_base = ASIC3_GPIO_TO_BASE(offset);
|
|
|
|
if (gpio_base > ASIC3_GPIO_D_BASE) {
|
|
dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
|
|
gpio_base, offset);
|
|
return;
|
|
}
|
|
|
|
mask = ASIC3_GPIO_TO_MASK(offset);
|
|
|
|
spin_lock_irqsave(&asic->lock, flags);
|
|
|
|
out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
|
|
|
|
if (value)
|
|
out_reg |= mask;
|
|
else
|
|
out_reg &= ~mask;
|
|
|
|
asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
|
|
|
|
spin_unlock_irqrestore(&asic->lock, flags);
|
|
|
|
return;
|
|
}
|
|
|
|
static __init int asic3_gpio_probe(struct platform_device *pdev,
|
|
u16 *gpio_config, int num)
|
|
{
|
|
struct asic3 *asic = platform_get_drvdata(pdev);
|
|
u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
|
|
u16 out_reg[ASIC3_NUM_GPIO_BANKS];
|
|
u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
|
|
int i;
|
|
|
|
memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
|
|
memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
|
|
memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
|
|
|
|
/* Enable all GPIOs */
|
|
asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
|
|
asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
|
|
asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
|
|
asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
|
|
|
|
for (i = 0; i < num; i++) {
|
|
u8 alt, pin, dir, init, bank_num, bit_num;
|
|
u16 config = gpio_config[i];
|
|
|
|
pin = ASIC3_CONFIG_GPIO_PIN(config);
|
|
alt = ASIC3_CONFIG_GPIO_ALT(config);
|
|
dir = ASIC3_CONFIG_GPIO_DIR(config);
|
|
init = ASIC3_CONFIG_GPIO_INIT(config);
|
|
|
|
bank_num = ASIC3_GPIO_TO_BANK(pin);
|
|
bit_num = ASIC3_GPIO_TO_BIT(pin);
|
|
|
|
alt_reg[bank_num] |= (alt << bit_num);
|
|
out_reg[bank_num] |= (init << bit_num);
|
|
dir_reg[bank_num] |= (dir << bit_num);
|
|
}
|
|
|
|
for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
|
|
asic3_write_register(asic,
|
|
ASIC3_BANK_TO_BASE(i) +
|
|
ASIC3_GPIO_DIRECTION,
|
|
dir_reg[i]);
|
|
asic3_write_register(asic,
|
|
ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
|
|
out_reg[i]);
|
|
asic3_write_register(asic,
|
|
ASIC3_BANK_TO_BASE(i) +
|
|
ASIC3_GPIO_ALT_FUNCTION,
|
|
alt_reg[i]);
|
|
}
|
|
|
|
return gpiochip_add(&asic->gpio);
|
|
}
|
|
|
|
static int asic3_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = platform_get_drvdata(pdev);
|
|
|
|
return gpiochip_remove(&asic->gpio);
|
|
}
|
|
|
|
static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
u32 cdex;
|
|
|
|
spin_lock_irqsave(&asic->lock, flags);
|
|
if (clk->enabled++ == 0) {
|
|
cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
|
|
cdex |= clk->cdex;
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
|
|
}
|
|
spin_unlock_irqrestore(&asic->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
|
|
{
|
|
unsigned long flags;
|
|
u32 cdex;
|
|
|
|
WARN_ON(clk->enabled == 0);
|
|
|
|
spin_lock_irqsave(&asic->lock, flags);
|
|
if (--clk->enabled == 0) {
|
|
cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
|
|
cdex &= ~clk->cdex;
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
|
|
}
|
|
spin_unlock_irqrestore(&asic->lock, flags);
|
|
}
|
|
|
|
/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
|
|
static struct ds1wm_driver_data ds1wm_pdata = {
|
|
.active_high = 1,
|
|
};
|
|
|
|
static struct resource ds1wm_resources[] = {
|
|
{
|
|
.start = ASIC3_OWM_BASE,
|
|
.end = ASIC3_OWM_BASE + 0x13,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = ASIC3_IRQ_OWM,
|
|
.start = ASIC3_IRQ_OWM,
|
|
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
|
|
},
|
|
};
|
|
|
|
static int ds1wm_enable(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
|
|
|
|
/* Turn on external clocks and the OWM clock */
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
|
|
msleep(1);
|
|
|
|
/* Reset and enable DS1WM */
|
|
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
|
|
ASIC3_EXTCF_OWM_RESET, 1);
|
|
msleep(1);
|
|
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
|
|
ASIC3_EXTCF_OWM_RESET, 0);
|
|
msleep(1);
|
|
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
|
|
ASIC3_EXTCF_OWM_EN, 1);
|
|
msleep(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ds1wm_disable(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
|
|
|
|
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
|
|
ASIC3_EXTCF_OWM_EN, 0);
|
|
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct mfd_cell asic3_cell_ds1wm = {
|
|
.name = "ds1wm",
|
|
.enable = ds1wm_enable,
|
|
.disable = ds1wm_disable,
|
|
.driver_data = &ds1wm_pdata,
|
|
.num_resources = ARRAY_SIZE(ds1wm_resources),
|
|
.resources = ds1wm_resources,
|
|
};
|
|
|
|
static void asic3_mmc_pwr(struct platform_device *pdev, int state)
|
|
{
|
|
struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
|
|
|
|
tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
|
|
}
|
|
|
|
static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
|
|
{
|
|
struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
|
|
|
|
tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
|
|
}
|
|
|
|
static struct tmio_mmc_data asic3_mmc_data = {
|
|
.hclk = 24576000,
|
|
.set_pwr = asic3_mmc_pwr,
|
|
.set_clk_div = asic3_mmc_clk_div,
|
|
};
|
|
|
|
static struct resource asic3_mmc_resources[] = {
|
|
{
|
|
.start = ASIC3_SD_CTRL_BASE,
|
|
.end = ASIC3_SD_CTRL_BASE + 0x3ff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = 0,
|
|
.end = 0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static int asic3_mmc_enable(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
|
|
|
|
/* Not sure if it must be done bit by bit, but leaving as-is */
|
|
asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
|
|
ASIC3_SDHWCTRL_LEVCD, 1);
|
|
asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
|
|
ASIC3_SDHWCTRL_LEVWP, 1);
|
|
asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
|
|
ASIC3_SDHWCTRL_SUSPEND, 0);
|
|
asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
|
|
ASIC3_SDHWCTRL_PCLR, 0);
|
|
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
|
|
/* CLK32 used for card detection and for interruption detection
|
|
* when HCLK is stopped.
|
|
*/
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
|
|
msleep(1);
|
|
|
|
/* HCLK 24.576 MHz, BCLK 12.288 MHz: */
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
|
|
CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
|
|
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
|
|
asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
|
|
msleep(1);
|
|
|
|
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
|
|
ASIC3_EXTCF_SD_MEM_ENABLE, 1);
|
|
|
|
/* Enable SD card slot 3.3V power supply */
|
|
asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
|
|
ASIC3_SDHWCTRL_SDPWR, 1);
|
|
|
|
/* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
|
|
tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
|
|
ASIC3_SD_CTRL_BASE >> 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int asic3_mmc_disable(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
|
|
|
|
/* Put in suspend mode */
|
|
asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
|
|
ASIC3_SDHWCTRL_SUSPEND, 1);
|
|
|
|
/* Disable clocks */
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
|
|
asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
|
|
return 0;
|
|
}
|
|
|
|
static struct mfd_cell asic3_cell_mmc = {
|
|
.name = "tmio-mmc",
|
|
.enable = asic3_mmc_enable,
|
|
.disable = asic3_mmc_disable,
|
|
.driver_data = &asic3_mmc_data,
|
|
.num_resources = ARRAY_SIZE(asic3_mmc_resources),
|
|
.resources = asic3_mmc_resources,
|
|
};
|
|
|
|
static int __init asic3_mfd_probe(struct platform_device *pdev,
|
|
struct resource *mem)
|
|
{
|
|
struct asic3 *asic = platform_get_drvdata(pdev);
|
|
struct resource *mem_sdio;
|
|
int irq, ret;
|
|
|
|
mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
if (!mem_sdio)
|
|
dev_dbg(asic->dev, "no SDIO MEM resource\n");
|
|
|
|
irq = platform_get_irq(pdev, 1);
|
|
if (irq < 0)
|
|
dev_dbg(asic->dev, "no SDIO IRQ resource\n");
|
|
|
|
/* DS1WM */
|
|
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
|
|
ASIC3_EXTCF_OWM_SMB, 0);
|
|
|
|
ds1wm_resources[0].start >>= asic->bus_shift;
|
|
ds1wm_resources[0].end >>= asic->bus_shift;
|
|
|
|
asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
|
|
asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
|
|
|
|
/* MMC */
|
|
asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
|
|
mem_sdio->start, 0x400 >> asic->bus_shift);
|
|
if (!asic->tmio_cnf) {
|
|
ret = -ENOMEM;
|
|
dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
|
|
goto out;
|
|
}
|
|
asic3_mmc_resources[0].start >>= asic->bus_shift;
|
|
asic3_mmc_resources[0].end >>= asic->bus_shift;
|
|
|
|
asic3_cell_mmc.platform_data = &asic3_cell_mmc;
|
|
asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc);
|
|
|
|
ret = mfd_add_devices(&pdev->dev, pdev->id,
|
|
&asic3_cell_ds1wm, 1, mem, asic->irq_base);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
if (mem_sdio && (irq >= 0))
|
|
ret = mfd_add_devices(&pdev->dev, pdev->id,
|
|
&asic3_cell_mmc, 1, mem_sdio, irq);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void asic3_mfd_remove(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = platform_get_drvdata(pdev);
|
|
|
|
mfd_remove_devices(&pdev->dev);
|
|
iounmap(asic->tmio_cnf);
|
|
}
|
|
|
|
/* Core */
|
|
static int __init asic3_probe(struct platform_device *pdev)
|
|
{
|
|
struct asic3_platform_data *pdata = pdev->dev.platform_data;
|
|
struct asic3 *asic;
|
|
struct resource *mem;
|
|
unsigned long clksel;
|
|
int ret = 0;
|
|
|
|
asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
|
|
if (asic == NULL) {
|
|
printk(KERN_ERR "kzalloc failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
spin_lock_init(&asic->lock);
|
|
platform_set_drvdata(pdev, asic);
|
|
asic->dev = &pdev->dev;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem) {
|
|
ret = -ENOMEM;
|
|
dev_err(asic->dev, "no MEM resource\n");
|
|
goto out_free;
|
|
}
|
|
|
|
asic->mapping = ioremap(mem->start, resource_size(mem));
|
|
if (!asic->mapping) {
|
|
ret = -ENOMEM;
|
|
dev_err(asic->dev, "Couldn't ioremap\n");
|
|
goto out_free;
|
|
}
|
|
|
|
asic->irq_base = pdata->irq_base;
|
|
|
|
/* calculate bus shift from mem resource */
|
|
asic->bus_shift = 2 - (resource_size(mem) >> 12);
|
|
|
|
clksel = 0;
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
|
|
|
|
ret = asic3_irq_probe(pdev);
|
|
if (ret < 0) {
|
|
dev_err(asic->dev, "Couldn't probe IRQs\n");
|
|
goto out_unmap;
|
|
}
|
|
|
|
asic->gpio.base = pdata->gpio_base;
|
|
asic->gpio.ngpio = ASIC3_NUM_GPIOS;
|
|
asic->gpio.get = asic3_gpio_get;
|
|
asic->gpio.set = asic3_gpio_set;
|
|
asic->gpio.direction_input = asic3_gpio_direction_input;
|
|
asic->gpio.direction_output = asic3_gpio_direction_output;
|
|
|
|
ret = asic3_gpio_probe(pdev,
|
|
pdata->gpio_config,
|
|
pdata->gpio_config_num);
|
|
if (ret < 0) {
|
|
dev_err(asic->dev, "GPIO probe failed\n");
|
|
goto out_irq;
|
|
}
|
|
|
|
/* Making a per-device copy is only needed for the
|
|
* theoretical case of multiple ASIC3s on one board:
|
|
*/
|
|
memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
|
|
|
|
asic3_mfd_probe(pdev, mem);
|
|
|
|
dev_info(asic->dev, "ASIC3 Core driver\n");
|
|
|
|
return 0;
|
|
|
|
out_irq:
|
|
asic3_irq_remove(pdev);
|
|
|
|
out_unmap:
|
|
iounmap(asic->mapping);
|
|
|
|
out_free:
|
|
kfree(asic);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit asic3_remove(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct asic3 *asic = platform_get_drvdata(pdev);
|
|
|
|
asic3_mfd_remove(pdev);
|
|
|
|
ret = asic3_gpio_remove(pdev);
|
|
if (ret < 0)
|
|
return ret;
|
|
asic3_irq_remove(pdev);
|
|
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
|
|
|
|
iounmap(asic->mapping);
|
|
|
|
kfree(asic);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void asic3_shutdown(struct platform_device *pdev)
|
|
{
|
|
}
|
|
|
|
static struct platform_driver asic3_device_driver = {
|
|
.driver = {
|
|
.name = "asic3",
|
|
},
|
|
.remove = __devexit_p(asic3_remove),
|
|
.shutdown = asic3_shutdown,
|
|
};
|
|
|
|
static int __init asic3_init(void)
|
|
{
|
|
int retval = 0;
|
|
retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
|
|
return retval;
|
|
}
|
|
|
|
subsys_initcall(asic3_init);
|