452 lines
13 KiB
C
452 lines
13 KiB
C
#include "radeonfb.h"
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/* the accelerated functions here are patterned after the
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* "ACCEL_MMIO" ifdef branches in XFree86
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* --dte
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*/
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#define FLUSH_CACHE_WORKAROUND 1
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void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
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{
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int i;
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for (i=0; i<2000000; i++) {
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rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f;
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if (rinfo->fifo_free >= entries)
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return;
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udelay(10);
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}
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printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
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/* XXX Todo: attempt to reset the engine */
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}
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static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
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{
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if (entries <= rinfo->fifo_free)
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rinfo->fifo_free -= entries;
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else
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radeon_fifo_update_and_wait(rinfo, entries);
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}
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static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg,
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u32 *cache, u32 new_val)
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{
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if (new_val == *cache)
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return;
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*cache = new_val;
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radeon_fifo_wait(rinfo, 1);
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OUTREG(reg, new_val);
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}
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static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
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const struct fb_fillrect *region)
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{
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radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
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rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P);
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radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
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DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
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radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache,
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region->color);
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/* Ensure the dst cache is flushed and the engine idle before
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* issuing the operation.
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*
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* This works around engine lockups on some cards
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*/
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#if FLUSH_CACHE_WORKAROUND
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radeon_fifo_wait(rinfo, 2);
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OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
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OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
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#endif
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radeon_fifo_wait(rinfo, 2);
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OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
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OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
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}
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void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
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{
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struct radeonfb_info *rinfo = info->par;
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struct fb_fillrect modded;
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int vxres, vyres;
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WARN_ON(rinfo->gfx_mode);
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if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
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return;
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if (info->flags & FBINFO_HWACCEL_DISABLED) {
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cfb_fillrect(info, region);
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return;
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}
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vxres = info->var.xres_virtual;
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vyres = info->var.yres_virtual;
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memcpy(&modded, region, sizeof(struct fb_fillrect));
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if(!modded.width || !modded.height ||
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modded.dx >= vxres || modded.dy >= vyres)
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return;
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if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
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if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
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if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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info->fix.visual == FB_VISUAL_DIRECTCOLOR )
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modded.color = ((u32 *) (info->pseudo_palette))[region->color];
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radeonfb_prim_fillrect(rinfo, &modded);
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}
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static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
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const struct fb_copyarea *area)
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{
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int xdir, ydir;
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u32 sx, sy, dx, dy, w, h;
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w = area->width; h = area->height;
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dx = area->dx; dy = area->dy;
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sx = area->sx; sy = area->sy;
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xdir = sx - dx;
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ydir = sy - dy;
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if ( xdir < 0 ) { sx += w-1; dx += w-1; }
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if ( ydir < 0 ) { sy += h-1; dy += h-1; }
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radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
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rinfo->dp_gui_mc_base |
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GMC_BRUSH_NONE |
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GMC_SRC_DATATYPE_COLOR |
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ROP3_S |
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DP_SRC_SOURCE_MEMORY);
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radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
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(xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) |
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(ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
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#if FLUSH_CACHE_WORKAROUND
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radeon_fifo_wait(rinfo, 2);
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OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
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OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
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#endif
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radeon_fifo_wait(rinfo, 3);
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OUTREG(SRC_Y_X, (sy << 16) | sx);
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OUTREG(DST_Y_X, (dy << 16) | dx);
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OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
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}
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void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
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{
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struct radeonfb_info *rinfo = info->par;
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struct fb_copyarea modded;
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u32 vxres, vyres;
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modded.sx = area->sx;
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modded.sy = area->sy;
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modded.dx = area->dx;
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modded.dy = area->dy;
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modded.width = area->width;
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modded.height = area->height;
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WARN_ON(rinfo->gfx_mode);
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if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
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return;
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if (info->flags & FBINFO_HWACCEL_DISABLED) {
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cfb_copyarea(info, area);
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return;
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}
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vxres = info->var.xres_virtual;
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vyres = info->var.yres_virtual;
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if(!modded.width || !modded.height ||
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modded.sx >= vxres || modded.sy >= vyres ||
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modded.dx >= vxres || modded.dy >= vyres)
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return;
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if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
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if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
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if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
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if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
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radeonfb_prim_copyarea(rinfo, &modded);
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}
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static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
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const struct fb_image *image,
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u32 fg, u32 bg)
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{
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unsigned int dwords;
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u32 *bits;
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radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
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rinfo->dp_gui_mc_base |
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GMC_BRUSH_NONE | GMC_DST_CLIP_LEAVE |
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GMC_SRC_DATATYPE_MONO_FG_BG |
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ROP3_S |
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GMC_BYTE_ORDER_MSB_TO_LSB |
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DP_SRC_SOURCE_HOST_DATA);
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radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
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DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
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radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
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radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
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/* Ensure the dst cache is flushed and the engine idle before
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* issuing the operation.
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*
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* This works around engine lockups on some cards
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*/
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#if FLUSH_CACHE_WORKAROUND
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radeon_fifo_wait(rinfo, 2);
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OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
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OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
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#endif
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/* X here pads width to a multiple of 32 and uses the clipper to
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* adjust the result. Is that really necessary ? Things seem to
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* work ok for me without that and the doco doesn't seem to imply]
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* there is such a restriction.
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*/
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radeon_fifo_wait(rinfo, 4);
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OUTREG(SC_TOP_LEFT, (image->dy << 16) | image->dx);
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OUTREG(SC_BOTTOM_RIGHT, ((image->dy + image->height) << 16) |
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(image->dx + image->width));
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OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
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OUTREG(DST_HEIGHT_WIDTH, (image->height << 16) | ((image->width + 31) & ~31));
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dwords = (image->width + 31) >> 5;
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dwords *= image->height;
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bits = (u32*)(image->data);
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while(dwords >= 8) {
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radeon_fifo_wait(rinfo, 8);
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#if BITS_PER_LONG == 64
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__raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0);
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__raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2);
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__raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4);
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__raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6);
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bits += 8;
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#else
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7);
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#endif
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dwords -= 8;
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}
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while(dwords--) {
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radeon_fifo_wait(rinfo, 1);
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__raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
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}
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}
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void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
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{
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struct radeonfb_info *rinfo = info->par;
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u32 fg, bg;
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WARN_ON(rinfo->gfx_mode);
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if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
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return;
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if (!image->width || !image->height)
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return;
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/* We only do 1 bpp color expansion for now */
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if (!accel_cexp ||
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(info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1)
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goto fallback;
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/* Fallback if running out of the screen. We may do clipping
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* in the future */
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if ((image->dx + image->width) > info->var.xres_virtual ||
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(image->dy + image->height) > info->var.yres_virtual)
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goto fallback;
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if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
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fg = ((u32*)(info->pseudo_palette))[image->fg_color];
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bg = ((u32*)(info->pseudo_palette))[image->bg_color];
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} else {
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fg = image->fg_color;
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bg = image->bg_color;
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}
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radeonfb_prim_imageblit(rinfo, image, fg, bg);
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return;
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fallback:
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radeon_engine_idle(rinfo);
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cfb_imageblit(info, image);
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}
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int radeonfb_sync(struct fb_info *info)
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{
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struct radeonfb_info *rinfo = info->par;
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if (info->state != FBINFO_STATE_RUNNING)
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return 0;
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radeon_engine_idle(rinfo);
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return 0;
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}
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void radeonfb_engine_reset(struct radeonfb_info *rinfo)
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{
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u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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u32 host_path_cntl;
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radeon_engine_flush (rinfo);
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clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
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mclk_cntl = INPLL(MCLK_CNTL);
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OUTPLL(MCLK_CNTL, (mclk_cntl |
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FORCEON_MCLKA |
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FORCEON_MCLKB |
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FORCEON_YCLKA |
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FORCEON_YCLKB |
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FORCEON_MC |
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FORCEON_AIC));
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host_path_cntl = INREG(HOST_PATH_CNTL);
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rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
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if (IS_R300_VARIANT(rinfo)) {
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u32 tmp;
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OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
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SOFT_RESET_CP |
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SOFT_RESET_HI |
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SOFT_RESET_E2));
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INREG(RBBM_SOFT_RESET);
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OUTREG(RBBM_SOFT_RESET, 0);
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tmp = INREG(RB2D_DSTCACHE_MODE);
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OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
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} else {
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OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
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SOFT_RESET_CP |
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SOFT_RESET_HI |
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SOFT_RESET_SE |
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SOFT_RESET_RE |
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SOFT_RESET_PP |
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SOFT_RESET_E2 |
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SOFT_RESET_RB);
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INREG(RBBM_SOFT_RESET);
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OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
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~(SOFT_RESET_CP |
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SOFT_RESET_HI |
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SOFT_RESET_SE |
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SOFT_RESET_RE |
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SOFT_RESET_PP |
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SOFT_RESET_E2 |
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SOFT_RESET_RB));
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INREG(RBBM_SOFT_RESET);
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}
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OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
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INREG(HOST_PATH_CNTL);
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OUTREG(HOST_PATH_CNTL, host_path_cntl);
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if (!IS_R300_VARIANT(rinfo))
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OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
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OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
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OUTPLL(MCLK_CNTL, mclk_cntl);
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}
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void radeonfb_engine_init (struct radeonfb_info *rinfo)
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{
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unsigned long temp;
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/* disable 3D engine */
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OUTREG(RB3D_CNTL, 0);
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rinfo->fifo_free = 0;
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radeonfb_engine_reset(rinfo);
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radeon_fifo_wait(rinfo, 1);
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if (IS_R300_VARIANT(rinfo)) {
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OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
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RB2D_DC_AUTOFLUSH_ENABLE |
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RB2D_DC_DC_DISABLE_IGNORE_PE);
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} else {
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/* This needs to be double checked with ATI. Latest X driver
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* completely "forgets" to set this register on < r3xx, and
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* we used to just write 0 there... I'll keep the 0 and update
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* that when we have sorted things out on X side.
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*/
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OUTREG(RB2D_DSTCACHE_MODE, 0);
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}
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radeon_fifo_wait(rinfo, 3);
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/* We re-read MC_FB_LOCATION from card as it can have been
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* modified by XFree drivers (ouch !)
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*/
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rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
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OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
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(rinfo->fb_local_base >> 10));
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OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
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OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
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radeon_fifo_wait(rinfo, 1);
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#ifdef __BIG_ENDIAN
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OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
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#else
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OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
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#endif
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radeon_fifo_wait(rinfo, 2);
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OUTREG(DEFAULT_SC_TOP_LEFT, 0);
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OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
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DEFAULT_SC_BOTTOM_MAX));
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/* set default DP_GUI_MASTER_CNTL */
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temp = radeon_get_dstbpp(rinfo->depth);
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rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
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rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base |
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GMC_BRUSH_SOLID_COLOR |
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GMC_SRC_DATATYPE_COLOR;
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radeon_fifo_wait(rinfo, 1);
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OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache);
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/* clear line drawing regs */
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radeon_fifo_wait(rinfo, 2);
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OUTREG(DST_LINE_START, 0);
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OUTREG(DST_LINE_END, 0);
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/* set brush and source color regs */
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rinfo->dp_brush_fg_cache = 0xffffffff;
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rinfo->dp_brush_bg_cache = 0x00000000;
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rinfo->dp_src_fg_cache = 0xffffffff;
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rinfo->dp_src_bg_cache = 0x00000000;
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radeon_fifo_wait(rinfo, 4);
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OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache);
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OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache);
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OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache);
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OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache);
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/* Default direction */
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rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM;
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radeon_fifo_wait(rinfo, 1);
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OUTREG(DP_CNTL, rinfo->dp_cntl_cache);
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/* default write mask */
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|
radeon_fifo_wait(rinfo, 1);
|
|
OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
|
|
/* Default to no swapping of host data */
|
|
radeon_fifo_wait(rinfo, 1);
|
|
OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE);
|
|
|
|
/* Make sure it's settled */
|
|
radeon_engine_idle(rinfo);
|
|
}
|