![Nick Piggin](/assets/img/avatar_default.png)
The comment being removed by this patch is incorrect and misleading. In the following situation: 1. load ... 2. store 1 -> X 3. wmb 4. rmb 5. load a <- Y 6. store ... 4 will only ensure ordering of 1 with 5. 3 will only ensure ordering of 2 with 6. Further, a CPU with strictly in-order stores will still only provide that 2 and 6 are ordered (effectively, it is the same as a weakly ordered CPU with wmb after every store). In all cases, 5 may still be executed before 2 is visible to other CPUs! The additional piece of the puzzle that mb() provides is the store/load ordering, which fundamentally cannot be achieved with any combination of rmb()s and wmb()s. This can be an unexpected result if one expected any sort of global ordering guarantee to barriers (eg. that the barriers themselves are sequentially consistent with other types of barriers). However sfence or lfence barriers need only provide an ordering partial ordering of memory operations -- Consider that wmb may be implemented as nothing more than inserting a special barrier entry in the store queue, or, in the case of x86, it can be a noop as the store queue is in order. And an rmb may be implemented as a directive to prevent subsequent loads only so long as their are no previous outstanding loads (while there could be stores still in store queues). I can actually see the occasional load/store being reordered around lfence on my core2. That doesn't prove my above assertions, but it does show the comment is wrong (unless my program is -- can send it out by request). So: mb() and smp_mb() always have and always will require a full mfence or lock prefixed instruction on x86. And we should remove this comment. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: Paul McKenney <paulmck@us.ibm.com> Cc: David Howells <dhowells@redhat.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
314 lines
8.1 KiB
C
314 lines
8.1 KiB
C
#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/cpufeature.h>
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#include <asm/cmpxchg.h>
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#ifdef __KERNEL__
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struct task_struct; /* one of the stranger aspects of C forward declarations.. */
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extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
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/*
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* Saving eflags is important. It switches not only IOPL between tasks,
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* it also protects other tasks from NT leaking through sysenter etc.
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*/
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#define switch_to(prev,next,last) do { \
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unsigned long esi,edi; \
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asm volatile("pushfl\n\t" /* Save flags */ \
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"pushl %%ebp\n\t" \
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"movl %%esp,%0\n\t" /* save ESP */ \
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"movl %5,%%esp\n\t" /* restore ESP */ \
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"movl $1f,%1\n\t" /* save EIP */ \
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"pushl %6\n\t" /* restore EIP */ \
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"jmp __switch_to\n" \
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"1:\t" \
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"popl %%ebp\n\t" \
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"popfl" \
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:"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
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"=a" (last),"=S" (esi),"=D" (edi) \
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:"m" (next->thread.esp),"m" (next->thread.eip), \
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"2" (prev), "d" (next)); \
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} while (0)
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#define _set_base(addr,base) do { unsigned long __pr; \
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__asm__ __volatile__ ("movw %%dx,%1\n\t" \
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"rorl $16,%%edx\n\t" \
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"movb %%dl,%2\n\t" \
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"movb %%dh,%3" \
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:"=&d" (__pr) \
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:"m" (*((addr)+2)), \
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"m" (*((addr)+4)), \
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"m" (*((addr)+7)), \
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"0" (base) \
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); } while(0)
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#define _set_limit(addr,limit) do { unsigned long __lr; \
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__asm__ __volatile__ ("movw %%dx,%1\n\t" \
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"rorl $16,%%edx\n\t" \
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"movb %2,%%dh\n\t" \
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"andb $0xf0,%%dh\n\t" \
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"orb %%dh,%%dl\n\t" \
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"movb %%dl,%2" \
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:"=&d" (__lr) \
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:"m" (*(addr)), \
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"m" (*((addr)+6)), \
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"0" (limit) \
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); } while(0)
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#define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
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#define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"mov %0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"pushl $0\n\t" \
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"popl %%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 4\n\t" \
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".long 1b,3b\n" \
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".previous" \
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: :"rm" (value))
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/*
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* Save a segment register away
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*/
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#define savesegment(seg, value) \
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asm volatile("mov %%" #seg ",%0":"=rm" (value))
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static inline void native_clts(void)
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{
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asm volatile ("clts");
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}
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr0(unsigned long val)
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{
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asm volatile("movl %0,%%cr0": :"r" (val));
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}
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static inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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{
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asm volatile("movl %0,%%cr2": :"r" (val));
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}
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static inline unsigned long native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("movl %0,%%cr3": :"r" (val));
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
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return val;
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}
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static inline unsigned long native_read_cr4_safe(void)
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{
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unsigned long val;
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/* This could fault if %cr4 does not exist */
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asm("1: movl %%cr4, %0 \n"
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"2: \n"
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".section __ex_table,\"a\" \n"
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".long 1b,2b \n"
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".previous \n"
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: "=r" (val): "0" (0));
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return val;
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}
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static inline void native_write_cr4(unsigned long val)
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{
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asm volatile("movl %0,%%cr4": :"r" (val));
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}
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define read_cr0() (native_read_cr0())
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#define write_cr0(x) (native_write_cr0(x))
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#define read_cr2() (native_read_cr2())
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#define write_cr2(x) (native_write_cr2(x))
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#define read_cr3() (native_read_cr3())
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#define write_cr3(x) (native_write_cr3(x))
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#define read_cr4() (native_read_cr4())
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#define read_cr4_safe() (native_read_cr4_safe())
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#define write_cr4(x) (native_write_cr4(x))
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#define wbinvd() (native_wbinvd())
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/* Clear the 'TS' bit */
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#define clts() (native_clts())
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#endif/* CONFIG_PARAVIRT */
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/* Set the 'TS' bit */
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#define stts() write_cr0(8 | read_cr0())
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#endif /* __KERNEL__ */
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static inline unsigned long get_limit(unsigned long segment)
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{
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unsigned long __limit;
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__asm__("lsll %1,%0"
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:"=r" (__limit):"r" (segment));
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return __limit+1;
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}
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#define nop() __asm__ __volatile__ ("nop")
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* For now, "wmb()" doesn't actually do anything, as all
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* Intel CPU's follow what Intel calls a *Processor Order*,
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* in which all writes are seen in the program order even
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* outside the CPU.
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*
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* I expect future Intel CPU's to have a weaker ordering,
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* but I'd also expect them to finally get their act together
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* and add some real memory barriers if so.
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*
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* Some non intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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**/
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_X86_OOSTORE
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/* Actually there are no OOO store capable CPUs for now that do SSE,
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but make it already an possibility. */
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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#else
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#endif
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif
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#include <linux/irqflags.h>
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/*
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* disable hlt during certain critical i/o operations
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*/
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#define HAVE_DISABLE_HLT
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void disable_hlt(void);
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void enable_hlt(void);
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extern int es7000_plat;
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void cpu_idle_wait(void);
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extern unsigned long arch_align_stack(unsigned long sp);
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extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
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void default_idle(void);
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#endif
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