7356f0b26b
In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are: 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: fixed whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com> |
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