917 lines
28 KiB
C
917 lines
28 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __RADEON_H__
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#define __RADEON_H__
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#include "radeon_object.h"
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/* TODO: Here are things that needs to be done :
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* - surface allocator & initializer : (bit like scratch reg) should
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* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
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* related to surface
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* - WB : write back stuff (do it bit like scratch reg things)
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* - Vblank : look at Jesse's rework and what we should do
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* - r600/r700: gart & cp
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* - cs : clean cs ioctl use bitmap & things like that.
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* - power management stuff
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* - Barrier in gart code
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* - Unmappabled vram ?
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* - TESTING, TESTING, TESTING
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*/
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#include <asm/atomic.h>
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#include <linux/wait.h>
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#include <linux/list.h>
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#include <linux/kref.h>
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#include "radeon_mode.h"
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#include "radeon_reg.h"
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#include "r300.h"
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/*
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* Modules parameters.
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*/
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extern int radeon_no_wb;
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extern int radeon_modeset;
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extern int radeon_dynclks;
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extern int radeon_r4xx_atom;
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extern int radeon_agpmode;
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extern int radeon_vram_limit;
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extern int radeon_gart_size;
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extern int radeon_benchmarking;
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extern int radeon_testing;
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extern int radeon_connector_table;
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/*
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* Copy from radeon_drv.h so we don't have to include both and have conflicting
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* symbol;
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*/
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#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define RADEON_IB_POOL_SIZE 16
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#define RADEON_DEBUGFS_MAX_NUM_FILES 32
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#define RADEONFB_CONN_LIMIT 4
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enum radeon_family {
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CHIP_R100,
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CHIP_RV100,
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CHIP_RS100,
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CHIP_RV200,
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CHIP_RS200,
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CHIP_R200,
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CHIP_RV250,
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CHIP_RS300,
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CHIP_RV280,
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CHIP_R300,
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CHIP_R350,
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CHIP_RV350,
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CHIP_RV380,
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CHIP_R420,
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CHIP_R423,
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CHIP_RV410,
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CHIP_RS400,
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CHIP_RS480,
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CHIP_RS600,
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CHIP_RS690,
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CHIP_RS740,
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CHIP_RV515,
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CHIP_R520,
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CHIP_RV530,
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CHIP_RV560,
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CHIP_RV570,
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CHIP_R580,
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CHIP_R600,
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CHIP_RV610,
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CHIP_RV630,
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CHIP_RV620,
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CHIP_RV635,
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CHIP_RV670,
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CHIP_RS780,
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CHIP_RV770,
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CHIP_RV730,
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CHIP_RV710,
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CHIP_RS880,
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CHIP_LAST,
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};
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enum radeon_chip_flags {
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RADEON_FAMILY_MASK = 0x0000ffffUL,
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RADEON_FLAGS_MASK = 0xffff0000UL,
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RADEON_IS_MOBILITY = 0x00010000UL,
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RADEON_IS_IGP = 0x00020000UL,
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RADEON_SINGLE_CRTC = 0x00040000UL,
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RADEON_IS_AGP = 0x00080000UL,
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RADEON_HAS_HIERZ = 0x00100000UL,
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RADEON_IS_PCIE = 0x00200000UL,
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RADEON_NEW_MEMMAP = 0x00400000UL,
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RADEON_IS_PCI = 0x00800000UL,
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RADEON_IS_IGPGART = 0x01000000UL,
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};
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/*
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* Errata workarounds.
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*/
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enum radeon_pll_errata {
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CHIP_ERRATA_R300_CG = 0x00000001,
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CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
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CHIP_ERRATA_PLL_DELAY = 0x00000004
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};
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struct radeon_device;
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/*
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* BIOS.
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*/
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bool radeon_get_bios(struct radeon_device *rdev);
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/*
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* Clocks
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*/
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struct radeon_clock {
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struct radeon_pll p1pll;
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struct radeon_pll p2pll;
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struct radeon_pll spll;
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struct radeon_pll mpll;
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/* 10 Khz units */
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uint32_t default_mclk;
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uint32_t default_sclk;
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};
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/*
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* Fences.
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*/
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struct radeon_fence_driver {
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uint32_t scratch_reg;
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atomic_t seq;
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uint32_t last_seq;
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unsigned long count_timeout;
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wait_queue_head_t queue;
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rwlock_t lock;
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struct list_head created;
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struct list_head emited;
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struct list_head signaled;
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};
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struct radeon_fence {
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struct radeon_device *rdev;
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struct kref kref;
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struct list_head list;
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/* protected by radeon_fence.lock */
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uint32_t seq;
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unsigned long timeout;
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bool emited;
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bool signaled;
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};
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int radeon_fence_driver_init(struct radeon_device *rdev);
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void radeon_fence_driver_fini(struct radeon_device *rdev);
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int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
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int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
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void radeon_fence_process(struct radeon_device *rdev);
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bool radeon_fence_signaled(struct radeon_fence *fence);
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int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
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int radeon_fence_wait_next(struct radeon_device *rdev);
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int radeon_fence_wait_last(struct radeon_device *rdev);
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struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
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void radeon_fence_unref(struct radeon_fence **fence);
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/*
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* Tiling registers
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*/
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struct radeon_surface_reg {
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struct radeon_object *robj;
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};
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#define RADEON_GEM_MAX_SURFACES 8
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/*
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* Radeon buffer.
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*/
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struct radeon_object;
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struct radeon_object_list {
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struct list_head list;
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struct radeon_object *robj;
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uint64_t gpu_offset;
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unsigned rdomain;
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unsigned wdomain;
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uint32_t tiling_flags;
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};
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int radeon_object_init(struct radeon_device *rdev);
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void radeon_object_fini(struct radeon_device *rdev);
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int radeon_object_create(struct radeon_device *rdev,
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struct drm_gem_object *gobj,
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unsigned long size,
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bool kernel,
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uint32_t domain,
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bool interruptible,
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struct radeon_object **robj_ptr);
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int radeon_object_kmap(struct radeon_object *robj, void **ptr);
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void radeon_object_kunmap(struct radeon_object *robj);
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void radeon_object_unref(struct radeon_object **robj);
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int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
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uint64_t *gpu_addr);
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void radeon_object_unpin(struct radeon_object *robj);
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int radeon_object_wait(struct radeon_object *robj);
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int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
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int radeon_object_evict_vram(struct radeon_device *rdev);
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int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
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void radeon_object_force_delete(struct radeon_device *rdev);
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void radeon_object_list_add_object(struct radeon_object_list *lobj,
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struct list_head *head);
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int radeon_object_list_validate(struct list_head *head, void *fence);
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void radeon_object_list_unvalidate(struct list_head *head);
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void radeon_object_list_clean(struct list_head *head);
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int radeon_object_fbdev_mmap(struct radeon_object *robj,
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struct vm_area_struct *vma);
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unsigned long radeon_object_size(struct radeon_object *robj);
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void radeon_object_clear_surface_reg(struct radeon_object *robj);
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int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
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bool force_drop);
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void radeon_object_set_tiling_flags(struct radeon_object *robj,
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uint32_t tiling_flags, uint32_t pitch);
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void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
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void radeon_bo_move_notify(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *mem);
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void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
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/*
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* GEM objects.
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*/
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struct radeon_gem {
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struct list_head objects;
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};
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int radeon_gem_init(struct radeon_device *rdev);
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void radeon_gem_fini(struct radeon_device *rdev);
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int radeon_gem_object_create(struct radeon_device *rdev, int size,
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int alignment, int initial_domain,
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bool discardable, bool kernel,
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bool interruptible,
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struct drm_gem_object **obj);
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int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
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uint64_t *gpu_addr);
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void radeon_gem_object_unpin(struct drm_gem_object *obj);
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/*
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* GART structures, functions & helpers
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*/
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struct radeon_mc;
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struct radeon_gart_table_ram {
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volatile uint32_t *ptr;
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};
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struct radeon_gart_table_vram {
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struct radeon_object *robj;
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volatile uint32_t *ptr;
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};
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union radeon_gart_table {
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struct radeon_gart_table_ram ram;
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struct radeon_gart_table_vram vram;
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};
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struct radeon_gart {
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dma_addr_t table_addr;
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unsigned num_gpu_pages;
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unsigned num_cpu_pages;
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unsigned table_size;
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union radeon_gart_table table;
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struct page **pages;
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dma_addr_t *pages_addr;
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bool ready;
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};
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int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
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void radeon_gart_table_ram_free(struct radeon_device *rdev);
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int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
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void radeon_gart_table_vram_free(struct radeon_device *rdev);
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int radeon_gart_init(struct radeon_device *rdev);
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void radeon_gart_fini(struct radeon_device *rdev);
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void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
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int pages);
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int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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int pages, struct page **pagelist);
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/*
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* GPU MC structures, functions & helpers
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*/
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struct radeon_mc {
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resource_size_t aper_size;
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resource_size_t aper_base;
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resource_size_t agp_base;
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unsigned gtt_location;
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unsigned gtt_size;
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unsigned vram_location;
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/* for some chips with <= 32MB we need to lie
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* about vram size near mc fb location */
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unsigned mc_vram_size;
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unsigned vram_width;
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unsigned real_vram_size;
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int vram_mtrr;
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bool vram_is_ddr;
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};
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int radeon_mc_setup(struct radeon_device *rdev);
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/*
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* GPU scratch registers structures, functions & helpers
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*/
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struct radeon_scratch {
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unsigned num_reg;
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bool free[32];
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uint32_t reg[32];
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};
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
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/*
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* IRQS.
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*/
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struct radeon_irq {
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bool installed;
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bool sw_int;
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/* FIXME: use a define max crtc rather than hardcode it */
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bool crtc_vblank_int[2];
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};
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int radeon_irq_kms_init(struct radeon_device *rdev);
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void radeon_irq_kms_fini(struct radeon_device *rdev);
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/*
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* CP & ring.
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*/
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struct radeon_ib {
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struct list_head list;
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unsigned long idx;
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uint64_t gpu_addr;
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struct radeon_fence *fence;
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volatile uint32_t *ptr;
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uint32_t length_dw;
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};
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struct radeon_ib_pool {
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struct mutex mutex;
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struct radeon_object *robj;
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struct list_head scheduled_ibs;
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struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
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bool ready;
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DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
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};
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struct radeon_cp {
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struct radeon_object *ring_obj;
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volatile uint32_t *ring;
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unsigned rptr;
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unsigned wptr;
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unsigned wptr_old;
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unsigned ring_size;
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unsigned ring_free_dw;
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int count_dw;
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uint64_t gpu_addr;
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uint32_t align_mask;
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uint32_t ptr_mask;
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struct mutex mutex;
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bool ready;
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};
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int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
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int radeon_ib_pool_init(struct radeon_device *rdev);
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void radeon_ib_pool_fini(struct radeon_device *rdev);
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int radeon_ib_test(struct radeon_device *rdev);
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/* Ring access between begin & end cannot sleep */
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void radeon_ring_free_size(struct radeon_device *rdev);
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int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
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void radeon_ring_unlock_commit(struct radeon_device *rdev);
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void radeon_ring_unlock_undo(struct radeon_device *rdev);
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int radeon_ring_test(struct radeon_device *rdev);
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int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
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void radeon_ring_fini(struct radeon_device *rdev);
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/*
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* CS.
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*/
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struct radeon_cs_reloc {
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struct drm_gem_object *gobj;
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struct radeon_object *robj;
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struct radeon_object_list lobj;
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uint32_t handle;
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uint32_t flags;
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};
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struct radeon_cs_chunk {
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uint32_t chunk_id;
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uint32_t length_dw;
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uint32_t *kdata;
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};
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struct radeon_cs_parser {
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struct radeon_device *rdev;
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struct drm_file *filp;
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/* chunks */
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unsigned nchunks;
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struct radeon_cs_chunk *chunks;
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uint64_t *chunks_array;
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/* IB */
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unsigned idx;
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/* relocations */
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unsigned nrelocs;
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struct radeon_cs_reloc *relocs;
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struct radeon_cs_reloc **relocs_ptr;
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struct list_head validated;
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/* indices of various chunks */
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int chunk_ib_idx;
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int chunk_relocs_idx;
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struct radeon_ib *ib;
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void *track;
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};
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struct radeon_cs_packet {
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unsigned idx;
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unsigned type;
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unsigned reg;
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unsigned opcode;
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int count;
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unsigned one_reg_wr;
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};
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typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg);
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typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt);
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/*
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* AGP
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*/
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int radeon_agp_init(struct radeon_device *rdev);
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void radeon_agp_fini(struct radeon_device *rdev);
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/*
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* Writeback
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*/
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struct radeon_wb {
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struct radeon_object *wb_obj;
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volatile uint32_t *wb;
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uint64_t gpu_addr;
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};
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/**
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* struct radeon_pm - power management datas
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* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
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* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
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* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
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* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
|
|
* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
|
|
* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
|
|
* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
|
|
* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
|
|
* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
|
|
* @sclk: GPU clock Mhz (core bandwith depends of this clock)
|
|
* @needed_bandwidth: current bandwidth needs
|
|
*
|
|
* It keeps track of various data needed to take powermanagement decision.
|
|
* Bandwith need is used to determine minimun clock of the GPU and memory.
|
|
* Equation between gpu/memory clock and available bandwidth is hw dependent
|
|
* (type of memory, bus size, efficiency, ...)
|
|
*/
|
|
struct radeon_pm {
|
|
fixed20_12 max_bandwidth;
|
|
fixed20_12 igp_sideport_mclk;
|
|
fixed20_12 igp_system_mclk;
|
|
fixed20_12 igp_ht_link_clk;
|
|
fixed20_12 igp_ht_link_width;
|
|
fixed20_12 k8_bandwidth;
|
|
fixed20_12 sideport_bandwidth;
|
|
fixed20_12 ht_bandwidth;
|
|
fixed20_12 core_bandwidth;
|
|
fixed20_12 sclk;
|
|
fixed20_12 needed_bandwidth;
|
|
};
|
|
|
|
|
|
/*
|
|
* Benchmarking
|
|
*/
|
|
void radeon_benchmark(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* Testing
|
|
*/
|
|
void radeon_test_moves(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* Debugfs
|
|
*/
|
|
int radeon_debugfs_add_files(struct radeon_device *rdev,
|
|
struct drm_info_list *files,
|
|
unsigned nfiles);
|
|
int radeon_debugfs_fence_init(struct radeon_device *rdev);
|
|
int r100_debugfs_rbbm_init(struct radeon_device *rdev);
|
|
int r100_debugfs_cp_init(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* ASIC specific functions.
|
|
*/
|
|
struct radeon_asic {
|
|
int (*init)(struct radeon_device *rdev);
|
|
void (*errata)(struct radeon_device *rdev);
|
|
void (*vram_info)(struct radeon_device *rdev);
|
|
int (*gpu_reset)(struct radeon_device *rdev);
|
|
int (*mc_init)(struct radeon_device *rdev);
|
|
void (*mc_fini)(struct radeon_device *rdev);
|
|
int (*wb_init)(struct radeon_device *rdev);
|
|
void (*wb_fini)(struct radeon_device *rdev);
|
|
int (*gart_enable)(struct radeon_device *rdev);
|
|
void (*gart_disable)(struct radeon_device *rdev);
|
|
void (*gart_tlb_flush)(struct radeon_device *rdev);
|
|
int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
|
|
int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
|
|
void (*cp_fini)(struct radeon_device *rdev);
|
|
void (*cp_disable)(struct radeon_device *rdev);
|
|
void (*ring_start)(struct radeon_device *rdev);
|
|
int (*irq_set)(struct radeon_device *rdev);
|
|
int (*irq_process)(struct radeon_device *rdev);
|
|
u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
|
|
void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
|
|
int (*cs_parse)(struct radeon_cs_parser *p);
|
|
int (*copy_blit)(struct radeon_device *rdev,
|
|
uint64_t src_offset,
|
|
uint64_t dst_offset,
|
|
unsigned num_pages,
|
|
struct radeon_fence *fence);
|
|
int (*copy_dma)(struct radeon_device *rdev,
|
|
uint64_t src_offset,
|
|
uint64_t dst_offset,
|
|
unsigned num_pages,
|
|
struct radeon_fence *fence);
|
|
int (*copy)(struct radeon_device *rdev,
|
|
uint64_t src_offset,
|
|
uint64_t dst_offset,
|
|
unsigned num_pages,
|
|
struct radeon_fence *fence);
|
|
void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
|
|
void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
|
|
void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
|
|
void (*set_clock_gating)(struct radeon_device *rdev, int enable);
|
|
int (*set_surface_reg)(struct radeon_device *rdev, int reg,
|
|
uint32_t tiling_flags, uint32_t pitch,
|
|
uint32_t offset, uint32_t obj_size);
|
|
int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
|
|
void (*bandwidth_update)(struct radeon_device *rdev);
|
|
};
|
|
|
|
union radeon_asic_config {
|
|
struct r300_asic r300;
|
|
};
|
|
|
|
|
|
/*
|
|
* IOCTL.
|
|
*/
|
|
int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
|
|
int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
|
|
|
|
/*
|
|
* Core structure, functions and helpers.
|
|
*/
|
|
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
|
|
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
|
|
|
|
struct radeon_device {
|
|
struct drm_device *ddev;
|
|
struct pci_dev *pdev;
|
|
/* ASIC */
|
|
union radeon_asic_config config;
|
|
enum radeon_family family;
|
|
unsigned long flags;
|
|
int usec_timeout;
|
|
enum radeon_pll_errata pll_errata;
|
|
int num_gb_pipes;
|
|
int disp_priority;
|
|
/* BIOS */
|
|
uint8_t *bios;
|
|
bool is_atom_bios;
|
|
uint16_t bios_header_start;
|
|
struct radeon_object *stollen_vga_memory;
|
|
struct fb_info *fbdev_info;
|
|
struct radeon_object *fbdev_robj;
|
|
struct radeon_framebuffer *fbdev_rfb;
|
|
/* Register mmio */
|
|
resource_size_t rmmio_base;
|
|
resource_size_t rmmio_size;
|
|
void *rmmio;
|
|
radeon_rreg_t mc_rreg;
|
|
radeon_wreg_t mc_wreg;
|
|
radeon_rreg_t pll_rreg;
|
|
radeon_wreg_t pll_wreg;
|
|
uint32_t pcie_reg_mask;
|
|
radeon_rreg_t pciep_rreg;
|
|
radeon_wreg_t pciep_wreg;
|
|
struct radeon_clock clock;
|
|
struct radeon_mc mc;
|
|
struct radeon_gart gart;
|
|
struct radeon_mode_info mode_info;
|
|
struct radeon_scratch scratch;
|
|
struct radeon_mman mman;
|
|
struct radeon_fence_driver fence_drv;
|
|
struct radeon_cp cp;
|
|
struct radeon_ib_pool ib_pool;
|
|
struct radeon_irq irq;
|
|
struct radeon_asic *asic;
|
|
struct radeon_gem gem;
|
|
struct radeon_pm pm;
|
|
struct mutex cs_mutex;
|
|
struct radeon_wb wb;
|
|
bool gpu_lockup;
|
|
bool shutdown;
|
|
bool suspend;
|
|
bool need_dma32;
|
|
struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
|
|
const struct firmware *fw; /* firmware */
|
|
};
|
|
|
|
int radeon_device_init(struct radeon_device *rdev,
|
|
struct drm_device *ddev,
|
|
struct pci_dev *pdev,
|
|
uint32_t flags);
|
|
void radeon_device_fini(struct radeon_device *rdev);
|
|
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
|
|
|
|
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
if (reg < 0x10000)
|
|
return readl(((void __iomem *)rdev->rmmio) + reg);
|
|
else {
|
|
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
|
|
return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
|
|
}
|
|
}
|
|
|
|
static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
if (reg < 0x10000)
|
|
writel(v, ((void __iomem *)rdev->rmmio) + reg);
|
|
else {
|
|
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
|
|
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Registers read & write functions.
|
|
*/
|
|
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
|
|
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
|
|
#define RREG32(reg) r100_mm_rreg(rdev, (reg))
|
|
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
|
|
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
|
|
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
|
|
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
|
|
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
|
|
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
|
|
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
|
|
#define WREG32_P(reg, val, mask) \
|
|
do { \
|
|
uint32_t tmp_ = RREG32(reg); \
|
|
tmp_ &= (mask); \
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
WREG32(reg, tmp_); \
|
|
} while (0)
|
|
#define WREG32_PLL_P(reg, val, mask) \
|
|
do { \
|
|
uint32_t tmp_ = RREG32_PLL(reg); \
|
|
tmp_ &= (mask); \
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
WREG32_PLL(reg, tmp_); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Indirect registers accessor
|
|
*/
|
|
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
uint32_t r;
|
|
|
|
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
|
|
r = RREG32(RADEON_PCIE_DATA);
|
|
return r;
|
|
}
|
|
|
|
static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
|
|
WREG32(RADEON_PCIE_DATA, (v));
|
|
}
|
|
|
|
void r100_pll_errata_after_index(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* ASICs helpers.
|
|
*/
|
|
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
|
|
(rdev->pdev->device == 0x5969))
|
|
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
|
|
(rdev->family == CHIP_RV200) || \
|
|
(rdev->family == CHIP_RS100) || \
|
|
(rdev->family == CHIP_RS200) || \
|
|
(rdev->family == CHIP_RV250) || \
|
|
(rdev->family == CHIP_RV280) || \
|
|
(rdev->family == CHIP_RS300))
|
|
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
|
|
(rdev->family == CHIP_RV350) || \
|
|
(rdev->family == CHIP_R350) || \
|
|
(rdev->family == CHIP_RV380) || \
|
|
(rdev->family == CHIP_R420) || \
|
|
(rdev->family == CHIP_R423) || \
|
|
(rdev->family == CHIP_RV410) || \
|
|
(rdev->family == CHIP_RS400) || \
|
|
(rdev->family == CHIP_RS480))
|
|
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
|
|
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
|
|
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
|
|
|
|
|
|
/*
|
|
* BIOS helpers.
|
|
*/
|
|
#define RBIOS8(i) (rdev->bios[i])
|
|
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
|
|
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
|
|
|
|
int radeon_combios_init(struct radeon_device *rdev);
|
|
void radeon_combios_fini(struct radeon_device *rdev);
|
|
int radeon_atombios_init(struct radeon_device *rdev);
|
|
void radeon_atombios_fini(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* RING helpers.
|
|
*/
|
|
#define CP_PACKET0 0x00000000
|
|
#define PACKET0_BASE_INDEX_SHIFT 0
|
|
#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
|
|
#define PACKET0_COUNT_SHIFT 16
|
|
#define PACKET0_COUNT_MASK (0x3fff << 16)
|
|
#define CP_PACKET1 0x40000000
|
|
#define CP_PACKET2 0x80000000
|
|
#define PACKET2_PAD_SHIFT 0
|
|
#define PACKET2_PAD_MASK (0x3fffffff << 0)
|
|
#define CP_PACKET3 0xC0000000
|
|
#define PACKET3_IT_OPCODE_SHIFT 8
|
|
#define PACKET3_IT_OPCODE_MASK (0xff << 8)
|
|
#define PACKET3_COUNT_SHIFT 16
|
|
#define PACKET3_COUNT_MASK (0x3fff << 16)
|
|
/* PACKET3 op code */
|
|
#define PACKET3_NOP 0x10
|
|
#define PACKET3_3D_DRAW_VBUF 0x28
|
|
#define PACKET3_3D_DRAW_IMMD 0x29
|
|
#define PACKET3_3D_DRAW_INDX 0x2A
|
|
#define PACKET3_3D_LOAD_VBPNTR 0x2F
|
|
#define PACKET3_INDX_BUFFER 0x33
|
|
#define PACKET3_3D_DRAW_VBUF_2 0x34
|
|
#define PACKET3_3D_DRAW_IMMD_2 0x35
|
|
#define PACKET3_3D_DRAW_INDX_2 0x36
|
|
#define PACKET3_BITBLT_MULTI 0x9B
|
|
|
|
#define PACKET0(reg, n) (CP_PACKET0 | \
|
|
REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
|
|
REG_SET(PACKET0_COUNT, (n)))
|
|
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
|
|
#define PACKET3(op, n) (CP_PACKET3 | \
|
|
REG_SET(PACKET3_IT_OPCODE, (op)) | \
|
|
REG_SET(PACKET3_COUNT, (n)))
|
|
|
|
#define PACKET_TYPE0 0
|
|
#define PACKET_TYPE1 1
|
|
#define PACKET_TYPE2 2
|
|
#define PACKET_TYPE3 3
|
|
|
|
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
|
|
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
|
|
#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
|
|
#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
|
|
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
|
|
|
|
static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
|
|
{
|
|
#if DRM_DEBUG_CODE
|
|
if (rdev->cp.count_dw <= 0) {
|
|
DRM_ERROR("radeon: writting more dword to ring than expected !\n");
|
|
}
|
|
#endif
|
|
rdev->cp.ring[rdev->cp.wptr++] = v;
|
|
rdev->cp.wptr &= rdev->cp.ptr_mask;
|
|
rdev->cp.count_dw--;
|
|
rdev->cp.ring_free_dw--;
|
|
}
|
|
|
|
|
|
/*
|
|
* ASICs macro.
|
|
*/
|
|
#define radeon_init(rdev) (rdev)->asic->init((rdev))
|
|
#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
|
|
#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
|
|
#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
|
|
#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
|
|
#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
|
|
#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
|
|
#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
|
|
#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
|
|
#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
|
|
#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
|
|
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
|
|
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
|
|
#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
|
|
#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
|
|
#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
|
|
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
|
|
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
|
|
#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
|
|
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
|
|
#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
|
|
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
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#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
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#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
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#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
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#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
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#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
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#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
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#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
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#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
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#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
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#endif
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