![Joe Perches](/assets/img/avatar_default.png)
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
1071 lines
28 KiB
C
1071 lines
28 KiB
C
/*
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* Freescale MPC85xx, MPC83xx DMA Engine support
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*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author:
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* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
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* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
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*
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* Description:
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* DMA engine driver for Freescale MPC8540 DMA controller, which is
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* also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
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* The support for MPC8349 DMA contorller is also added.
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*
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* This driver instructs the DMA controller to issue the PCI Read Multiple
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* command for PCI read operations, instead of using the default PCI Read Line
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* command. Please be aware that this setting may result in read pre-fetching
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* on some platforms.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/of_platform.h>
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#include "fsldma.h"
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static void dma_init(struct fsl_dma_chan *fsl_chan)
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{
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/* Reset the channel */
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
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switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
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case FSL_DMA_IP_85XX:
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/* Set the channel to below modes:
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* EIE - Error interrupt enable
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* EOSIE - End of segments interrupt enable (basic mode)
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* EOLNIE - End of links interrupt enable
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*/
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
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| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
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break;
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case FSL_DMA_IP_83XX:
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/* Set the channel to below modes:
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* EOTIE - End-of-transfer interrupt enable
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* PRC_RM - PCI read multiple
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*/
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE
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| FSL_DMA_MR_PRC_RM, 32);
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break;
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}
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}
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static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
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{
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
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}
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static u32 get_sr(struct fsl_dma_chan *fsl_chan)
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{
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return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
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}
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static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
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struct fsl_dma_ld_hw *hw, u32 count)
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{
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hw->count = CPU_TO_DMA(fsl_chan, count, 32);
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}
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static void set_desc_src(struct fsl_dma_chan *fsl_chan,
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struct fsl_dma_ld_hw *hw, dma_addr_t src)
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{
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u64 snoop_bits;
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snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
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? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
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hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
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}
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static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
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struct fsl_dma_ld_hw *hw, dma_addr_t dest)
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{
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u64 snoop_bits;
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snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
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? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
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hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
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}
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static void set_desc_next(struct fsl_dma_chan *fsl_chan,
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struct fsl_dma_ld_hw *hw, dma_addr_t next)
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{
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u64 snoop_bits;
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snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
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? FSL_DMA_SNEN : 0;
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hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
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}
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static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
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{
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
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}
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static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
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{
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return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
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}
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static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
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{
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
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}
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static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
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{
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return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
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}
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static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
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{
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return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
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}
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static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
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{
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u32 sr = get_sr(fsl_chan);
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return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
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}
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static void dma_start(struct fsl_dma_chan *fsl_chan)
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{
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u32 mr_set = 0;
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if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
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mr_set |= FSL_DMA_MR_EMP_EN;
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} else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
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& ~FSL_DMA_MR_EMP_EN, 32);
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}
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if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
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mr_set |= FSL_DMA_MR_EMS_EN;
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else
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mr_set |= FSL_DMA_MR_CS;
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
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| mr_set, 32);
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}
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static void dma_halt(struct fsl_dma_chan *fsl_chan)
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{
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int i;
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
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32);
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
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| FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
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for (i = 0; i < 100; i++) {
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if (dma_is_idle(fsl_chan))
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break;
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udelay(10);
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}
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if (i >= 100 && !dma_is_idle(fsl_chan))
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dev_err(fsl_chan->dev, "DMA halt timeout!\n");
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}
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static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
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struct fsl_desc_sw *desc)
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{
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u64 snoop_bits;
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snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
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? FSL_DMA_SNEN : 0;
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desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
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DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
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| snoop_bits, 64);
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}
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static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
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struct fsl_desc_sw *new_desc)
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{
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struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
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if (list_empty(&fsl_chan->ld_queue))
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return;
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/* Link to the new descriptor physical address and
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* Enable End-of-segment interrupt for
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* the last link descriptor.
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* (the previous node's next link descriptor)
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*
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* For FSL_DMA_IP_83xx, the snoop enable bit need be set.
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*/
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queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
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new_desc->async_tx.phys | FSL_DMA_EOSIE |
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(((fsl_chan->feature & FSL_DMA_IP_MASK)
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== FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
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}
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/**
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* fsl_chan_set_src_loop_size - Set source address hold transfer size
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* @fsl_chan : Freescale DMA channel
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* @size : Address loop size, 0 for disable loop
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*
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* The set source address hold transfer size. The source
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* address hold or loop transfer size is when the DMA transfer
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* data from source address (SA), if the loop size is 4, the DMA will
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* read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
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* SA + 1 ... and so on.
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*/
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static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
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{
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switch (size) {
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case 0:
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
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(~FSL_DMA_MR_SAHE), 32);
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break;
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case 1:
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case 2:
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case 4:
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case 8:
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
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FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
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32);
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break;
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}
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}
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/**
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* fsl_chan_set_dest_loop_size - Set destination address hold transfer size
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* @fsl_chan : Freescale DMA channel
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* @size : Address loop size, 0 for disable loop
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*
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* The set destination address hold transfer size. The destination
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* address hold or loop transfer size is when the DMA transfer
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* data to destination address (TA), if the loop size is 4, the DMA will
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* write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
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* TA + 1 ... and so on.
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*/
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static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
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{
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switch (size) {
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case 0:
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
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(~FSL_DMA_MR_DAHE), 32);
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break;
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case 1:
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case 2:
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case 4:
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case 8:
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
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FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
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32);
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break;
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}
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}
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/**
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* fsl_chan_toggle_ext_pause - Toggle channel external pause status
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* @fsl_chan : Freescale DMA channel
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* @size : Pause control size, 0 for disable external pause control.
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* The maximum is 1024.
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*
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* The Freescale DMA channel can be controlled by the external
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* signal DREQ#. The pause control size is how many bytes are allowed
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* to transfer before pausing the channel, after which a new assertion
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* of DREQ# resumes channel operation.
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*/
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static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
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{
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if (size > 1024)
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return;
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if (size) {
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DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
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DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
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| ((__ilog2(size) << 24) & 0x0f000000),
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32);
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fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
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} else
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fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
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}
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/**
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* fsl_chan_toggle_ext_start - Toggle channel external start status
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* @fsl_chan : Freescale DMA channel
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* @enable : 0 is disabled, 1 is enabled.
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*
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* If enable the external start, the channel can be started by an
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* external DMA start pin. So the dma_start() does not start the
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* transfer immediately. The DMA channel will wait for the
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* control pin asserted.
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*/
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static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
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{
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if (enable)
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fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
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else
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fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
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}
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static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
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struct fsl_desc_sw *desc;
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unsigned long flags;
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dma_cookie_t cookie;
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/* cookie increment and adding to ld_queue must be atomic */
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spin_lock_irqsave(&fsl_chan->desc_lock, flags);
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cookie = fsl_chan->common.cookie;
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list_for_each_entry(desc, &tx->tx_list, node) {
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cookie++;
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if (cookie < 0)
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cookie = 1;
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desc->async_tx.cookie = cookie;
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}
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fsl_chan->common.cookie = cookie;
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append_ld_queue(fsl_chan, tx_to_fsl_desc(tx));
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list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev);
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spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
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return cookie;
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}
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/**
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* fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
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* @fsl_chan : Freescale DMA channel
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*
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* Return - The descriptor allocated. NULL for failed.
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*/
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static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
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struct fsl_dma_chan *fsl_chan)
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{
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dma_addr_t pdesc;
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struct fsl_desc_sw *desc_sw;
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desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
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if (desc_sw) {
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memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
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dma_async_tx_descriptor_init(&desc_sw->async_tx,
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&fsl_chan->common);
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desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
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desc_sw->async_tx.phys = pdesc;
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}
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return desc_sw;
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}
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/**
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* fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
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* @fsl_chan : Freescale DMA channel
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*
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* This function will create a dma pool for descriptor allocation.
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*
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* Return - The number of descriptors allocated.
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*/
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static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
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/* Has this channel already been allocated? */
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if (fsl_chan->desc_pool)
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return 1;
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/* We need the descriptor to be aligned to 32bytes
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* for meeting FSL DMA specification requirement.
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*/
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fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
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fsl_chan->dev, sizeof(struct fsl_desc_sw),
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32, 0);
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if (!fsl_chan->desc_pool) {
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dev_err(fsl_chan->dev, "No memory for channel %d "
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"descriptor dma pool.\n", fsl_chan->id);
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return 0;
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}
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return 1;
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}
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/**
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* fsl_dma_free_chan_resources - Free all resources of the channel.
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* @fsl_chan : Freescale DMA channel
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*/
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static void fsl_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
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struct fsl_desc_sw *desc, *_desc;
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unsigned long flags;
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dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
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spin_lock_irqsave(&fsl_chan->desc_lock, flags);
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list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
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#ifdef FSL_DMA_LD_DEBUG
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dev_dbg(fsl_chan->dev,
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"LD %p will be released.\n", desc);
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#endif
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list_del(&desc->node);
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/* free link descriptor */
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dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
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}
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spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
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dma_pool_destroy(fsl_chan->desc_pool);
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fsl_chan->desc_pool = NULL;
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}
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static struct dma_async_tx_descriptor *
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fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
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{
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struct fsl_dma_chan *fsl_chan;
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struct fsl_desc_sw *new;
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if (!chan)
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return NULL;
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fsl_chan = to_fsl_chan(chan);
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new = fsl_dma_alloc_descriptor(fsl_chan);
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if (!new) {
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dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
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return NULL;
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}
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new->async_tx.cookie = -EBUSY;
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new->async_tx.flags = flags;
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|
|
/* Insert the link descriptor to the LD ring */
|
|
list_add_tail(&new->node, &new->async_tx.tx_list);
|
|
|
|
/* Set End-of-link to the last link descriptor of new list*/
|
|
set_ld_eol(fsl_chan, new);
|
|
|
|
return &new->async_tx;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
|
|
struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
|
|
size_t len, unsigned long flags)
|
|
{
|
|
struct fsl_dma_chan *fsl_chan;
|
|
struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
|
|
struct list_head *list;
|
|
size_t copy;
|
|
|
|
if (!chan)
|
|
return NULL;
|
|
|
|
if (!len)
|
|
return NULL;
|
|
|
|
fsl_chan = to_fsl_chan(chan);
|
|
|
|
do {
|
|
|
|
/* Allocate the link descriptor from DMA pool */
|
|
new = fsl_dma_alloc_descriptor(fsl_chan);
|
|
if (!new) {
|
|
dev_err(fsl_chan->dev,
|
|
"No free memory for link descriptor\n");
|
|
goto fail;
|
|
}
|
|
#ifdef FSL_DMA_LD_DEBUG
|
|
dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
|
|
#endif
|
|
|
|
copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
|
|
|
|
set_desc_cnt(fsl_chan, &new->hw, copy);
|
|
set_desc_src(fsl_chan, &new->hw, dma_src);
|
|
set_desc_dest(fsl_chan, &new->hw, dma_dest);
|
|
|
|
if (!first)
|
|
first = new;
|
|
else
|
|
set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
|
|
|
|
new->async_tx.cookie = 0;
|
|
async_tx_ack(&new->async_tx);
|
|
|
|
prev = new;
|
|
len -= copy;
|
|
dma_src += copy;
|
|
dma_dest += copy;
|
|
|
|
/* Insert the link descriptor to the LD ring */
|
|
list_add_tail(&new->node, &first->async_tx.tx_list);
|
|
} while (len);
|
|
|
|
new->async_tx.flags = flags; /* client is in control of this ack */
|
|
new->async_tx.cookie = -EBUSY;
|
|
|
|
/* Set End-of-link to the last link descriptor of new list*/
|
|
set_ld_eol(fsl_chan, new);
|
|
|
|
return &first->async_tx;
|
|
|
|
fail:
|
|
if (!first)
|
|
return NULL;
|
|
|
|
list = &first->async_tx.tx_list;
|
|
list_for_each_entry_safe_reverse(new, prev, list, node) {
|
|
list_del(&new->node);
|
|
dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_update_completed_cookie - Update the completed cookie.
|
|
* @fsl_chan : Freescale DMA channel
|
|
*/
|
|
static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
|
|
{
|
|
struct fsl_desc_sw *cur_desc, *desc;
|
|
dma_addr_t ld_phy;
|
|
|
|
ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
|
|
|
|
if (ld_phy) {
|
|
cur_desc = NULL;
|
|
list_for_each_entry(desc, &fsl_chan->ld_queue, node)
|
|
if (desc->async_tx.phys == ld_phy) {
|
|
cur_desc = desc;
|
|
break;
|
|
}
|
|
|
|
if (cur_desc && cur_desc->async_tx.cookie) {
|
|
if (dma_is_idle(fsl_chan))
|
|
fsl_chan->completed_cookie =
|
|
cur_desc->async_tx.cookie;
|
|
else
|
|
fsl_chan->completed_cookie =
|
|
cur_desc->async_tx.cookie - 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* fsl_chan_ld_cleanup - Clean up link descriptors
|
|
* @fsl_chan : Freescale DMA channel
|
|
*
|
|
* This function clean up the ld_queue of DMA channel.
|
|
* If 'in_intr' is set, the function will move the link descriptor to
|
|
* the recycle list. Otherwise, free it directly.
|
|
*/
|
|
static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
|
|
{
|
|
struct fsl_desc_sw *desc, *_desc;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&fsl_chan->desc_lock, flags);
|
|
|
|
dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
|
|
fsl_chan->completed_cookie);
|
|
list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
|
|
dma_async_tx_callback callback;
|
|
void *callback_param;
|
|
|
|
if (dma_async_is_complete(desc->async_tx.cookie,
|
|
fsl_chan->completed_cookie, fsl_chan->common.cookie)
|
|
== DMA_IN_PROGRESS)
|
|
break;
|
|
|
|
callback = desc->async_tx.callback;
|
|
callback_param = desc->async_tx.callback_param;
|
|
|
|
/* Remove from ld_queue list */
|
|
list_del(&desc->node);
|
|
|
|
dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
|
|
desc);
|
|
dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
|
|
|
|
/* Run the link descriptor callback function */
|
|
if (callback) {
|
|
spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
|
|
dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
|
|
desc);
|
|
callback(callback_param);
|
|
spin_lock_irqsave(&fsl_chan->desc_lock, flags);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
|
|
}
|
|
|
|
/**
|
|
* fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
|
|
* @fsl_chan : Freescale DMA channel
|
|
*/
|
|
static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
|
|
{
|
|
struct list_head *ld_node;
|
|
dma_addr_t next_dest_addr;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&fsl_chan->desc_lock, flags);
|
|
|
|
if (!dma_is_idle(fsl_chan))
|
|
goto out_unlock;
|
|
|
|
dma_halt(fsl_chan);
|
|
|
|
/* If there are some link descriptors
|
|
* not transfered in queue. We need to start it.
|
|
*/
|
|
|
|
/* Find the first un-transfer desciptor */
|
|
for (ld_node = fsl_chan->ld_queue.next;
|
|
(ld_node != &fsl_chan->ld_queue)
|
|
&& (dma_async_is_complete(
|
|
to_fsl_desc(ld_node)->async_tx.cookie,
|
|
fsl_chan->completed_cookie,
|
|
fsl_chan->common.cookie) == DMA_SUCCESS);
|
|
ld_node = ld_node->next);
|
|
|
|
if (ld_node != &fsl_chan->ld_queue) {
|
|
/* Get the ld start address from ld_queue */
|
|
next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
|
|
dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
|
|
(unsigned long long)next_dest_addr);
|
|
set_cdar(fsl_chan, next_dest_addr);
|
|
dma_start(fsl_chan);
|
|
} else {
|
|
set_cdar(fsl_chan, 0);
|
|
set_ndar(fsl_chan, 0);
|
|
}
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_memcpy_issue_pending - Issue the DMA start command
|
|
* @fsl_chan : Freescale DMA channel
|
|
*/
|
|
static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
|
|
|
|
#ifdef FSL_DMA_LD_DEBUG
|
|
struct fsl_desc_sw *ld;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&fsl_chan->desc_lock, flags);
|
|
if (list_empty(&fsl_chan->ld_queue)) {
|
|
spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
|
|
return;
|
|
}
|
|
|
|
dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
|
|
list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
|
|
int i;
|
|
dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
|
|
fsl_chan->id, ld->async_tx.phys);
|
|
for (i = 0; i < 8; i++)
|
|
dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
|
|
i, *(((u32 *)&ld->hw) + i));
|
|
}
|
|
dev_dbg(fsl_chan->dev, "----------------\n");
|
|
spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
|
|
#endif
|
|
|
|
fsl_chan_xfer_ld_queue(fsl_chan);
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_is_complete - Determine the DMA status
|
|
* @fsl_chan : Freescale DMA channel
|
|
*/
|
|
static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
|
|
dma_cookie_t cookie,
|
|
dma_cookie_t *done,
|
|
dma_cookie_t *used)
|
|
{
|
|
struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
|
|
dma_cookie_t last_used;
|
|
dma_cookie_t last_complete;
|
|
|
|
fsl_chan_ld_cleanup(fsl_chan);
|
|
|
|
last_used = chan->cookie;
|
|
last_complete = fsl_chan->completed_cookie;
|
|
|
|
if (done)
|
|
*done = last_complete;
|
|
|
|
if (used)
|
|
*used = last_used;
|
|
|
|
return dma_async_is_complete(cookie, last_complete, last_used);
|
|
}
|
|
|
|
static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
|
|
{
|
|
struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
|
|
u32 stat;
|
|
int update_cookie = 0;
|
|
int xfer_ld_q = 0;
|
|
|
|
stat = get_sr(fsl_chan);
|
|
dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
|
|
fsl_chan->id, stat);
|
|
set_sr(fsl_chan, stat); /* Clear the event register */
|
|
|
|
stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
|
|
if (!stat)
|
|
return IRQ_NONE;
|
|
|
|
if (stat & FSL_DMA_SR_TE)
|
|
dev_err(fsl_chan->dev, "Transfer Error!\n");
|
|
|
|
/* Programming Error
|
|
* The DMA_INTERRUPT async_tx is a NULL transfer, which will
|
|
* triger a PE interrupt.
|
|
*/
|
|
if (stat & FSL_DMA_SR_PE) {
|
|
dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
|
|
if (get_bcr(fsl_chan) == 0) {
|
|
/* BCR register is 0, this is a DMA_INTERRUPT async_tx.
|
|
* Now, update the completed cookie, and continue the
|
|
* next uncompleted transfer.
|
|
*/
|
|
update_cookie = 1;
|
|
xfer_ld_q = 1;
|
|
}
|
|
stat &= ~FSL_DMA_SR_PE;
|
|
}
|
|
|
|
/* If the link descriptor segment transfer finishes,
|
|
* we will recycle the used descriptor.
|
|
*/
|
|
if (stat & FSL_DMA_SR_EOSI) {
|
|
dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
|
|
dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
|
|
(unsigned long long)get_cdar(fsl_chan),
|
|
(unsigned long long)get_ndar(fsl_chan));
|
|
stat &= ~FSL_DMA_SR_EOSI;
|
|
update_cookie = 1;
|
|
}
|
|
|
|
/* For MPC8349, EOCDI event need to update cookie
|
|
* and start the next transfer if it exist.
|
|
*/
|
|
if (stat & FSL_DMA_SR_EOCDI) {
|
|
dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
|
|
stat &= ~FSL_DMA_SR_EOCDI;
|
|
update_cookie = 1;
|
|
xfer_ld_q = 1;
|
|
}
|
|
|
|
/* If it current transfer is the end-of-transfer,
|
|
* we should clear the Channel Start bit for
|
|
* prepare next transfer.
|
|
*/
|
|
if (stat & FSL_DMA_SR_EOLNI) {
|
|
dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
|
|
stat &= ~FSL_DMA_SR_EOLNI;
|
|
xfer_ld_q = 1;
|
|
}
|
|
|
|
if (update_cookie)
|
|
fsl_dma_update_completed_cookie(fsl_chan);
|
|
if (xfer_ld_q)
|
|
fsl_chan_xfer_ld_queue(fsl_chan);
|
|
if (stat)
|
|
dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
|
|
stat);
|
|
|
|
dev_dbg(fsl_chan->dev, "event: Exit\n");
|
|
tasklet_schedule(&fsl_chan->tasklet);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
|
|
{
|
|
struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
|
|
u32 gsr;
|
|
int ch_nr;
|
|
|
|
gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
|
|
: in_le32(fdev->reg_base);
|
|
ch_nr = (32 - ffs(gsr)) / 8;
|
|
|
|
return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
|
|
fdev->chan[ch_nr]) : IRQ_NONE;
|
|
}
|
|
|
|
static void dma_do_tasklet(unsigned long data)
|
|
{
|
|
struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
|
|
fsl_chan_ld_cleanup(fsl_chan);
|
|
}
|
|
|
|
static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
|
|
struct device_node *node, u32 feature, const char *compatible)
|
|
{
|
|
struct fsl_dma_chan *new_fsl_chan;
|
|
int err;
|
|
|
|
/* alloc channel */
|
|
new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
|
|
if (!new_fsl_chan) {
|
|
dev_err(fdev->dev, "No free memory for allocating "
|
|
"dma channels!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* get dma channel register base */
|
|
err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
|
|
if (err) {
|
|
dev_err(fdev->dev, "Can't get %s property 'reg'\n",
|
|
node->full_name);
|
|
goto err_no_reg;
|
|
}
|
|
|
|
new_fsl_chan->feature = feature;
|
|
|
|
if (!fdev->feature)
|
|
fdev->feature = new_fsl_chan->feature;
|
|
|
|
/* If the DMA device's feature is different than its channels',
|
|
* report the bug.
|
|
*/
|
|
WARN_ON(fdev->feature != new_fsl_chan->feature);
|
|
|
|
new_fsl_chan->dev = fdev->dev;
|
|
new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
|
|
new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
|
|
|
|
new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
|
|
if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
|
|
dev_err(fdev->dev, "There is no %d channel!\n",
|
|
new_fsl_chan->id);
|
|
err = -EINVAL;
|
|
goto err_no_chan;
|
|
}
|
|
fdev->chan[new_fsl_chan->id] = new_fsl_chan;
|
|
tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
|
|
(unsigned long)new_fsl_chan);
|
|
|
|
/* Init the channel */
|
|
dma_init(new_fsl_chan);
|
|
|
|
/* Clear cdar registers */
|
|
set_cdar(new_fsl_chan, 0);
|
|
|
|
switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
|
|
case FSL_DMA_IP_85XX:
|
|
new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
|
|
case FSL_DMA_IP_83XX:
|
|
new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
|
|
new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
|
|
new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
|
|
}
|
|
|
|
spin_lock_init(&new_fsl_chan->desc_lock);
|
|
INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
|
|
|
|
new_fsl_chan->common.device = &fdev->common;
|
|
|
|
/* Add the channel to DMA device channel list */
|
|
list_add_tail(&new_fsl_chan->common.device_node,
|
|
&fdev->common.channels);
|
|
fdev->common.chancnt++;
|
|
|
|
new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
|
|
if (new_fsl_chan->irq != NO_IRQ) {
|
|
err = request_irq(new_fsl_chan->irq,
|
|
&fsl_dma_chan_do_interrupt, IRQF_SHARED,
|
|
"fsldma-channel", new_fsl_chan);
|
|
if (err) {
|
|
dev_err(fdev->dev, "DMA channel %s request_irq error "
|
|
"with return %d\n", node->full_name, err);
|
|
goto err_no_irq;
|
|
}
|
|
}
|
|
|
|
dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
|
|
compatible,
|
|
new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
|
|
|
|
return 0;
|
|
|
|
err_no_irq:
|
|
list_del(&new_fsl_chan->common.device_node);
|
|
err_no_chan:
|
|
iounmap(new_fsl_chan->reg_base);
|
|
err_no_reg:
|
|
kfree(new_fsl_chan);
|
|
return err;
|
|
}
|
|
|
|
static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
|
|
{
|
|
if (fchan->irq != NO_IRQ)
|
|
free_irq(fchan->irq, fchan);
|
|
list_del(&fchan->common.device_node);
|
|
iounmap(fchan->reg_base);
|
|
kfree(fchan);
|
|
}
|
|
|
|
static int __devinit of_fsl_dma_probe(struct of_device *dev,
|
|
const struct of_device_id *match)
|
|
{
|
|
int err;
|
|
struct fsl_dma_device *fdev;
|
|
struct device_node *child;
|
|
|
|
fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
|
|
if (!fdev) {
|
|
dev_err(&dev->dev, "No enough memory for 'priv'\n");
|
|
return -ENOMEM;
|
|
}
|
|
fdev->dev = &dev->dev;
|
|
INIT_LIST_HEAD(&fdev->common.channels);
|
|
|
|
/* get DMA controller register base */
|
|
err = of_address_to_resource(dev->node, 0, &fdev->reg);
|
|
if (err) {
|
|
dev_err(&dev->dev, "Can't get %s property 'reg'\n",
|
|
dev->node->full_name);
|
|
goto err_no_reg;
|
|
}
|
|
|
|
dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
|
|
"controller at 0x%llx...\n",
|
|
match->compatible, (unsigned long long)fdev->reg.start);
|
|
fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
|
|
- fdev->reg.start + 1);
|
|
|
|
dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
|
|
dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
|
|
fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
|
|
fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
|
|
fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
|
|
fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
|
|
fdev->common.device_is_tx_complete = fsl_dma_is_complete;
|
|
fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
|
|
fdev->common.dev = &dev->dev;
|
|
|
|
fdev->irq = irq_of_parse_and_map(dev->node, 0);
|
|
if (fdev->irq != NO_IRQ) {
|
|
err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
|
|
"fsldma-device", fdev);
|
|
if (err) {
|
|
dev_err(&dev->dev, "DMA device request_irq error "
|
|
"with return %d\n", err);
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
dev_set_drvdata(&(dev->dev), fdev);
|
|
|
|
/* We cannot use of_platform_bus_probe() because there is no
|
|
* of_platform_bus_remove. Instead, we manually instantiate every DMA
|
|
* channel object.
|
|
*/
|
|
for_each_child_of_node(dev->node, child) {
|
|
if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
|
|
fsl_dma_chan_probe(fdev, child,
|
|
FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
|
|
"fsl,eloplus-dma-channel");
|
|
if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
|
|
fsl_dma_chan_probe(fdev, child,
|
|
FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
|
|
"fsl,elo-dma-channel");
|
|
}
|
|
|
|
dma_async_device_register(&fdev->common);
|
|
return 0;
|
|
|
|
err:
|
|
iounmap(fdev->reg_base);
|
|
err_no_reg:
|
|
kfree(fdev);
|
|
return err;
|
|
}
|
|
|
|
static int of_fsl_dma_remove(struct of_device *of_dev)
|
|
{
|
|
struct fsl_dma_device *fdev;
|
|
unsigned int i;
|
|
|
|
fdev = dev_get_drvdata(&of_dev->dev);
|
|
|
|
dma_async_device_unregister(&fdev->common);
|
|
|
|
for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
|
|
if (fdev->chan[i])
|
|
fsl_dma_chan_remove(fdev->chan[i]);
|
|
|
|
if (fdev->irq != NO_IRQ)
|
|
free_irq(fdev->irq, fdev);
|
|
|
|
iounmap(fdev->reg_base);
|
|
|
|
kfree(fdev);
|
|
dev_set_drvdata(&of_dev->dev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id of_fsl_dma_ids[] = {
|
|
{ .compatible = "fsl,eloplus-dma", },
|
|
{ .compatible = "fsl,elo-dma", },
|
|
{}
|
|
};
|
|
|
|
static struct of_platform_driver of_fsl_dma_driver = {
|
|
.name = "fsl-elo-dma",
|
|
.match_table = of_fsl_dma_ids,
|
|
.probe = of_fsl_dma_probe,
|
|
.remove = of_fsl_dma_remove,
|
|
};
|
|
|
|
static __init int of_fsl_dma_init(void)
|
|
{
|
|
int ret;
|
|
|
|
pr_info("Freescale Elo / Elo Plus DMA driver\n");
|
|
|
|
ret = of_register_platform_driver(&of_fsl_dma_driver);
|
|
if (ret)
|
|
pr_err("fsldma: failed to register platform driver\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit of_fsl_dma_exit(void)
|
|
{
|
|
of_unregister_platform_driver(&of_fsl_dma_driver);
|
|
}
|
|
|
|
subsys_initcall(of_fsl_dma_init);
|
|
module_exit(of_fsl_dma_exit);
|
|
|
|
MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
|
|
MODULE_LICENSE("GPL");
|