c658eac628
The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* This header file describes this specific Xtensa processor's TIE extensions
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* that extend basic Xtensa core functionality. It is customized to this
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* Xtensa processor configuration.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999-2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_CORE_TIE_H
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#define _XTENSA_CORE_TIE_H
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#define XCHAL_CP_NUM 0 /* number of coprocessors */
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#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
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#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
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#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
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/* Basic parameters of each coprocessor: */
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#define XCHAL_CP7_NAME "XTIOP"
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#define XCHAL_CP7_IDENT XTIOP
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#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
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#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
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#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
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/* Filler info for unassigned coprocessors, to simplify arrays etc: */
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#define XCHAL_NCP_SA_SIZE 0
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#define XCHAL_NCP_SA_ALIGN 1
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#define XCHAL_CP0_SA_SIZE 0
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#define XCHAL_CP0_SA_ALIGN 1
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#define XCHAL_CP1_SA_SIZE 0
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#define XCHAL_CP1_SA_ALIGN 1
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#define XCHAL_CP2_SA_SIZE 0
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#define XCHAL_CP2_SA_ALIGN 1
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#define XCHAL_CP3_SA_SIZE 0
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#define XCHAL_CP3_SA_ALIGN 1
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#define XCHAL_CP4_SA_SIZE 0
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#define XCHAL_CP4_SA_ALIGN 1
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#define XCHAL_CP5_SA_SIZE 0
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#define XCHAL_CP5_SA_ALIGN 1
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#define XCHAL_CP6_SA_SIZE 0
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#define XCHAL_CP6_SA_ALIGN 1
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/* Save area for non-coprocessor optional and custom (TIE) state: */
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#define XCHAL_NCP_SA_SIZE 0
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#define XCHAL_NCP_SA_ALIGN 1
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/* Total save area for optional and custom state (NCP + CPn): */
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#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */
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#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */
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#define XCHAL_NCP_SA_NUM 0
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#define XCHAL_NCP_SA_LIST(s)
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#define XCHAL_CP0_SA_NUM 0
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#define XCHAL_CP0_SA_LIST(s)
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#define XCHAL_CP1_SA_NUM 0
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#define XCHAL_CP1_SA_LIST(s)
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#define XCHAL_CP2_SA_NUM 0
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#define XCHAL_CP2_SA_LIST(s)
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#define XCHAL_CP3_SA_NUM 0
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#define XCHAL_CP3_SA_LIST(s)
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#define XCHAL_CP4_SA_NUM 0
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#define XCHAL_CP4_SA_LIST(s)
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#define XCHAL_CP5_SA_NUM 0
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#define XCHAL_CP5_SA_LIST(s)
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#define XCHAL_CP6_SA_NUM 0
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#define XCHAL_CP6_SA_LIST(s)
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#define XCHAL_CP7_SA_NUM 0
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#define XCHAL_CP7_SA_LIST(s)
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/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
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#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
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#endif /*_XTENSA_CORE_TIE_H*/
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