![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
634 lines
16 KiB
C
634 lines
16 KiB
C
/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Common functions for DMA access on PA Semi PWRficient
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <asm/pasemi_dma.h>
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#define MAX_TXCH 64
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#define MAX_RXCH 64
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#define MAX_FLAGS 64
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#define MAX_FUN 8
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static struct pasdma_status *dma_status;
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static void __iomem *iob_regs;
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static void __iomem *mac_regs[6];
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static void __iomem *dma_regs;
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static int base_hw_irq;
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static int num_txch, num_rxch;
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static struct pci_dev *dma_pdev;
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/* Bitmaps to handle allocation of channels */
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static DECLARE_BITMAP(txch_free, MAX_TXCH);
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static DECLARE_BITMAP(rxch_free, MAX_RXCH);
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static DECLARE_BITMAP(flags_free, MAX_FLAGS);
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static DECLARE_BITMAP(fun_free, MAX_FUN);
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/* pasemi_read_iob_reg - read IOB register
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* @reg: Register to read (offset into PCI CFG space)
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*/
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unsigned int pasemi_read_iob_reg(unsigned int reg)
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{
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return in_le32(iob_regs+reg);
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}
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EXPORT_SYMBOL(pasemi_read_iob_reg);
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/* pasemi_write_iob_reg - write IOB register
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* @reg: Register to write to (offset into PCI CFG space)
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* @val: Value to write
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*/
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void pasemi_write_iob_reg(unsigned int reg, unsigned int val)
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{
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out_le32(iob_regs+reg, val);
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}
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EXPORT_SYMBOL(pasemi_write_iob_reg);
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/* pasemi_read_mac_reg - read MAC register
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* @intf: MAC interface
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* @reg: Register to read (offset into PCI CFG space)
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*/
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unsigned int pasemi_read_mac_reg(int intf, unsigned int reg)
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{
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return in_le32(mac_regs[intf]+reg);
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}
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EXPORT_SYMBOL(pasemi_read_mac_reg);
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/* pasemi_write_mac_reg - write MAC register
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* @intf: MAC interface
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* @reg: Register to write to (offset into PCI CFG space)
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* @val: Value to write
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*/
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void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val)
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{
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out_le32(mac_regs[intf]+reg, val);
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}
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EXPORT_SYMBOL(pasemi_write_mac_reg);
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/* pasemi_read_dma_reg - read DMA register
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* @reg: Register to read (offset into PCI CFG space)
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*/
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unsigned int pasemi_read_dma_reg(unsigned int reg)
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{
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return in_le32(dma_regs+reg);
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}
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EXPORT_SYMBOL(pasemi_read_dma_reg);
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/* pasemi_write_dma_reg - write DMA register
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* @reg: Register to write to (offset into PCI CFG space)
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* @val: Value to write
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*/
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void pasemi_write_dma_reg(unsigned int reg, unsigned int val)
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{
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out_le32(dma_regs+reg, val);
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}
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EXPORT_SYMBOL(pasemi_write_dma_reg);
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static int pasemi_alloc_tx_chan(enum pasemi_dmachan_type type)
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{
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int bit;
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int start, limit;
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switch (type & (TXCHAN_EVT0|TXCHAN_EVT1)) {
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case TXCHAN_EVT0:
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start = 0;
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limit = 10;
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break;
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case TXCHAN_EVT1:
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start = 10;
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limit = MAX_TXCH;
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break;
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default:
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start = 0;
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limit = MAX_TXCH;
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break;
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}
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retry:
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bit = find_next_bit(txch_free, MAX_TXCH, start);
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if (bit >= limit)
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return -ENOSPC;
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if (!test_and_clear_bit(bit, txch_free))
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goto retry;
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return bit;
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}
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static void pasemi_free_tx_chan(int chan)
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{
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BUG_ON(test_bit(chan, txch_free));
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set_bit(chan, txch_free);
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}
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static int pasemi_alloc_rx_chan(void)
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{
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int bit;
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retry:
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bit = find_first_bit(rxch_free, MAX_RXCH);
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if (bit >= MAX_TXCH)
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return -ENOSPC;
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if (!test_and_clear_bit(bit, rxch_free))
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goto retry;
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return bit;
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}
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static void pasemi_free_rx_chan(int chan)
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{
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BUG_ON(test_bit(chan, rxch_free));
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set_bit(chan, rxch_free);
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}
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/* pasemi_dma_alloc_chan - Allocate a DMA channel
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* @type: Type of channel to allocate
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* @total_size: Total size of structure to allocate (to allow for more
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* room behind the structure to be used by the client)
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* @offset: Offset in bytes from start of the total structure to the beginning
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* of struct pasemi_dmachan. Needed when struct pasemi_dmachan is
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* not the first member of the client structure.
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*
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* pasemi_dma_alloc_chan allocates a DMA channel for use by a client. The
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* type argument specifies whether it's a RX or TX channel, and in the case
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* of TX channels which group it needs to belong to (if any).
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*
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* Returns a pointer to the total structure allocated on success, NULL
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* on failure.
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*/
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void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
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int total_size, int offset)
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{
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void *buf;
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struct pasemi_dmachan *chan;
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int chno;
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BUG_ON(total_size < sizeof(struct pasemi_dmachan));
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buf = kzalloc(total_size, GFP_KERNEL);
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if (!buf)
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return NULL;
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chan = buf + offset;
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chan->priv = buf;
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switch (type & (TXCHAN|RXCHAN)) {
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case RXCHAN:
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chno = pasemi_alloc_rx_chan();
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chan->chno = chno;
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chan->irq = irq_create_mapping(NULL,
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base_hw_irq + num_txch + chno);
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chan->status = &dma_status->rx_sta[chno];
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break;
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case TXCHAN:
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chno = pasemi_alloc_tx_chan(type);
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chan->chno = chno;
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chan->irq = irq_create_mapping(NULL, base_hw_irq + chno);
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chan->status = &dma_status->tx_sta[chno];
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break;
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}
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chan->chan_type = type;
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return chan;
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_chan);
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/* pasemi_dma_free_chan - Free a previously allocated channel
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* @chan: Channel to free
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*
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* Frees a previously allocated channel. It will also deallocate any
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* descriptor ring associated with the channel, if allocated.
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*/
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void pasemi_dma_free_chan(struct pasemi_dmachan *chan)
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{
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if (chan->ring_virt)
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pasemi_dma_free_ring(chan);
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switch (chan->chan_type & (RXCHAN|TXCHAN)) {
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case RXCHAN:
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pasemi_free_rx_chan(chan->chno);
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break;
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case TXCHAN:
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pasemi_free_tx_chan(chan->chno);
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break;
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}
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kfree(chan->priv);
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}
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EXPORT_SYMBOL(pasemi_dma_free_chan);
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/* pasemi_dma_alloc_ring - Allocate descriptor ring for a channel
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* @chan: Channel for which to allocate
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* @ring_size: Ring size in 64-bit (8-byte) words
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*
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* Allocate a descriptor ring for a channel. Returns 0 on success, errno
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* on failure. The passed in struct pasemi_dmachan is updated with the
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* virtual and DMA addresses of the ring.
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*/
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int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size)
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{
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BUG_ON(chan->ring_virt);
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chan->ring_size = ring_size;
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chan->ring_virt = dma_alloc_coherent(&dma_pdev->dev,
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ring_size * sizeof(u64),
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&chan->ring_dma, GFP_KERNEL);
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if (!chan->ring_virt)
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return -ENOMEM;
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memset(chan->ring_virt, 0, ring_size * sizeof(u64));
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return 0;
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_ring);
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/* pasemi_dma_free_ring - Free an allocated descriptor ring for a channel
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* @chan: Channel for which to free the descriptor ring
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*
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* Frees a previously allocated descriptor ring for a channel.
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*/
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void pasemi_dma_free_ring(struct pasemi_dmachan *chan)
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{
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BUG_ON(!chan->ring_virt);
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dma_free_coherent(&dma_pdev->dev, chan->ring_size * sizeof(u64),
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chan->ring_virt, chan->ring_dma);
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chan->ring_virt = NULL;
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chan->ring_size = 0;
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chan->ring_dma = 0;
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}
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EXPORT_SYMBOL(pasemi_dma_free_ring);
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/* pasemi_dma_start_chan - Start a DMA channel
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* @chan: Channel to start
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* @cmdsta: Additional CCMDSTA/TCMDSTA bits to write
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*
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* Enables (starts) a DMA channel with optional additional arguments.
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*/
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void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, const u32 cmdsta)
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{
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if (chan->chan_type == RXCHAN)
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pasemi_write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno),
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cmdsta | PAS_DMA_RXCHAN_CCMDSTA_EN);
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else
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pasemi_write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno),
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cmdsta | PAS_DMA_TXCHAN_TCMDSTA_EN);
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}
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EXPORT_SYMBOL(pasemi_dma_start_chan);
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/* pasemi_dma_stop_chan - Stop a DMA channel
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* @chan: Channel to stop
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*
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* Stops (disables) a DMA channel. This is done by setting the ST bit in the
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* CMDSTA register and waiting on the ACT (active) bit to clear, then
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* finally disabling the whole channel.
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*
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* This function will only try for a short while for the channel to stop, if
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* it doesn't it will return failure.
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*
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* Returns 1 on success, 0 on failure.
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*/
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#define MAX_RETRIES 5000
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int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan)
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{
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int reg, retries;
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u32 sta;
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if (chan->chan_type == RXCHAN) {
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reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno);
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pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST);
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for (retries = 0; retries < MAX_RETRIES; retries++) {
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sta = pasemi_read_dma_reg(reg);
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if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) {
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pasemi_write_dma_reg(reg, 0);
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return 1;
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}
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cond_resched();
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}
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} else {
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reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno);
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pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST);
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for (retries = 0; retries < MAX_RETRIES; retries++) {
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sta = pasemi_read_dma_reg(reg);
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if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) {
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pasemi_write_dma_reg(reg, 0);
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return 1;
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}
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cond_resched();
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(pasemi_dma_stop_chan);
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/* pasemi_dma_alloc_buf - Allocate a buffer to use for DMA
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* @chan: Channel to allocate for
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* @size: Size of buffer in bytes
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* @handle: DMA handle
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*
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* Allocate a buffer to be used by the DMA engine for read/write,
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* similar to dma_alloc_coherent().
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*
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* Returns the virtual address of the buffer, or NULL in case of failure.
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*/
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void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
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dma_addr_t *handle)
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{
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return dma_alloc_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_buf);
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/* pasemi_dma_free_buf - Free a buffer used for DMA
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* @chan: Channel the buffer was allocated for
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* @size: Size of buffer in bytes
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* @handle: DMA handle
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*
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* Frees a previously allocated buffer.
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*/
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void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
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dma_addr_t *handle)
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{
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dma_free_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL);
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}
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EXPORT_SYMBOL(pasemi_dma_free_buf);
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/* pasemi_dma_alloc_flag - Allocate a flag (event) for channel syncronization
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*
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* Allocates a flag for use with channel syncronization (event descriptors).
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* Returns allocated flag (0-63), < 0 on error.
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*/
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int pasemi_dma_alloc_flag(void)
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{
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int bit;
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retry:
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bit = find_next_bit(flags_free, MAX_FLAGS, 0);
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if (bit >= MAX_FLAGS)
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return -ENOSPC;
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if (!test_and_clear_bit(bit, flags_free))
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goto retry;
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return bit;
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}
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EXPORT_SYMBOL(pasemi_dma_alloc_flag);
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/* pasemi_dma_free_flag - Deallocates a flag (event)
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* @flag: Flag number to deallocate
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*
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* Frees up a flag so it can be reused for other purposes.
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*/
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void pasemi_dma_free_flag(int flag)
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{
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BUG_ON(test_bit(flag, flags_free));
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BUG_ON(flag >= MAX_FLAGS);
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set_bit(flag, flags_free);
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}
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EXPORT_SYMBOL(pasemi_dma_free_flag);
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/* pasemi_dma_set_flag - Sets a flag (event) to 1
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* @flag: Flag number to set active
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*
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* Sets the flag provided to 1.
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*/
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void pasemi_dma_set_flag(int flag)
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{
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BUG_ON(flag >= MAX_FLAGS);
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if (flag < 32)
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pasemi_write_dma_reg(PAS_DMA_TXF_SFLG0, 1 << flag);
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else
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pasemi_write_dma_reg(PAS_DMA_TXF_SFLG1, 1 << flag);
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}
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EXPORT_SYMBOL(pasemi_dma_set_flag);
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/* pasemi_dma_clear_flag - Sets a flag (event) to 0
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* @flag: Flag number to set inactive
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*
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* Sets the flag provided to 0.
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*/
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void pasemi_dma_clear_flag(int flag)
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{
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BUG_ON(flag >= MAX_FLAGS);
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if (flag < 32)
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pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 1 << flag);
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else
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pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 1 << flag);
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}
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EXPORT_SYMBOL(pasemi_dma_clear_flag);
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/* pasemi_dma_alloc_fun - Allocate a function engine
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*
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* Allocates a function engine to use for crypto/checksum offload
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* Returns allocated engine (0-8), < 0 on error.
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*/
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int pasemi_dma_alloc_fun(void)
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{
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int bit;
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retry:
|
|
bit = find_next_bit(fun_free, MAX_FLAGS, 0);
|
|
if (bit >= MAX_FLAGS)
|
|
return -ENOSPC;
|
|
if (!test_and_clear_bit(bit, fun_free))
|
|
goto retry;
|
|
|
|
return bit;
|
|
}
|
|
EXPORT_SYMBOL(pasemi_dma_alloc_fun);
|
|
|
|
|
|
/* pasemi_dma_free_fun - Deallocates a function engine
|
|
* @flag: Engine number to deallocate
|
|
*
|
|
* Frees up a function engine so it can be used for other purposes.
|
|
*/
|
|
void pasemi_dma_free_fun(int fun)
|
|
{
|
|
BUG_ON(test_bit(fun, fun_free));
|
|
BUG_ON(fun >= MAX_FLAGS);
|
|
set_bit(fun, fun_free);
|
|
}
|
|
EXPORT_SYMBOL(pasemi_dma_free_fun);
|
|
|
|
|
|
static void *map_onedev(struct pci_dev *p, int index)
|
|
{
|
|
struct device_node *dn;
|
|
void __iomem *ret;
|
|
|
|
dn = pci_device_to_OF_node(p);
|
|
if (!dn)
|
|
goto fallback;
|
|
|
|
ret = of_iomap(dn, index);
|
|
if (!ret)
|
|
goto fallback;
|
|
|
|
return ret;
|
|
fallback:
|
|
/* This is hardcoded and ugly, but we have some firmware versions
|
|
* that don't provide the register space in the device tree. Luckily
|
|
* they are at well-known locations so we can just do the math here.
|
|
*/
|
|
return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
|
|
}
|
|
|
|
/* pasemi_dma_init - Initialize the PA Semi DMA library
|
|
*
|
|
* This function initializes the DMA library. It must be called before
|
|
* any other function in the library.
|
|
*
|
|
* Returns 0 on success, errno on failure.
|
|
*/
|
|
int pasemi_dma_init(void)
|
|
{
|
|
static DEFINE_SPINLOCK(init_lock);
|
|
struct pci_dev *iob_pdev;
|
|
struct pci_dev *pdev;
|
|
struct resource res;
|
|
struct device_node *dn;
|
|
int i, intf, err = 0;
|
|
unsigned long timeout;
|
|
u32 tmp;
|
|
|
|
if (!machine_is(pasemi))
|
|
return -ENODEV;
|
|
|
|
spin_lock(&init_lock);
|
|
|
|
/* Make sure we haven't already initialized */
|
|
if (dma_pdev)
|
|
goto out;
|
|
|
|
iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
|
|
if (!iob_pdev) {
|
|
BUG();
|
|
printk(KERN_WARNING "Can't find I/O Bridge\n");
|
|
err = -ENODEV;
|
|
goto out;
|
|
}
|
|
iob_regs = map_onedev(iob_pdev, 0);
|
|
|
|
dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
|
|
if (!dma_pdev) {
|
|
BUG();
|
|
printk(KERN_WARNING "Can't find DMA controller\n");
|
|
err = -ENODEV;
|
|
goto out;
|
|
}
|
|
dma_regs = map_onedev(dma_pdev, 0);
|
|
base_hw_irq = virq_to_hw(dma_pdev->irq);
|
|
|
|
pci_read_config_dword(dma_pdev, PAS_DMA_CAP_TXCH, &tmp);
|
|
num_txch = (tmp & PAS_DMA_CAP_TXCH_TCHN_M) >> PAS_DMA_CAP_TXCH_TCHN_S;
|
|
|
|
pci_read_config_dword(dma_pdev, PAS_DMA_CAP_RXCH, &tmp);
|
|
num_rxch = (tmp & PAS_DMA_CAP_RXCH_RCHN_M) >> PAS_DMA_CAP_RXCH_RCHN_S;
|
|
|
|
intf = 0;
|
|
for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, NULL);
|
|
pdev;
|
|
pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, pdev))
|
|
mac_regs[intf++] = map_onedev(pdev, 0);
|
|
|
|
pci_dev_put(pdev);
|
|
|
|
for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, NULL);
|
|
pdev;
|
|
pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, pdev))
|
|
mac_regs[intf++] = map_onedev(pdev, 0);
|
|
|
|
pci_dev_put(pdev);
|
|
|
|
dn = pci_device_to_OF_node(iob_pdev);
|
|
if (dn)
|
|
err = of_address_to_resource(dn, 1, &res);
|
|
if (!dn || err) {
|
|
/* Fallback for old firmware */
|
|
res.start = 0xfd800000;
|
|
res.end = res.start + 0x1000;
|
|
}
|
|
dma_status = __ioremap(res.start, res.end-res.start, 0);
|
|
pci_dev_put(iob_pdev);
|
|
|
|
for (i = 0; i < MAX_TXCH; i++)
|
|
__set_bit(i, txch_free);
|
|
|
|
for (i = 0; i < MAX_RXCH; i++)
|
|
__set_bit(i, rxch_free);
|
|
|
|
timeout = jiffies + HZ;
|
|
pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0);
|
|
while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) {
|
|
if (time_after(jiffies, timeout)) {
|
|
pr_warning("Warning: Could not disable RX section\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
timeout = jiffies + HZ;
|
|
pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0);
|
|
while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) {
|
|
if (time_after(jiffies, timeout)) {
|
|
pr_warning("Warning: Could not disable TX section\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* setup resource allocations for the different DMA sections */
|
|
tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG);
|
|
pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000);
|
|
|
|
/* enable tx section */
|
|
pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
|
|
|
|
/* enable rx section */
|
|
pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
|
|
|
|
for (i = 0; i < MAX_FLAGS; i++)
|
|
__set_bit(i, flags_free);
|
|
|
|
for (i = 0; i < MAX_FUN; i++)
|
|
__set_bit(i, fun_free);
|
|
|
|
/* clear all status flags */
|
|
pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 0xffffffff);
|
|
pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 0xffffffff);
|
|
|
|
printk(KERN_INFO "PA Semi PWRficient DMA library initialized "
|
|
"(%d tx, %d rx channels)\n", num_txch, num_rxch);
|
|
|
|
out:
|
|
spin_unlock(&init_lock);
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(pasemi_dma_init);
|