![Albert Herranz](/assets/img/avatar_default.png)
Fix the following build failures: arch/powerpc/platforms/embedded6xx/flipper-pic.c: In function 'flipper_pic_map': arch/powerpc/platforms/embedded6xx/flipper-pic.c:105: error: implicit declaration of function 'get_irq_desc' arch/powerpc/platforms/embedded6xx/hlwd-pic.c: In function 'hlwd_pic_map': arch/powerpc/platforms/embedded6xx/hlwd-pic.c:98: error: implicit declaration of function 'get_irq_desc' These failures are caused by the changes introduced in commit "powerpc: Remove get_irq_desc()". The reason these drivers were not updated is that they weren't merged yet. Signed-off-by: Albert Herranz <albert_herranz@yahoo.es> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
242 lines
5.2 KiB
C
242 lines
5.2 KiB
C
/*
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* arch/powerpc/platforms/embedded6xx/hlwd-pic.c
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*
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* Nintendo Wii "Hollywood" interrupt controller support.
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* Copyright (C) 2009 The GameCube Linux Team
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* Copyright (C) 2009 Albert Herranz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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*/
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#define DRV_MODULE_NAME "hlwd-pic"
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#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include "hlwd-pic.h"
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#define HLWD_NR_IRQS 32
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/*
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* Each interrupt has a corresponding bit in both
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* the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
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*
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* Enabling/disabling an interrupt line involves asserting/clearing
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* the corresponding bit in IMR. ACK'ing a request simply involves
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* asserting the corresponding bit in ICR.
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*/
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#define HW_BROADWAY_ICR 0x00
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#define HW_BROADWAY_IMR 0x04
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/*
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* IRQ chip hooks.
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*
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*/
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static void hlwd_pic_mask_and_ack(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void __iomem *io_base = get_irq_chip_data(virq);
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u32 mask = 1 << irq;
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clrbits32(io_base + HW_BROADWAY_IMR, mask);
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out_be32(io_base + HW_BROADWAY_ICR, mask);
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}
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static void hlwd_pic_ack(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void __iomem *io_base = get_irq_chip_data(virq);
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out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
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}
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static void hlwd_pic_mask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void __iomem *io_base = get_irq_chip_data(virq);
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clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
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}
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static void hlwd_pic_unmask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void __iomem *io_base = get_irq_chip_data(virq);
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setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
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}
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static struct irq_chip hlwd_pic = {
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.name = "hlwd-pic",
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.ack = hlwd_pic_ack,
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.mask_ack = hlwd_pic_mask_and_ack,
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.mask = hlwd_pic_mask,
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.unmask = hlwd_pic_unmask,
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};
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/*
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* IRQ host hooks.
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*
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*/
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static struct irq_host *hlwd_irq_host;
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static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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set_irq_chip_data(virq, h->host_data);
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irq_to_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
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return 0;
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}
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static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq)
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{
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set_irq_chip_data(irq, NULL);
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set_irq_chip(irq, NULL);
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}
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static struct irq_host_ops hlwd_irq_host_ops = {
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.map = hlwd_pic_map,
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.unmap = hlwd_pic_unmap,
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};
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static unsigned int __hlwd_pic_get_irq(struct irq_host *h)
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{
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void __iomem *io_base = h->host_data;
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int irq;
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u32 irq_status;
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irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
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in_be32(io_base + HW_BROADWAY_IMR);
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if (irq_status == 0)
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return NO_IRQ; /* no more IRQs pending */
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irq = __ffs(irq_status);
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return irq_linear_revmap(h, irq);
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}
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static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
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struct irq_desc *desc)
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{
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struct irq_host *irq_host = get_irq_data(cascade_virq);
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unsigned int virq;
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raw_spin_lock(&desc->lock);
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desc->chip->mask(cascade_virq); /* IRQ_LEVEL */
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raw_spin_unlock(&desc->lock);
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virq = __hlwd_pic_get_irq(irq_host);
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if (virq != NO_IRQ)
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generic_handle_irq(virq);
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else
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pr_err("spurious interrupt!\n");
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raw_spin_lock(&desc->lock);
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desc->chip->ack(cascade_virq); /* IRQ_LEVEL */
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if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
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desc->chip->unmask(cascade_virq);
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raw_spin_unlock(&desc->lock);
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}
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/*
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* Platform hooks.
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*
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*/
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static void __hlwd_quiesce(void __iomem *io_base)
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{
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/* mask and ack all IRQs */
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out_be32(io_base + HW_BROADWAY_IMR, 0);
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out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
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}
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struct irq_host *hlwd_pic_init(struct device_node *np)
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{
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struct irq_host *irq_host;
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struct resource res;
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void __iomem *io_base;
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int retval;
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retval = of_address_to_resource(np, 0, &res);
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if (retval) {
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pr_err("no io memory range found\n");
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return NULL;
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}
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io_base = ioremap(res.start, resource_size(&res));
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if (!io_base) {
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pr_err("ioremap failed\n");
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return NULL;
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}
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pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
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__hlwd_quiesce(io_base);
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irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, HLWD_NR_IRQS,
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&hlwd_irq_host_ops, -1);
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if (!irq_host) {
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pr_err("failed to allocate irq_host\n");
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return NULL;
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}
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irq_host->host_data = io_base;
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return irq_host;
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}
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unsigned int hlwd_pic_get_irq(void)
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{
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return __hlwd_pic_get_irq(hlwd_irq_host);
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}
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/*
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* Probe function.
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*
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*/
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void hlwd_pic_probe(void)
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{
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struct irq_host *host;
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struct device_node *np;
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const u32 *interrupts;
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int cascade_virq;
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for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
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interrupts = of_get_property(np, "interrupts", NULL);
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if (interrupts) {
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host = hlwd_pic_init(np);
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BUG_ON(!host);
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cascade_virq = irq_of_parse_and_map(np, 0);
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set_irq_data(cascade_virq, host);
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set_irq_chained_handler(cascade_virq,
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hlwd_pic_irq_cascade);
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hlwd_irq_host = host;
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break;
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}
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}
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}
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/**
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* hlwd_quiesce() - quiesce hollywood irq controller
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*
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* Mask and ack all interrupt sources.
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*
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*/
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void hlwd_quiesce(void)
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{
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void __iomem *io_base = hlwd_irq_host->host_data;
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__hlwd_quiesce(io_base);
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}
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