![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
507 lines
12 KiB
C
507 lines
12 KiB
C
/*
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* Copyright 2007, Michael Ellerman, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/of_platform.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include <asm/dcr.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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/*
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* MSIC registers, specified as offsets from dcr_base
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*/
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#define MSIC_CTRL_REG 0x0
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/* Base Address registers specify FIFO location in BE memory */
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#define MSIC_BASE_ADDR_HI_REG 0x3
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#define MSIC_BASE_ADDR_LO_REG 0x4
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/* Hold the read/write offsets into the FIFO */
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#define MSIC_READ_OFFSET_REG 0x5
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#define MSIC_WRITE_OFFSET_REG 0x6
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/* MSIC control register flags */
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#define MSIC_CTRL_ENABLE 0x0001
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#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
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#define MSIC_CTRL_IRQ_ENABLE 0x0008
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#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
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/*
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* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
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* Currently we're using a 64KB FIFO size.
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*/
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#define MSIC_FIFO_SIZE_SHIFT 16
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#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
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/*
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* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
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* 8-9 of the MSIC control reg.
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*/
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#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
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/*
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* We need to mask the read/write offsets to make sure they stay within
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* the bounds of the FIFO. Also they should always be 16-byte aligned.
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*/
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#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
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/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
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#define MSIC_FIFO_ENTRY_SIZE 0x10
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struct axon_msic {
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struct irq_host *irq_host;
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__le32 *fifo_virt;
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dma_addr_t fifo_phys;
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dcr_host_t dcr_host;
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u32 read_offset;
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#ifdef DEBUG
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u32 __iomem *trigger;
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#endif
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};
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#ifdef DEBUG
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void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
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#else
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static inline void axon_msi_debug_setup(struct device_node *dn,
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struct axon_msic *msic) { }
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#endif
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static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
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{
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pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
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dcr_write(msic->dcr_host, dcr_n, val);
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}
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static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct axon_msic *msic = get_irq_data(irq);
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u32 write_offset, msi;
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int idx;
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int retry = 0;
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write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
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pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
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/* write_offset doesn't wrap properly, so we have to mask it */
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write_offset &= MSIC_FIFO_SIZE_MASK;
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while (msic->read_offset != write_offset && retry < 100) {
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idx = msic->read_offset / sizeof(__le32);
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msi = le32_to_cpu(msic->fifo_virt[idx]);
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msi &= 0xFFFF;
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pr_devel("axon_msi: woff %x roff %x msi %x\n",
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write_offset, msic->read_offset, msi);
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if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
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generic_handle_irq(msi);
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msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
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} else {
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/*
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* Reading the MSIC_WRITE_OFFSET_REG does not
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* reliably flush the outstanding DMA to the
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* FIFO buffer. Here we were reading stale
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* data, so we need to retry.
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*/
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udelay(1);
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retry++;
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pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
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continue;
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}
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if (retry) {
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pr_devel("axon_msi: late irq 0x%x, retry %d\n",
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msi, retry);
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retry = 0;
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}
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msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
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msic->read_offset &= MSIC_FIFO_SIZE_MASK;
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}
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if (retry) {
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printk(KERN_WARNING "axon_msi: irq timed out\n");
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msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
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msic->read_offset &= MSIC_FIFO_SIZE_MASK;
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}
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desc->chip->eoi(irq);
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}
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static struct axon_msic *find_msi_translator(struct pci_dev *dev)
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{
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struct irq_host *irq_host;
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struct device_node *dn, *tmp;
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const phandle *ph;
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struct axon_msic *msic = NULL;
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dn = of_node_get(pci_device_to_OF_node(dev));
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if (!dn) {
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dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
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return NULL;
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}
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for (; dn; dn = of_get_next_parent(dn)) {
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ph = of_get_property(dn, "msi-translator", NULL);
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if (ph)
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break;
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}
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if (!ph) {
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dev_dbg(&dev->dev,
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"axon_msi: no msi-translator property found\n");
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goto out_error;
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}
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tmp = dn;
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dn = of_find_node_by_phandle(*ph);
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of_node_put(tmp);
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if (!dn) {
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dev_dbg(&dev->dev,
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"axon_msi: msi-translator doesn't point to a node\n");
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goto out_error;
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}
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irq_host = irq_find_host(dn);
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if (!irq_host) {
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dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
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dn->full_name);
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goto out_error;
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}
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msic = irq_host->host_data;
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out_error:
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of_node_put(dn);
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return msic;
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}
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static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
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{
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if (!find_msi_translator(dev))
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return -ENODEV;
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return 0;
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}
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static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
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{
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struct device_node *dn;
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struct msi_desc *entry;
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int len;
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const u32 *prop;
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dn = of_node_get(pci_device_to_OF_node(dev));
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if (!dn) {
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dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
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return -ENODEV;
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}
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entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
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for (; dn; dn = of_get_next_parent(dn)) {
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if (entry->msi_attrib.is_64) {
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prop = of_get_property(dn, "msi-address-64", &len);
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if (prop)
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break;
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}
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prop = of_get_property(dn, "msi-address-32", &len);
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if (prop)
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break;
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}
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if (!prop) {
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dev_dbg(&dev->dev,
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"axon_msi: no msi-address-(32|64) properties found\n");
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return -ENOENT;
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}
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switch (len) {
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case 8:
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msg->address_hi = prop[0];
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msg->address_lo = prop[1];
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break;
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case 4:
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msg->address_hi = 0;
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msg->address_lo = prop[0];
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break;
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default:
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dev_dbg(&dev->dev,
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"axon_msi: malformed msi-address-(32|64) property\n");
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of_node_put(dn);
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return -EINVAL;
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}
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of_node_put(dn);
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return 0;
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}
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static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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unsigned int virq, rc;
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struct msi_desc *entry;
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struct msi_msg msg;
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struct axon_msic *msic;
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msic = find_msi_translator(dev);
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if (!msic)
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return -ENODEV;
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rc = setup_msi_msg_address(dev, &msg);
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if (rc)
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return rc;
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/* We rely on being able to stash a virq in a u16 */
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BUILD_BUG_ON(NR_IRQS > 65536);
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list_for_each_entry(entry, &dev->msi_list, list) {
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virq = irq_create_direct_mapping(msic->irq_host);
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if (virq == NO_IRQ) {
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dev_warn(&dev->dev,
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"axon_msi: virq allocation failed!\n");
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return -1;
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}
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dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
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set_irq_msi(virq, entry);
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msg.data = virq;
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write_msi_msg(virq, &msg);
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}
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return 0;
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}
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static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
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list_for_each_entry(entry, &dev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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set_irq_msi(entry->irq, NULL);
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irq_dispose_mapping(entry->irq);
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}
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}
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static struct irq_chip msic_irq_chip = {
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.mask = mask_msi_irq,
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.unmask = unmask_msi_irq,
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.shutdown = unmask_msi_irq,
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.name = "AXON-MSI",
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};
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static int msic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
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return 0;
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}
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static struct irq_host_ops msic_host_ops = {
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.map = msic_host_map,
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};
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static int axon_msi_shutdown(struct of_device *device)
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{
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struct axon_msic *msic = dev_get_drvdata(&device->dev);
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u32 tmp;
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pr_devel("axon_msi: disabling %s\n",
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msic->irq_host->of_node->full_name);
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tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
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tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
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msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
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return 0;
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}
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static int axon_msi_probe(struct of_device *device,
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const struct of_device_id *device_id)
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{
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struct device_node *dn = device->node;
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struct axon_msic *msic;
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unsigned int virq;
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int dcr_base, dcr_len;
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pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
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msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
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if (!msic) {
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printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
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dn->full_name);
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goto out;
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}
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dcr_base = dcr_resource_start(dn, 0);
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dcr_len = dcr_resource_len(dn, 0);
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if (dcr_base == 0 || dcr_len == 0) {
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printk(KERN_ERR
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"axon_msi: couldn't parse dcr properties on %s\n",
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dn->full_name);
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goto out_free_msic;
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}
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msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
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if (!DCR_MAP_OK(msic->dcr_host)) {
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printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
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dn->full_name);
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goto out_free_msic;
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}
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msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
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&msic->fifo_phys, GFP_KERNEL);
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if (!msic->fifo_virt) {
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printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
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dn->full_name);
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goto out_free_msic;
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}
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virq = irq_of_parse_and_map(dn, 0);
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if (virq == NO_IRQ) {
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printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
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dn->full_name);
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goto out_free_fifo;
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}
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memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
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msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
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NR_IRQS, &msic_host_ops, 0);
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if (!msic->irq_host) {
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printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
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dn->full_name);
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goto out_free_fifo;
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}
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msic->irq_host->host_data = msic;
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set_irq_data(virq, msic);
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set_irq_chained_handler(virq, axon_msi_cascade);
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pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
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/* Enable the MSIC hardware */
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msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
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msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
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msic->fifo_phys & 0xFFFFFFFF);
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msic_dcr_write(msic, MSIC_CTRL_REG,
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MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
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MSIC_CTRL_FIFO_SIZE);
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msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
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& MSIC_FIFO_SIZE_MASK;
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dev_set_drvdata(&device->dev, msic);
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ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
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ppc_md.msi_check_device = axon_msi_check_device;
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axon_msi_debug_setup(dn, msic);
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printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
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return 0;
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out_free_fifo:
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dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
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msic->fifo_phys);
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out_free_msic:
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kfree(msic);
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out:
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return -1;
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}
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static const struct of_device_id axon_msi_device_id[] = {
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{
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.compatible = "ibm,axon-msic"
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},
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{}
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};
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static struct of_platform_driver axon_msi_driver = {
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.match_table = axon_msi_device_id,
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.probe = axon_msi_probe,
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|
.shutdown = axon_msi_shutdown,
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|
.driver = {
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|
.name = "axon-msi"
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|
},
|
|
};
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|
|
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static int __init axon_msi_init(void)
|
|
{
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|
return of_register_platform_driver(&axon_msi_driver);
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|
}
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subsys_initcall(axon_msi_init);
|
|
|
|
|
|
#ifdef DEBUG
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static int msic_set(void *data, u64 val)
|
|
{
|
|
struct axon_msic *msic = data;
|
|
out_le32(msic->trigger, val);
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|
return 0;
|
|
}
|
|
|
|
static int msic_get(void *data, u64 *val)
|
|
{
|
|
*val = 0;
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
|
|
|
|
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
|
|
{
|
|
char name[8];
|
|
u64 addr;
|
|
|
|
addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
|
|
if (addr == OF_BAD_ADDR) {
|
|
pr_devel("axon_msi: couldn't translate reg property\n");
|
|
return;
|
|
}
|
|
|
|
msic->trigger = ioremap(addr, 0x4);
|
|
if (!msic->trigger) {
|
|
pr_devel("axon_msi: ioremap failed\n");
|
|
return;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
|
|
|
|
if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
|
|
msic, &fops_msic)) {
|
|
pr_devel("axon_msi: debugfs_create_file failed!\n");
|
|
return;
|
|
}
|
|
}
|
|
#endif /* DEBUG */
|