b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
233 lines
5.5 KiB
Text
233 lines
5.5 KiB
Text
/*
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* MPC8572 DS Core1 Device Tree Source in CAMP mode.
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*
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* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
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* can be shared, all the other devices must be assigned to one core only.
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* This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
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*
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* Please note to add "-b 1" for core1's dts compiling.
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*
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8572@1 {
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device_type = "cpu";
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reg = <0x1>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>; // Filled by U-Boot
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};
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soc8572@ffe00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xffe00000 0x100000>;
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bus-frequency = <0>; // Filled out by uboot.
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8572-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
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reg = <0xc300 0x4>;
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ranges = <0x0 0xc100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <76 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <77 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <78 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <79 2>;
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};
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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reg = <0x2>;
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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reg = <0x3>;
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};
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};
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enet2: ethernet@26000 {
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cell-index = <2>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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phy-connection-type = "rgmii-id";
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};
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enet3: ethernet@27000 {
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cell-index = <3>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x27000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <37 2 38 2 39 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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};
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msi@41600 {
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compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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serial0: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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protected-sources = <
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18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
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29 30 34 35 36 40 /* enet0 enet1 */
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24 25 20 21 22 23 /* pci0 pci1 dma1 */
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43 /* i2c */
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0x1 0x2 0x3 0x4 /* pci slot */
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0x9 0xa 0xb 0xc /* usb */
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0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
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>;
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};
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};
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pci2: pcie@ffe0a000 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xffe0a000 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1
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0000 0x0 0x0 0x2 &mpic 0x1 0x1
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0000 0x0 0x0 0x3 &mpic 0x2 0x1
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0000 0x0 0x0 0x4 &mpic 0x3 0x1
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>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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