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linux-2.6/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
Kumar Gala b1b6802586 powerpc/fsl: Removed reg property from 85xx/86xx soc node 
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level.  It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-19 00:50:29 -05:00

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/*
* MPC8572 DS Core0 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
* eth1, crypto, pci0, pci1.
*
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>; // Filled by U-Boot
};
soc8572@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x1>;
};
};
};
enet1: ethernet@25000 {
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
protected-sources = <
31 32 33 37 38 39 /* enet2 enet3 */
76 77 78 79 26 42 /* dma2 pci2 serial*/
0xe0 0xe1 0xe2 0xe3 /* msi */
0xe4 0xe5 0xe6 0xe7
>;
};
};
pci0: pcie@ffe08000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xffe08000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 1 - PCI slot 1 */
0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 2 - PCI slot 1 */
0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 3 - PCI slot 1 */
0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 4 - PCI slot 1 */
0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 5 - PCI slot 1 */
0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 6 - PCI slot 1 */
0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 7 - PCI slot 1 */
0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 func 0 - PCI slot 2 */
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 1 - PCI slot 2 */
0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 2 - PCI slot 2 */
0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 3 - PCI slot 2 */
0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 4 - PCI slot 2 */
0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 5 - PCI slot 2 */
0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 6 - PCI slot 2 */
0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 7 - PCI slot 2 */
0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
// IDSEL 0x1c USB
0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
uli1575@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0
0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
interrupts = <1 3 12 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0x0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <0x1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <0x1 0x70 0x2>;
};
gpio@400 {
reg = <0x1 0x400 0x80>;
};
};
};
};
};
pci1: pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xffe09000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
};
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