b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
395 lines
9.5 KiB
Text
395 lines
9.5 KiB
Text
/*
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* MPC8560 ADS Device Tree Source
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*
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* Copyright 2006, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "MPC8560ADS";
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compatible = "MPC8560ADS", "MPC85xxADS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8560@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <82500000>;
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bus-frequency = <330000000>;
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clock-frequency = <825000000>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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soc8560@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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bus-frequency = <330000000>;
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <8>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8560-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,8540-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,8540-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <7 1>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <7 1>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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cpm@919c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
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reg = <0x919c0 0x30>;
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ranges;
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muram@80000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000 0x10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0x0 0x4000 0x9000 0x2000>;
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};
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};
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brg@919f0 {
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compatible = "fsl,mpc8560-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <0x919f0 0x10 0x915f0 0x10>;
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clock-frequency = <165000000>;
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};
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cpmpic: pic@90c00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <46 2>;
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interrupt-parent = <&mpic>;
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reg = <0x90c00 0x80>;
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compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
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};
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serial0: serial@91a00 {
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device_type = "serial";
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compatible = "fsl,mpc8560-scc-uart",
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"fsl,cpm2-scc-uart";
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reg = <0x91a00 0x20 0x88000 0x100>;
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fsl,cpm-brg = <1>;
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fsl,cpm-command = <0x800000>;
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current-speed = <115200>;
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interrupts = <40 8>;
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interrupt-parent = <&cpmpic>;
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};
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serial1: serial@91a20 {
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device_type = "serial";
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compatible = "fsl,mpc8560-scc-uart",
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"fsl,cpm2-scc-uart";
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reg = <0x91a20 0x20 0x88100 0x100>;
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fsl,cpm-brg = <2>;
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fsl,cpm-command = <0x4a00000>;
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current-speed = <115200>;
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interrupts = <41 8>;
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interrupt-parent = <&cpmpic>;
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};
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enet2: ethernet@91320 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x16200300>;
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interrupts = <33 8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy2>;
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};
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enet3: ethernet@91340 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x1a400300>;
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interrupts = <34 8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy3>;
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};
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};
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};
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pci0: pci@e0008000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xe0008000 0x1000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x2 */
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0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x3 */
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0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x4 */
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0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
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0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
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0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
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0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x5 */
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0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 12 */
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0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 13 */
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0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 14*/
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0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
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0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
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0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
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0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 15 */
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0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 18 */
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0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 19 */
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0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 20 */
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0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
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0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
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0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
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0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 21 */
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0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
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0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
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0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
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0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
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};
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};
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