![Stefan Roese](/assets/img/avatar_default.png)
This patch implements supports for EHCI controllers whose in-memory data structures are represented in big-endian format. This is needed (unfortunately) for the AMCC PPC440EPx SoC EHCI controller; the EHCI spec doesn't specify little-endian format, although that's what most other implementations use. The guts of the patch are to introduce the hc32 type and change all references from le32 to hc32. All access routines are converted from cpu_to_le32(...) to cpu_to_hc32(ehci, ...) and similar for the other "direction". (This is the same approach used with OHCI.) David fixed: Whitespace fixes; refresh against ehci cpufreq patch; move glue for that PPC driver to the patch adding it; fix free symbol capture bugs in modified "constant" macros; and make "hc32" etc be "le32" unless we really need the BE options, so "sparse" can do some real good. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
1123 lines
31 KiB
C
1123 lines
31 KiB
C
/*
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* Copyright (C) 2001-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* this file is part of ehci-hcd.c */
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI hardware queue manipulation ... the core. QH/QTD manipulation.
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*
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* Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd"
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* entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
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* buffers needed for the larger number). We use one QH per endpoint, queue
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* multiple urbs (all three types) per endpoint. URBs may need several qtds.
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*
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* ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with
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* interrupts) needs careful scheduling. Performance improvements can be
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* an ongoing challenge. That's in "ehci-sched.c".
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*
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* USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
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* or otherwise through transaction translators (TTs) in USB 2.0 hubs using
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* (b) special fields in qh entries or (c) split iso entries. TTs will
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* buffer low/full speed data so the host collects it at high speed.
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*/
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/*-------------------------------------------------------------------------*/
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/* fill a qtd, returning how much of the buffer we were able to queue up */
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static int
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qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf,
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size_t len, int token, int maxpacket)
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{
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int i, count;
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u64 addr = buf;
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/* one buffer entry per 4K ... first might be short or unaligned */
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qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32)addr);
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qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32)(addr >> 32));
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count = 0x1000 - (buf & 0x0fff); /* rest of that page */
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if (likely (len < count)) /* ... iff needed */
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count = len;
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else {
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buf += 0x1000;
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buf &= ~0x0fff;
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/* per-qtd limit: from 16K to 20K (best alignment) */
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for (i = 1; count < len && i < 5; i++) {
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addr = buf;
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qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32)addr);
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qtd->hw_buf_hi[i] = cpu_to_hc32(ehci,
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(u32)(addr >> 32));
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buf += 0x1000;
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if ((count + 0x1000) < len)
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count += 0x1000;
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else
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count = len;
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}
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/* short packets may only terminate transfers */
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if (count != len)
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count -= (count % maxpacket);
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}
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qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token);
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qtd->length = count;
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return count;
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}
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/*-------------------------------------------------------------------------*/
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static inline void
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qh_update (struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd)
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{
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/* writes to an active overlay are unsafe */
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BUG_ON(qh->qh_state != QH_STATE_IDLE);
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qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma);
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qh->hw_alt_next = EHCI_LIST_END(ehci);
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/* Except for control endpoints, we make hardware maintain data
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* toggle (like OHCI) ... here (re)initialize the toggle in the QH,
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* and set the pseudo-toggle in udev. Only usb_clear_halt() will
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* ever clear it.
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*/
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if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) {
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unsigned is_out, epnum;
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is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8));
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epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f;
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if (unlikely (!usb_gettoggle (qh->dev, epnum, is_out))) {
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qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE);
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usb_settoggle (qh->dev, epnum, is_out, 1);
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}
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}
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/* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
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wmb ();
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qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING);
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}
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/* if it weren't for a common silicon quirk (writing the dummy into the qh
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* overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
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* recovery (including urb dequeue) would need software changes to a QH...
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*/
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static void
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qh_refresh (struct ehci_hcd *ehci, struct ehci_qh *qh)
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{
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struct ehci_qtd *qtd;
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if (list_empty (&qh->qtd_list))
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qtd = qh->dummy;
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else {
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qtd = list_entry (qh->qtd_list.next,
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struct ehci_qtd, qtd_list);
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/* first qtd may already be partially processed */
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if (cpu_to_hc32(ehci, qtd->qtd_dma) == qh->hw_current)
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qtd = NULL;
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}
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if (qtd)
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qh_update (ehci, qh, qtd);
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}
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/*-------------------------------------------------------------------------*/
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static void qtd_copy_status (
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struct ehci_hcd *ehci,
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struct urb *urb,
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size_t length,
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u32 token
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)
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{
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/* count IN/OUT bytes, not SETUP (even short packets) */
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if (likely (QTD_PID (token) != 2))
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urb->actual_length += length - QTD_LENGTH (token);
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/* don't modify error codes */
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if (unlikely (urb->status != -EINPROGRESS))
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return;
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/* force cleanup after short read; not always an error */
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if (unlikely (IS_SHORT_READ (token)))
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urb->status = -EREMOTEIO;
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/* serious "can't proceed" faults reported by the hardware */
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if (token & QTD_STS_HALT) {
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if (token & QTD_STS_BABBLE) {
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/* FIXME "must" disable babbling device's port too */
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urb->status = -EOVERFLOW;
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} else if (token & QTD_STS_MMF) {
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/* fs/ls interrupt xfer missed the complete-split */
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urb->status = -EPROTO;
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} else if (token & QTD_STS_DBE) {
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urb->status = (QTD_PID (token) == 1) /* IN ? */
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? -ENOSR /* hc couldn't read data */
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: -ECOMM; /* hc couldn't write data */
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} else if (token & QTD_STS_XACT) {
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/* timeout, bad crc, wrong PID, etc; retried */
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if (QTD_CERR (token))
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urb->status = -EPIPE;
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else {
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ehci_dbg (ehci, "devpath %s ep%d%s 3strikes\n",
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urb->dev->devpath,
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usb_pipeendpoint (urb->pipe),
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usb_pipein (urb->pipe) ? "in" : "out");
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urb->status = -EPROTO;
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}
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/* CERR nonzero + no errors + halt --> stall */
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} else if (QTD_CERR (token))
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urb->status = -EPIPE;
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else /* unknown */
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urb->status = -EPROTO;
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ehci_vdbg (ehci,
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"dev%d ep%d%s qtd token %08x --> status %d\n",
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usb_pipedevice (urb->pipe),
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usb_pipeendpoint (urb->pipe),
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usb_pipein (urb->pipe) ? "in" : "out",
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token, urb->status);
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/* if async CSPLIT failed, try cleaning out the TT buffer */
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if (urb->status != -EPIPE
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&& urb->dev->tt && !usb_pipeint (urb->pipe)
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&& ((token & QTD_STS_MMF) != 0
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|| QTD_CERR(token) == 0)
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&& (!ehci_is_TDI(ehci)
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|| urb->dev->tt->hub !=
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ehci_to_hcd(ehci)->self.root_hub)) {
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#ifdef DEBUG
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struct usb_device *tt = urb->dev->tt->hub;
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dev_dbg (&tt->dev,
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"clear tt buffer port %d, a%d ep%d t%08x\n",
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urb->dev->ttport, urb->dev->devnum,
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usb_pipeendpoint (urb->pipe), token);
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#endif /* DEBUG */
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usb_hub_tt_clear_buffer (urb->dev, urb->pipe);
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}
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}
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}
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static void
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ehci_urb_done (struct ehci_hcd *ehci, struct urb *urb)
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__releases(ehci->lock)
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__acquires(ehci->lock)
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{
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if (likely (urb->hcpriv != NULL)) {
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struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv;
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/* S-mask in a QH means it's an interrupt urb */
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if ((qh->hw_info2 & cpu_to_hc32(ehci, QH_SMASK)) != 0) {
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/* ... update hc-wide periodic stats (for usbfs) */
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ehci_to_hcd(ehci)->self.bandwidth_int_reqs--;
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}
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qh_put (qh);
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}
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spin_lock (&urb->lock);
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urb->hcpriv = NULL;
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switch (urb->status) {
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case -EINPROGRESS: /* success */
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urb->status = 0;
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default: /* fault */
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COUNT (ehci->stats.complete);
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break;
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case -EREMOTEIO: /* fault or normal */
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if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
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urb->status = 0;
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COUNT (ehci->stats.complete);
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break;
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case -ECONNRESET: /* canceled */
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case -ENOENT:
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COUNT (ehci->stats.unlink);
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break;
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}
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spin_unlock (&urb->lock);
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#ifdef EHCI_URB_TRACE
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ehci_dbg (ehci,
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"%s %s urb %p ep%d%s status %d len %d/%d\n",
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__FUNCTION__, urb->dev->devpath, urb,
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usb_pipeendpoint (urb->pipe),
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usb_pipein (urb->pipe) ? "in" : "out",
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urb->status,
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urb->actual_length, urb->transfer_buffer_length);
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#endif
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/* complete() can reenter this HCD */
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spin_unlock (&ehci->lock);
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usb_hcd_giveback_urb (ehci_to_hcd(ehci), urb);
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spin_lock (&ehci->lock);
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}
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static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh);
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static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh);
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static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh);
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static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh);
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/*
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* Process and free completed qtds for a qh, returning URBs to drivers.
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* Chases up to qh->hw_current. Returns number of completions called,
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* indicating how much "real" work we did.
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*/
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static unsigned
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qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh)
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{
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struct ehci_qtd *last = NULL, *end = qh->dummy;
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struct list_head *entry, *tmp;
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int stopped;
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unsigned count = 0;
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int do_status = 0;
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u8 state;
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u32 halt = HALT_BIT(ehci);
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if (unlikely (list_empty (&qh->qtd_list)))
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return count;
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/* completions (or tasks on other cpus) must never clobber HALT
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* till we've gone through and cleaned everything up, even when
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* they add urbs to this qh's queue or mark them for unlinking.
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*
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* NOTE: unlinking expects to be done in queue order.
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*/
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state = qh->qh_state;
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qh->qh_state = QH_STATE_COMPLETING;
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stopped = (state == QH_STATE_IDLE);
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/* remove de-activated QTDs from front of queue.
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* after faults (including short reads), cleanup this urb
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* then let the queue advance.
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* if queue is stopped, handles unlinks.
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*/
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list_for_each_safe (entry, tmp, &qh->qtd_list) {
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struct ehci_qtd *qtd;
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struct urb *urb;
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u32 token = 0;
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/* ignore QHs that are currently inactive */
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if (qh->hw_info1 & __constant_cpu_to_le32(QH_INACTIVATE))
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break;
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qtd = list_entry (entry, struct ehci_qtd, qtd_list);
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urb = qtd->urb;
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/* clean up any state from previous QTD ...*/
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if (last) {
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if (likely (last->urb != urb)) {
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ehci_urb_done (ehci, last->urb);
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count++;
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}
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ehci_qtd_free (ehci, last);
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last = NULL;
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}
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/* ignore urbs submitted during completions we reported */
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if (qtd == end)
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break;
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/* hardware copies qtd out of qh overlay */
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rmb ();
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token = hc32_to_cpu(ehci, qtd->hw_token);
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/* always clean up qtds the hc de-activated */
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if ((token & QTD_STS_ACTIVE) == 0) {
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if ((token & QTD_STS_HALT) != 0) {
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stopped = 1;
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/* magic dummy for some short reads; qh won't advance.
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* that silicon quirk can kick in with this dummy too.
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*/
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} else if (IS_SHORT_READ (token)
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&& !(qtd->hw_alt_next
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& EHCI_LIST_END(ehci))) {
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stopped = 1;
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goto halt;
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}
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/* stop scanning when we reach qtds the hc is using */
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} else if (likely (!stopped
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&& HC_IS_RUNNING (ehci_to_hcd(ehci)->state))) {
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break;
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} else {
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stopped = 1;
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if (unlikely (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)))
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urb->status = -ESHUTDOWN;
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/* ignore active urbs unless some previous qtd
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* for the urb faulted (including short read) or
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* its urb was canceled. we may patch qh or qtds.
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*/
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if (likely (urb->status == -EINPROGRESS))
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continue;
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/* issue status after short control reads */
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if (unlikely (do_status != 0)
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&& QTD_PID (token) == 0 /* OUT */) {
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do_status = 0;
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continue;
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}
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/* token in overlay may be most current */
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if (state == QH_STATE_IDLE
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&& cpu_to_hc32(ehci, qtd->qtd_dma)
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== qh->hw_current)
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token = hc32_to_cpu(ehci, qh->hw_token);
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/* force halt for unlinked or blocked qh, so we'll
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* patch the qh later and so that completions can't
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* activate it while we "know" it's stopped.
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*/
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if ((halt & qh->hw_token) == 0) {
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halt:
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qh->hw_token |= halt;
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wmb ();
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}
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}
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/* remove it from the queue */
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spin_lock (&urb->lock);
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qtd_copy_status (ehci, urb, qtd->length, token);
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do_status = (urb->status == -EREMOTEIO)
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&& usb_pipecontrol (urb->pipe);
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spin_unlock (&urb->lock);
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if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
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last = list_entry (qtd->qtd_list.prev,
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struct ehci_qtd, qtd_list);
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last->hw_next = qtd->hw_next;
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}
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list_del (&qtd->qtd_list);
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last = qtd;
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}
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/* last urb's completion might still need calling */
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if (likely (last != NULL)) {
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ehci_urb_done (ehci, last->urb);
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count++;
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ehci_qtd_free (ehci, last);
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}
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/* restore original state; caller must unlink or relink */
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qh->qh_state = state;
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/* be sure the hardware's done with the qh before refreshing
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* it after fault cleanup, or recovering from silicon wrongly
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* overlaying the dummy qtd (which reduces DMA chatter).
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*/
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if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END(ehci)) {
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switch (state) {
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case QH_STATE_IDLE:
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qh_refresh(ehci, qh);
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break;
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case QH_STATE_LINKED:
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/* should be rare for periodic transfers,
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* except maybe high bandwidth ...
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*/
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if ((cpu_to_hc32(ehci, QH_SMASK)
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& qh->hw_info2) != 0) {
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intr_deschedule (ehci, qh);
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(void) qh_schedule (ehci, qh);
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} else
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unlink_async (ehci, qh);
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break;
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/* otherwise, unlink already started */
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}
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}
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return count;
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}
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|
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/*-------------------------------------------------------------------------*/
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// high bandwidth multiplier, as encoded in highspeed endpoint descriptors
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#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
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// ... and packet size, for any kind of endpoint descriptor
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#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
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/*
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* reverse of qh_urb_transaction: free a list of TDs.
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* used for cleanup after errors, before HC sees an URB's TDs.
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*/
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static void qtd_list_free (
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|
struct ehci_hcd *ehci,
|
|
struct urb *urb,
|
|
struct list_head *qtd_list
|
|
) {
|
|
struct list_head *entry, *temp;
|
|
|
|
list_for_each_safe (entry, temp, qtd_list) {
|
|
struct ehci_qtd *qtd;
|
|
|
|
qtd = list_entry (entry, struct ehci_qtd, qtd_list);
|
|
list_del (&qtd->qtd_list);
|
|
ehci_qtd_free (ehci, qtd);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* create a list of filled qtds for this URB; won't link into qh.
|
|
*/
|
|
static struct list_head *
|
|
qh_urb_transaction (
|
|
struct ehci_hcd *ehci,
|
|
struct urb *urb,
|
|
struct list_head *head,
|
|
gfp_t flags
|
|
) {
|
|
struct ehci_qtd *qtd, *qtd_prev;
|
|
dma_addr_t buf;
|
|
int len, maxpacket;
|
|
int is_input;
|
|
u32 token;
|
|
|
|
/*
|
|
* URBs map to sequences of QTDs: one logical transaction
|
|
*/
|
|
qtd = ehci_qtd_alloc (ehci, flags);
|
|
if (unlikely (!qtd))
|
|
return NULL;
|
|
list_add_tail (&qtd->qtd_list, head);
|
|
qtd->urb = urb;
|
|
|
|
token = QTD_STS_ACTIVE;
|
|
token |= (EHCI_TUNE_CERR << 10);
|
|
/* for split transactions, SplitXState initialized to zero */
|
|
|
|
len = urb->transfer_buffer_length;
|
|
is_input = usb_pipein (urb->pipe);
|
|
if (usb_pipecontrol (urb->pipe)) {
|
|
/* SETUP pid */
|
|
qtd_fill(ehci, qtd, urb->setup_dma,
|
|
sizeof (struct usb_ctrlrequest),
|
|
token | (2 /* "setup" */ << 8), 8);
|
|
|
|
/* ... and always at least one more pid */
|
|
token ^= QTD_TOGGLE;
|
|
qtd_prev = qtd;
|
|
qtd = ehci_qtd_alloc (ehci, flags);
|
|
if (unlikely (!qtd))
|
|
goto cleanup;
|
|
qtd->urb = urb;
|
|
qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
|
|
list_add_tail (&qtd->qtd_list, head);
|
|
|
|
/* for zero length DATA stages, STATUS is always IN */
|
|
if (len == 0)
|
|
token |= (1 /* "in" */ << 8);
|
|
}
|
|
|
|
/*
|
|
* data transfer stage: buffer setup
|
|
*/
|
|
buf = urb->transfer_dma;
|
|
|
|
if (is_input)
|
|
token |= (1 /* "in" */ << 8);
|
|
/* else it's already initted to "out" pid (0 << 8) */
|
|
|
|
maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
|
|
|
|
/*
|
|
* buffer gets wrapped in one or more qtds;
|
|
* last one may be "short" (including zero len)
|
|
* and may serve as a control status ack
|
|
*/
|
|
for (;;) {
|
|
int this_qtd_len;
|
|
|
|
this_qtd_len = qtd_fill(ehci, qtd, buf, len, token, maxpacket);
|
|
len -= this_qtd_len;
|
|
buf += this_qtd_len;
|
|
if (is_input)
|
|
qtd->hw_alt_next = ehci->async->hw_alt_next;
|
|
|
|
/* qh makes control packets use qtd toggle; maybe switch it */
|
|
if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
|
|
token ^= QTD_TOGGLE;
|
|
|
|
if (likely (len <= 0))
|
|
break;
|
|
|
|
qtd_prev = qtd;
|
|
qtd = ehci_qtd_alloc (ehci, flags);
|
|
if (unlikely (!qtd))
|
|
goto cleanup;
|
|
qtd->urb = urb;
|
|
qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
|
|
list_add_tail (&qtd->qtd_list, head);
|
|
}
|
|
|
|
/* unless the bulk/interrupt caller wants a chance to clean
|
|
* up after short reads, hc should advance qh past this urb
|
|
*/
|
|
if (likely ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
|
|
|| usb_pipecontrol (urb->pipe)))
|
|
qtd->hw_alt_next = EHCI_LIST_END(ehci);
|
|
|
|
/*
|
|
* control requests may need a terminating data "status" ack;
|
|
* bulk ones may need a terminating short packet (zero length).
|
|
*/
|
|
if (likely (urb->transfer_buffer_length != 0)) {
|
|
int one_more = 0;
|
|
|
|
if (usb_pipecontrol (urb->pipe)) {
|
|
one_more = 1;
|
|
token ^= 0x0100; /* "in" <--> "out" */
|
|
token |= QTD_TOGGLE; /* force DATA1 */
|
|
} else if (usb_pipebulk (urb->pipe)
|
|
&& (urb->transfer_flags & URB_ZERO_PACKET)
|
|
&& !(urb->transfer_buffer_length % maxpacket)) {
|
|
one_more = 1;
|
|
}
|
|
if (one_more) {
|
|
qtd_prev = qtd;
|
|
qtd = ehci_qtd_alloc (ehci, flags);
|
|
if (unlikely (!qtd))
|
|
goto cleanup;
|
|
qtd->urb = urb;
|
|
qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
|
|
list_add_tail (&qtd->qtd_list, head);
|
|
|
|
/* never any data in such packets */
|
|
qtd_fill(ehci, qtd, 0, 0, token, 0);
|
|
}
|
|
}
|
|
|
|
/* by default, enable interrupt on urb completion */
|
|
if (likely (!(urb->transfer_flags & URB_NO_INTERRUPT)))
|
|
qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC);
|
|
return head;
|
|
|
|
cleanup:
|
|
qtd_list_free (ehci, urb, head);
|
|
return NULL;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
// Would be best to create all qh's from config descriptors,
|
|
// when each interface/altsetting is established. Unlink
|
|
// any previous qh and cancel its urbs first; endpoints are
|
|
// implicitly reset then (data toggle too).
|
|
// That'd mean updating how usbcore talks to HCDs. (2.7?)
|
|
|
|
|
|
/*
|
|
* Each QH holds a qtd list; a QH is used for everything except iso.
|
|
*
|
|
* For interrupt urbs, the scheduler must set the microframe scheduling
|
|
* mask(s) each time the QH gets scheduled. For highspeed, that's
|
|
* just one microframe in the s-mask. For split interrupt transactions
|
|
* there are additional complications: c-mask, maybe FSTNs.
|
|
*/
|
|
static struct ehci_qh *
|
|
qh_make (
|
|
struct ehci_hcd *ehci,
|
|
struct urb *urb,
|
|
gfp_t flags
|
|
) {
|
|
struct ehci_qh *qh = ehci_qh_alloc (ehci, flags);
|
|
u32 info1 = 0, info2 = 0;
|
|
int is_input, type;
|
|
int maxp = 0;
|
|
|
|
if (!qh)
|
|
return qh;
|
|
|
|
/*
|
|
* init endpoint/device data for this QH
|
|
*/
|
|
info1 |= usb_pipeendpoint (urb->pipe) << 8;
|
|
info1 |= usb_pipedevice (urb->pipe) << 0;
|
|
|
|
is_input = usb_pipein (urb->pipe);
|
|
type = usb_pipetype (urb->pipe);
|
|
maxp = usb_maxpacket (urb->dev, urb->pipe, !is_input);
|
|
|
|
/* Compute interrupt scheduling parameters just once, and save.
|
|
* - allowing for high bandwidth, how many nsec/uframe are used?
|
|
* - split transactions need a second CSPLIT uframe; same question
|
|
* - splits also need a schedule gap (for full/low speed I/O)
|
|
* - qh has a polling interval
|
|
*
|
|
* For control/bulk requests, the HC or TT handles these.
|
|
*/
|
|
if (type == PIPE_INTERRUPT) {
|
|
qh->usecs = NS_TO_US (usb_calc_bus_time (USB_SPEED_HIGH, is_input, 0,
|
|
hb_mult (maxp) * max_packet (maxp)));
|
|
qh->start = NO_FRAME;
|
|
|
|
if (urb->dev->speed == USB_SPEED_HIGH) {
|
|
qh->c_usecs = 0;
|
|
qh->gap_uf = 0;
|
|
|
|
qh->period = urb->interval >> 3;
|
|
if (qh->period == 0 && urb->interval != 1) {
|
|
/* NOTE interval 2 or 4 uframes could work.
|
|
* But interval 1 scheduling is simpler, and
|
|
* includes high bandwidth.
|
|
*/
|
|
dbg ("intr period %d uframes, NYET!",
|
|
urb->interval);
|
|
goto done;
|
|
}
|
|
} else {
|
|
struct usb_tt *tt = urb->dev->tt;
|
|
int think_time;
|
|
|
|
/* gap is f(FS/LS transfer times) */
|
|
qh->gap_uf = 1 + usb_calc_bus_time (urb->dev->speed,
|
|
is_input, 0, maxp) / (125 * 1000);
|
|
|
|
/* FIXME this just approximates SPLIT/CSPLIT times */
|
|
if (is_input) { // SPLIT, gap, CSPLIT+DATA
|
|
qh->c_usecs = qh->usecs + HS_USECS (0);
|
|
qh->usecs = HS_USECS (1);
|
|
} else { // SPLIT+DATA, gap, CSPLIT
|
|
qh->usecs += HS_USECS (1);
|
|
qh->c_usecs = HS_USECS (0);
|
|
}
|
|
|
|
think_time = tt ? tt->think_time : 0;
|
|
qh->tt_usecs = NS_TO_US (think_time +
|
|
usb_calc_bus_time (urb->dev->speed,
|
|
is_input, 0, max_packet (maxp)));
|
|
qh->period = urb->interval;
|
|
}
|
|
}
|
|
|
|
/* support for tt scheduling, and access to toggles */
|
|
qh->dev = urb->dev;
|
|
|
|
/* using TT? */
|
|
switch (urb->dev->speed) {
|
|
case USB_SPEED_LOW:
|
|
info1 |= (1 << 12); /* EPS "low" */
|
|
/* FALL THROUGH */
|
|
|
|
case USB_SPEED_FULL:
|
|
/* EPS 0 means "full" */
|
|
if (type != PIPE_INTERRUPT)
|
|
info1 |= (EHCI_TUNE_RL_TT << 28);
|
|
if (type == PIPE_CONTROL) {
|
|
info1 |= (1 << 27); /* for TT */
|
|
info1 |= 1 << 14; /* toggle from qtd */
|
|
}
|
|
info1 |= maxp << 16;
|
|
|
|
info2 |= (EHCI_TUNE_MULT_TT << 30);
|
|
|
|
/* Some Freescale processors have an erratum in which the
|
|
* port number in the queue head was 0..N-1 instead of 1..N.
|
|
*/
|
|
if (ehci_has_fsl_portno_bug(ehci))
|
|
info2 |= (urb->dev->ttport-1) << 23;
|
|
else
|
|
info2 |= urb->dev->ttport << 23;
|
|
|
|
/* set the address of the TT; for TDI's integrated
|
|
* root hub tt, leave it zeroed.
|
|
*/
|
|
if (!ehci_is_TDI(ehci)
|
|
|| urb->dev->tt->hub !=
|
|
ehci_to_hcd(ehci)->self.root_hub)
|
|
info2 |= urb->dev->tt->hub->devnum << 16;
|
|
|
|
/* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
|
|
|
|
break;
|
|
|
|
case USB_SPEED_HIGH: /* no TT involved */
|
|
info1 |= (2 << 12); /* EPS "high" */
|
|
if (type == PIPE_CONTROL) {
|
|
info1 |= (EHCI_TUNE_RL_HS << 28);
|
|
info1 |= 64 << 16; /* usb2 fixed maxpacket */
|
|
info1 |= 1 << 14; /* toggle from qtd */
|
|
info2 |= (EHCI_TUNE_MULT_HS << 30);
|
|
} else if (type == PIPE_BULK) {
|
|
info1 |= (EHCI_TUNE_RL_HS << 28);
|
|
info1 |= 512 << 16; /* usb2 fixed maxpacket */
|
|
info2 |= (EHCI_TUNE_MULT_HS << 30);
|
|
} else { /* PIPE_INTERRUPT */
|
|
info1 |= max_packet (maxp) << 16;
|
|
info2 |= hb_mult (maxp) << 30;
|
|
}
|
|
break;
|
|
default:
|
|
dbg ("bogus dev %p speed %d", urb->dev, urb->dev->speed);
|
|
done:
|
|
qh_put (qh);
|
|
return NULL;
|
|
}
|
|
|
|
/* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
|
|
|
|
/* init as live, toggle clear, advance to dummy */
|
|
qh->qh_state = QH_STATE_IDLE;
|
|
qh->hw_info1 = cpu_to_hc32(ehci, info1);
|
|
qh->hw_info2 = cpu_to_hc32(ehci, info2);
|
|
usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1);
|
|
qh_refresh (ehci, qh);
|
|
return qh;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/* move qh (and its qtds) onto async queue; maybe enable queue. */
|
|
|
|
static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
|
|
{
|
|
__hc32 dma = QH_NEXT(ehci, qh->qh_dma);
|
|
struct ehci_qh *head;
|
|
|
|
/* (re)start the async schedule? */
|
|
head = ehci->async;
|
|
timer_action_done (ehci, TIMER_ASYNC_OFF);
|
|
if (!head->qh_next.qh) {
|
|
u32 cmd = ehci_readl(ehci, &ehci->regs->command);
|
|
|
|
if (!(cmd & CMD_ASE)) {
|
|
/* in case a clear of CMD_ASE didn't take yet */
|
|
(void)handshake(ehci, &ehci->regs->status,
|
|
STS_ASS, 0, 150);
|
|
cmd |= CMD_ASE | CMD_RUN;
|
|
ehci_writel(ehci, cmd, &ehci->regs->command);
|
|
ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
|
|
/* posted write need not be known to HC yet ... */
|
|
}
|
|
}
|
|
|
|
/* clear halt and/or toggle; and maybe recover from silicon quirk */
|
|
if (qh->qh_state == QH_STATE_IDLE)
|
|
qh_refresh (ehci, qh);
|
|
|
|
/* splice right after start */
|
|
qh->qh_next = head->qh_next;
|
|
qh->hw_next = head->hw_next;
|
|
wmb ();
|
|
|
|
head->qh_next.qh = qh;
|
|
head->hw_next = dma;
|
|
|
|
qh->qh_state = QH_STATE_LINKED;
|
|
/* qtd completions reported later by interrupt */
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* For control/bulk/interrupt, return QH with these TDs appended.
|
|
* Allocates and initializes the QH if necessary.
|
|
* Returns null if it can't allocate a QH it needs to.
|
|
* If the QH has TDs (urbs) already, that's great.
|
|
*/
|
|
static struct ehci_qh *qh_append_tds (
|
|
struct ehci_hcd *ehci,
|
|
struct urb *urb,
|
|
struct list_head *qtd_list,
|
|
int epnum,
|
|
void **ptr
|
|
)
|
|
{
|
|
struct ehci_qh *qh = NULL;
|
|
u32 qh_addr_mask = cpu_to_hc32(ehci, 0x7f);
|
|
|
|
qh = (struct ehci_qh *) *ptr;
|
|
if (unlikely (qh == NULL)) {
|
|
/* can't sleep here, we have ehci->lock... */
|
|
qh = qh_make (ehci, urb, GFP_ATOMIC);
|
|
*ptr = qh;
|
|
}
|
|
if (likely (qh != NULL)) {
|
|
struct ehci_qtd *qtd;
|
|
|
|
if (unlikely (list_empty (qtd_list)))
|
|
qtd = NULL;
|
|
else
|
|
qtd = list_entry (qtd_list->next, struct ehci_qtd,
|
|
qtd_list);
|
|
|
|
/* control qh may need patching ... */
|
|
if (unlikely (epnum == 0)) {
|
|
|
|
/* usb_reset_device() briefly reverts to address 0 */
|
|
if (usb_pipedevice (urb->pipe) == 0)
|
|
qh->hw_info1 &= ~qh_addr_mask;
|
|
}
|
|
|
|
/* just one way to queue requests: swap with the dummy qtd.
|
|
* only hc or qh_refresh() ever modify the overlay.
|
|
*/
|
|
if (likely (qtd != NULL)) {
|
|
struct ehci_qtd *dummy;
|
|
dma_addr_t dma;
|
|
__hc32 token;
|
|
|
|
/* to avoid racing the HC, use the dummy td instead of
|
|
* the first td of our list (becomes new dummy). both
|
|
* tds stay deactivated until we're done, when the
|
|
* HC is allowed to fetch the old dummy (4.10.2).
|
|
*/
|
|
token = qtd->hw_token;
|
|
qtd->hw_token = HALT_BIT(ehci);
|
|
wmb ();
|
|
dummy = qh->dummy;
|
|
|
|
dma = dummy->qtd_dma;
|
|
*dummy = *qtd;
|
|
dummy->qtd_dma = dma;
|
|
|
|
list_del (&qtd->qtd_list);
|
|
list_add (&dummy->qtd_list, qtd_list);
|
|
__list_splice (qtd_list, qh->qtd_list.prev);
|
|
|
|
ehci_qtd_init(ehci, qtd, qtd->qtd_dma);
|
|
qh->dummy = qtd;
|
|
|
|
/* hc must see the new dummy at list end */
|
|
dma = qtd->qtd_dma;
|
|
qtd = list_entry (qh->qtd_list.prev,
|
|
struct ehci_qtd, qtd_list);
|
|
qtd->hw_next = QTD_NEXT(ehci, dma);
|
|
|
|
/* let the hc process these next qtds */
|
|
wmb ();
|
|
dummy->hw_token = token;
|
|
|
|
urb->hcpriv = qh_get (qh);
|
|
}
|
|
}
|
|
return qh;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static int
|
|
submit_async (
|
|
struct ehci_hcd *ehci,
|
|
struct usb_host_endpoint *ep,
|
|
struct urb *urb,
|
|
struct list_head *qtd_list,
|
|
gfp_t mem_flags
|
|
) {
|
|
struct ehci_qtd *qtd;
|
|
int epnum;
|
|
unsigned long flags;
|
|
struct ehci_qh *qh = NULL;
|
|
int rc = 0;
|
|
|
|
qtd = list_entry (qtd_list->next, struct ehci_qtd, qtd_list);
|
|
epnum = ep->desc.bEndpointAddress;
|
|
|
|
#ifdef EHCI_URB_TRACE
|
|
ehci_dbg (ehci,
|
|
"%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
|
|
__FUNCTION__, urb->dev->devpath, urb,
|
|
epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
|
|
urb->transfer_buffer_length,
|
|
qtd, ep->hcpriv);
|
|
#endif
|
|
|
|
spin_lock_irqsave (&ehci->lock, flags);
|
|
if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
|
|
&ehci_to_hcd(ehci)->flags))) {
|
|
rc = -ESHUTDOWN;
|
|
goto done;
|
|
}
|
|
|
|
qh = qh_append_tds (ehci, urb, qtd_list, epnum, &ep->hcpriv);
|
|
if (unlikely(qh == NULL)) {
|
|
rc = -ENOMEM;
|
|
goto done;
|
|
}
|
|
|
|
/* Control/bulk operations through TTs don't need scheduling,
|
|
* the HC and TT handle it when the TT has a buffer ready.
|
|
*/
|
|
if (likely (qh->qh_state == QH_STATE_IDLE))
|
|
qh_link_async (ehci, qh_get (qh));
|
|
done:
|
|
spin_unlock_irqrestore (&ehci->lock, flags);
|
|
if (unlikely (qh == NULL))
|
|
qtd_list_free (ehci, urb, qtd_list);
|
|
return rc;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/* the async qh for the qtds being reclaimed are now unlinked from the HC */
|
|
|
|
static void end_unlink_async (struct ehci_hcd *ehci)
|
|
{
|
|
struct ehci_qh *qh = ehci->reclaim;
|
|
struct ehci_qh *next;
|
|
|
|
timer_action_done (ehci, TIMER_IAA_WATCHDOG);
|
|
|
|
// qh->hw_next = cpu_to_hc32(qh->qh_dma);
|
|
qh->qh_state = QH_STATE_IDLE;
|
|
qh->qh_next.qh = NULL;
|
|
qh_put (qh); // refcount from reclaim
|
|
|
|
/* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
|
|
next = qh->reclaim;
|
|
ehci->reclaim = next;
|
|
ehci->reclaim_ready = 0;
|
|
qh->reclaim = NULL;
|
|
|
|
qh_completions (ehci, qh);
|
|
|
|
if (!list_empty (&qh->qtd_list)
|
|
&& HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
|
|
qh_link_async (ehci, qh);
|
|
else {
|
|
qh_put (qh); // refcount from async list
|
|
|
|
/* it's not free to turn the async schedule on/off; leave it
|
|
* active but idle for a while once it empties.
|
|
*/
|
|
if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
|
|
&& ehci->async->qh_next.qh == NULL)
|
|
timer_action (ehci, TIMER_ASYNC_OFF);
|
|
}
|
|
|
|
if (next) {
|
|
ehci->reclaim = NULL;
|
|
start_unlink_async (ehci, next);
|
|
}
|
|
}
|
|
|
|
/* makes sure the async qh will become idle */
|
|
/* caller must own ehci->lock */
|
|
|
|
static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
|
|
{
|
|
int cmd = ehci_readl(ehci, &ehci->regs->command);
|
|
struct ehci_qh *prev;
|
|
|
|
#ifdef DEBUG
|
|
assert_spin_locked(&ehci->lock);
|
|
if (ehci->reclaim
|
|
|| (qh->qh_state != QH_STATE_LINKED
|
|
&& qh->qh_state != QH_STATE_UNLINK_WAIT)
|
|
)
|
|
BUG ();
|
|
#endif
|
|
|
|
/* stop async schedule right now? */
|
|
if (unlikely (qh == ehci->async)) {
|
|
/* can't get here without STS_ASS set */
|
|
if (ehci_to_hcd(ehci)->state != HC_STATE_HALT
|
|
&& !ehci->reclaim) {
|
|
/* ... and CMD_IAAD clear */
|
|
ehci_writel(ehci, cmd & ~CMD_ASE,
|
|
&ehci->regs->command);
|
|
wmb ();
|
|
// handshake later, if we need to
|
|
timer_action_done (ehci, TIMER_ASYNC_OFF);
|
|
}
|
|
return;
|
|
}
|
|
|
|
qh->qh_state = QH_STATE_UNLINK;
|
|
ehci->reclaim = qh = qh_get (qh);
|
|
|
|
prev = ehci->async;
|
|
while (prev->qh_next.qh != qh)
|
|
prev = prev->qh_next.qh;
|
|
|
|
prev->hw_next = qh->hw_next;
|
|
prev->qh_next = qh->qh_next;
|
|
wmb ();
|
|
|
|
if (unlikely (ehci_to_hcd(ehci)->state == HC_STATE_HALT)) {
|
|
/* if (unlikely (qh->reclaim != 0))
|
|
* this will recurse, probably not much
|
|
*/
|
|
end_unlink_async (ehci);
|
|
return;
|
|
}
|
|
|
|
ehci->reclaim_ready = 0;
|
|
cmd |= CMD_IAAD;
|
|
ehci_writel(ehci, cmd, &ehci->regs->command);
|
|
(void)ehci_readl(ehci, &ehci->regs->command);
|
|
timer_action (ehci, TIMER_IAA_WATCHDOG);
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static void scan_async (struct ehci_hcd *ehci)
|
|
{
|
|
struct ehci_qh *qh;
|
|
enum ehci_timer_action action = TIMER_IO_WATCHDOG;
|
|
|
|
if (!++(ehci->stamp))
|
|
ehci->stamp++;
|
|
timer_action_done (ehci, TIMER_ASYNC_SHRINK);
|
|
rescan:
|
|
qh = ehci->async->qh_next.qh;
|
|
if (likely (qh != NULL)) {
|
|
do {
|
|
/* clean any finished work for this qh */
|
|
if (!list_empty (&qh->qtd_list)
|
|
&& qh->stamp != ehci->stamp) {
|
|
int temp;
|
|
|
|
/* unlinks could happen here; completion
|
|
* reporting drops the lock. rescan using
|
|
* the latest schedule, but don't rescan
|
|
* qhs we already finished (no looping).
|
|
*/
|
|
qh = qh_get (qh);
|
|
qh->stamp = ehci->stamp;
|
|
temp = qh_completions (ehci, qh);
|
|
qh_put (qh);
|
|
if (temp != 0) {
|
|
goto rescan;
|
|
}
|
|
}
|
|
|
|
/* unlink idle entries, reducing HC PCI usage as well
|
|
* as HCD schedule-scanning costs. delay for any qh
|
|
* we just scanned, there's a not-unusual case that it
|
|
* doesn't stay idle for long.
|
|
* (plus, avoids some kind of re-activation race.)
|
|
*/
|
|
if (list_empty (&qh->qtd_list)) {
|
|
if (qh->stamp == ehci->stamp)
|
|
action = TIMER_ASYNC_SHRINK;
|
|
else if (!ehci->reclaim
|
|
&& qh->qh_state == QH_STATE_LINKED)
|
|
start_unlink_async (ehci, qh);
|
|
}
|
|
|
|
qh = qh->qh_next.qh;
|
|
} while (qh);
|
|
}
|
|
if (action == TIMER_ASYNC_SHRINK)
|
|
timer_action (ehci, TIMER_ASYNC_SHRINK);
|
|
}
|