![Geoff Levand](/assets/img/avatar_default.png)
USB HCD glue updates to reflect the new PS3 unifed device support.
- Fixed remove() routine.
- Added shutdown() routine.
- Added request_mem_region() call.
- Fixed MODULE_ALIAS().
- Made a proper fix for the hack done to support muti-platform in commit
48fda45120
.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
1080 lines
30 KiB
C
1080 lines
30 KiB
C
/*
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* Copyright (c) 2000-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/dmapool.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/timer.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <linux/usb.h>
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#include <linux/moduleparam.h>
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#include <linux/dma-mapping.h>
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#include "../core/hcd.h"
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/unaligned.h>
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI hc_driver implementation ... experimental, incomplete.
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* Based on the final 1.0 register interface specification.
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*
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* USB 2.0 shows up in upcoming www.pcmcia.org technology.
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* First was PCMCIA, like ISA; then CardBus, which is PCI.
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* Next comes "CardBay", using USB 2.0 signals.
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*
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* Contains additional contributions by Brad Hards, Rory Bolt, and others.
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* Special thanks to Intel and VIA for providing host controllers to
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* test this driver on, and Cypress (including In-System Design) for
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* providing early devices for those host controllers to talk to!
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*
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* HISTORY:
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*
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* 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
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* 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
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* 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
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* <sojkam@centrum.cz>, updates by DB).
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*
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* 2002-11-29 Correct handling for hw async_next register.
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* 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
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* only scheduling is different, no arbitrary limitations.
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* 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
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* clean up HC run state handshaking.
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* 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
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* 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
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* missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
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* 2002-05-07 Some error path cleanups to report better errors; wmb();
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* use non-CVS version id; better iso bandwidth claim.
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* 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
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* errors in submit path. Bugfixes to interrupt scheduling/processing.
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* 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
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* more checking to generic hcd framework (db). Make it work with
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* Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
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* 2002-01-14 Minor cleanup; version synch.
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* 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
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* 2002-01-04 Control/Bulk queuing behaves.
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*
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* 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
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* 2001-June Works with usb-storage and NEC EHCI on 2.4
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*/
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#define DRIVER_VERSION "10 Dec 2004"
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#define DRIVER_AUTHOR "David Brownell"
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#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
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static const char hcd_name [] = "ehci_hcd";
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#undef EHCI_VERBOSE_DEBUG
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#undef EHCI_URB_TRACE
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#ifdef DEBUG
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#define EHCI_STATS
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#endif
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/* magic numbers that can affect system performance */
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#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
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#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
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#define EHCI_TUNE_RL_TT 0
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#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
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#define EHCI_TUNE_MULT_TT 1
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#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
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#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
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#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
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#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
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#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
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/* Initial IRQ latency: faster than hw default */
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static int log2_irq_thresh = 0; // 0 to 6
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module_param (log2_irq_thresh, int, S_IRUGO);
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MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
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/* initial park setting: slower than hw default */
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static unsigned park = 0;
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module_param (park, uint, S_IRUGO);
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MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
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/* for flakey hardware, ignore overcurrent indicators */
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static int ignore_oc = 0;
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module_param (ignore_oc, bool, S_IRUGO);
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MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
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#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
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/*-------------------------------------------------------------------------*/
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#include "ehci.h"
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#include "ehci-dbg.c"
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/*-------------------------------------------------------------------------*/
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/*
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* handshake - spin reading hc until handshake completes or fails
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* @ptr: address of hc register to be read
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* @mask: bits to look at in result of read
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* @done: value of those bits when handshake succeeds
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* @usec: timeout in microseconds
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*
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* Returns negative errno, or zero on success
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*
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* Success happens when the "mask" bits have the specified value (hardware
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* handshake done). There are two failure modes: "usec" have passed (major
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* hardware flakeout), or the register reads as all-ones (hardware removed).
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*
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* That last failure should_only happen in cases like physical cardbus eject
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* before driver shutdown. But it also seems to be caused by bugs in cardbus
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* bridge shutdown: shutting down the bridge before the devices using it.
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*/
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static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
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u32 mask, u32 done, int usec)
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{
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u32 result;
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do {
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result = ehci_readl(ehci, ptr);
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if (result == ~(u32)0) /* card removed */
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return -ENODEV;
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result &= mask;
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if (result == done)
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return 0;
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udelay (1);
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usec--;
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} while (usec > 0);
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return -ETIMEDOUT;
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}
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/* force HC to halt state from unknown (EHCI spec section 2.3) */
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static int ehci_halt (struct ehci_hcd *ehci)
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{
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u32 temp = ehci_readl(ehci, &ehci->regs->status);
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/* disable any irqs left enabled by previous code */
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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if ((temp & STS_HALT) != 0)
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return 0;
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temp = ehci_readl(ehci, &ehci->regs->command);
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temp &= ~CMD_RUN;
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ehci_writel(ehci, temp, &ehci->regs->command);
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return handshake (ehci, &ehci->regs->status,
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STS_HALT, STS_HALT, 16 * 125);
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}
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/* put TDI/ARC silicon into EHCI mode */
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static void tdi_reset (struct ehci_hcd *ehci)
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{
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u32 __iomem *reg_ptr;
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u32 tmp;
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reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
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tmp = ehci_readl(ehci, reg_ptr);
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tmp |= USBMODE_CM_HC;
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/* The default byte access to MMR space is LE after
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* controller reset. Set the required endian mode
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* for transfer buffers to match the host microprocessor
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*/
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if (ehci_big_endian_mmio(ehci))
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tmp |= USBMODE_BE;
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ehci_writel(ehci, tmp, reg_ptr);
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}
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/* reset a non-running (STS_HALT == 1) controller */
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static int ehci_reset (struct ehci_hcd *ehci)
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{
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int retval;
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u32 command = ehci_readl(ehci, &ehci->regs->command);
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command |= CMD_RESET;
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dbg_cmd (ehci, "reset", command);
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ehci_writel(ehci, command, &ehci->regs->command);
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ehci_to_hcd(ehci)->state = HC_STATE_HALT;
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ehci->next_statechange = jiffies;
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retval = handshake (ehci, &ehci->regs->command,
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CMD_RESET, 0, 250 * 1000);
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if (retval)
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return retval;
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if (ehci_is_TDI(ehci))
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tdi_reset (ehci);
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return retval;
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}
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/* idle the controller (from running) */
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static void ehci_quiesce (struct ehci_hcd *ehci)
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{
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u32 temp;
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#ifdef DEBUG
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if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
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BUG ();
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#endif
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/* wait for any schedule enables/disables to take effect */
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temp = ehci_readl(ehci, &ehci->regs->command) << 10;
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temp &= STS_ASS | STS_PSS;
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if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS,
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temp, 16 * 125) != 0) {
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ehci_to_hcd(ehci)->state = HC_STATE_HALT;
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return;
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}
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/* then disable anything that's still active */
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temp = ehci_readl(ehci, &ehci->regs->command);
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temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
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ehci_writel(ehci, temp, &ehci->regs->command);
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/* hardware can take 16 microframes to turn off ... */
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if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS,
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0, 16 * 125) != 0) {
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ehci_to_hcd(ehci)->state = HC_STATE_HALT;
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return;
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}
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}
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/*-------------------------------------------------------------------------*/
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static void ehci_work(struct ehci_hcd *ehci);
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#include "ehci-hub.c"
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#include "ehci-mem.c"
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#include "ehci-q.c"
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#include "ehci-sched.c"
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/*-------------------------------------------------------------------------*/
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#ifdef CONFIG_CPU_FREQ
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#include <linux/cpufreq.h>
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static void ehci_cpufreq_pause (struct ehci_hcd *ehci)
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{
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unsigned long flags;
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spin_lock_irqsave(&ehci->lock, flags);
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if (!ehci->cpufreq_changing++)
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qh_inactivate_split_intr_qhs(ehci);
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spin_unlock_irqrestore(&ehci->lock, flags);
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}
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static void ehci_cpufreq_unpause (struct ehci_hcd *ehci)
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{
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unsigned long flags;
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spin_lock_irqsave(&ehci->lock, flags);
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if (!--ehci->cpufreq_changing)
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qh_reactivate_split_intr_qhs(ehci);
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spin_unlock_irqrestore(&ehci->lock, flags);
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}
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/*
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* ehci_cpufreq_notifier is needed to avoid MMF errors that occur when
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* EHCI controllers that don't cache many uframes get delayed trying to
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* read main memory during CPU frequency transitions. This can cause
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* split interrupt transactions to not be completed in the required uframe.
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* This has been observed on the Broadcom/ServerWorks HT1000 controller.
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*/
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static int ehci_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct ehci_hcd *ehci = container_of(nb, struct ehci_hcd,
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cpufreq_transition);
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switch (val) {
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case CPUFREQ_PRECHANGE:
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ehci_cpufreq_pause(ehci);
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break;
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case CPUFREQ_POSTCHANGE:
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ehci_cpufreq_unpause(ehci);
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break;
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}
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return 0;
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}
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#endif
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/*-------------------------------------------------------------------------*/
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static void ehci_watchdog (unsigned long param)
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{
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struct ehci_hcd *ehci = (struct ehci_hcd *) param;
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unsigned long flags;
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spin_lock_irqsave (&ehci->lock, flags);
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/* lost IAA irqs wedge things badly; seen with a vt8235 */
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if (ehci->reclaim) {
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u32 status = ehci_readl(ehci, &ehci->regs->status);
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if (status & STS_IAA) {
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ehci_vdbg (ehci, "lost IAA\n");
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COUNT (ehci->stats.lost_iaa);
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ehci_writel(ehci, STS_IAA, &ehci->regs->status);
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ehci->reclaim_ready = 1;
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}
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}
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/* stop async processing after it's idled a bit */
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if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
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start_unlink_async (ehci, ehci->async);
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/* ehci could run by timer, without IRQs ... */
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ehci_work (ehci);
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spin_unlock_irqrestore (&ehci->lock, flags);
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}
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/* On some systems, leaving remote wakeup enabled prevents system shutdown.
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* The firmware seems to think that powering off is a wakeup event!
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* This routine turns off remote wakeup and everything else, on all ports.
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*/
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static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
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{
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int port = HCS_N_PORTS(ehci->hcs_params);
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while (port--)
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ehci_writel(ehci, PORT_RWC_BITS,
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&ehci->regs->port_status[port]);
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}
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/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
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* This forcibly disables dma and IRQs, helping kexec and other cases
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* where the next system software may expect clean state.
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*/
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static void
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ehci_shutdown (struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci;
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ehci = hcd_to_ehci (hcd);
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(void) ehci_halt (ehci);
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ehci_turn_off_all_ports(ehci);
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/* make BIOS/etc use companion controller during reboot */
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ehci_writel(ehci, 0, &ehci->regs->configured_flag);
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/* unblock posted writes */
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ehci_readl(ehci, &ehci->regs->configured_flag);
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}
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static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
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{
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unsigned port;
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if (!HCS_PPC (ehci->hcs_params))
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return;
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ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
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for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
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(void) ehci_hub_control(ehci_to_hcd(ehci),
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is_on ? SetPortFeature : ClearPortFeature,
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USB_PORT_FEAT_POWER,
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port--, NULL, 0);
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/* Flush those writes */
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ehci_readl(ehci, &ehci->regs->command);
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msleep(20);
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}
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/*-------------------------------------------------------------------------*/
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/*
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* ehci_work is called from some interrupts, timers, and so on.
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* it calls driver completion functions, after dropping ehci->lock.
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*/
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static void ehci_work (struct ehci_hcd *ehci)
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{
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timer_action_done (ehci, TIMER_IO_WATCHDOG);
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if (ehci->reclaim_ready)
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end_unlink_async (ehci);
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/* another CPU may drop ehci->lock during a schedule scan while
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* it reports urb completions. this flag guards against bogus
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* attempts at re-entrant schedule scanning.
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*/
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if (ehci->scanning)
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return;
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ehci->scanning = 1;
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scan_async (ehci);
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if (ehci->next_uframe != -1)
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scan_periodic (ehci);
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ehci->scanning = 0;
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/* the IO watchdog guards against hardware or driver bugs that
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* misplace IRQs, and should let us run completely without IRQs.
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* such lossage has been observed on both VT6202 and VT8235.
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*/
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if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
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(ehci->async->qh_next.ptr != NULL ||
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ehci->periodic_sched != 0))
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timer_action (ehci, TIMER_IO_WATCHDOG);
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}
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static void ehci_stop (struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci (hcd);
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ehci_dbg (ehci, "stop\n");
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/* Turn off port power on all root hub ports. */
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ehci_port_power (ehci, 0);
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/* no more interrupts ... */
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del_timer_sync (&ehci->watchdog);
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spin_lock_irq(&ehci->lock);
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if (HC_IS_RUNNING (hcd->state))
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ehci_quiesce (ehci);
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ehci_reset (ehci);
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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spin_unlock_irq(&ehci->lock);
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#ifdef CONFIG_CPU_FREQ
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cpufreq_unregister_notifier(&ehci->cpufreq_transition,
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CPUFREQ_TRANSITION_NOTIFIER);
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#endif
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/* let companion controllers work when we aren't */
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|
ehci_writel(ehci, 0, &ehci->regs->configured_flag);
|
|
|
|
remove_companion_file(ehci);
|
|
remove_debug_files (ehci);
|
|
|
|
/* root hub is shut down separately (first, when possible) */
|
|
spin_lock_irq (&ehci->lock);
|
|
if (ehci->async)
|
|
ehci_work (ehci);
|
|
spin_unlock_irq (&ehci->lock);
|
|
ehci_mem_cleanup (ehci);
|
|
|
|
#ifdef EHCI_STATS
|
|
ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
|
|
ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
|
|
ehci->stats.lost_iaa);
|
|
ehci_dbg (ehci, "complete %ld unlink %ld\n",
|
|
ehci->stats.complete, ehci->stats.unlink);
|
|
#endif
|
|
|
|
dbg_status (ehci, "ehci_stop completed",
|
|
ehci_readl(ehci, &ehci->regs->status));
|
|
}
|
|
|
|
/* one-time init, only for memory state */
|
|
static int ehci_init(struct usb_hcd *hcd)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
|
u32 temp;
|
|
int retval;
|
|
u32 hcc_params;
|
|
|
|
spin_lock_init(&ehci->lock);
|
|
|
|
init_timer(&ehci->watchdog);
|
|
ehci->watchdog.function = ehci_watchdog;
|
|
ehci->watchdog.data = (unsigned long) ehci;
|
|
|
|
/*
|
|
* hw default: 1K periodic list heads, one per frame.
|
|
* periodic_size can shrink by USBCMD update if hcc_params allows.
|
|
*/
|
|
ehci->periodic_size = DEFAULT_I_TDPS;
|
|
if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
|
|
return retval;
|
|
|
|
/* controllers may cache some of the periodic schedule ... */
|
|
hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
|
|
if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
|
|
ehci->i_thresh = 8;
|
|
else // N microframes cached
|
|
ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
|
|
|
|
ehci->reclaim = NULL;
|
|
ehci->reclaim_ready = 0;
|
|
ehci->next_uframe = -1;
|
|
|
|
/*
|
|
* dedicate a qh for the async ring head, since we couldn't unlink
|
|
* a 'real' qh without stopping the async schedule [4.8]. use it
|
|
* as the 'reclamation list head' too.
|
|
* its dummy is used in hw_alt_next of many tds, to prevent the qh
|
|
* from automatically advancing to the next td after short reads.
|
|
*/
|
|
ehci->async->qh_next.qh = NULL;
|
|
ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
|
|
ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
|
|
ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
|
|
ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
|
|
ehci->async->qh_state = QH_STATE_LINKED;
|
|
ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
|
|
|
|
/* clear interrupt enables, set irq latency */
|
|
if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
|
|
log2_irq_thresh = 0;
|
|
temp = 1 << (16 + log2_irq_thresh);
|
|
if (HCC_CANPARK(hcc_params)) {
|
|
/* HW default park == 3, on hardware that supports it (like
|
|
* NVidia and ALI silicon), maximizes throughput on the async
|
|
* schedule by avoiding QH fetches between transfers.
|
|
*
|
|
* With fast usb storage devices and NForce2, "park" seems to
|
|
* make problems: throughput reduction (!), data errors...
|
|
*/
|
|
if (park) {
|
|
park = min(park, (unsigned) 3);
|
|
temp |= CMD_PARK;
|
|
temp |= park << 8;
|
|
}
|
|
ehci_dbg(ehci, "park %d\n", park);
|
|
}
|
|
if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
|
|
/* periodic schedule size can be smaller than default */
|
|
temp &= ~(3 << 2);
|
|
temp |= (EHCI_TUNE_FLS << 2);
|
|
switch (EHCI_TUNE_FLS) {
|
|
case 0: ehci->periodic_size = 1024; break;
|
|
case 1: ehci->periodic_size = 512; break;
|
|
case 2: ehci->periodic_size = 256; break;
|
|
default: BUG();
|
|
}
|
|
}
|
|
ehci->command = temp;
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
INIT_LIST_HEAD(&ehci->split_intr_qhs);
|
|
/*
|
|
* If the EHCI controller caches enough uframes, this probably
|
|
* isn't needed unless there are so many low/full speed devices
|
|
* that the controller's can't cache it all.
|
|
*/
|
|
ehci->cpufreq_transition.notifier_call = ehci_cpufreq_notifier;
|
|
cpufreq_register_notifier(&ehci->cpufreq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/* start HC running; it's halted, ehci_init() has been run (once) */
|
|
static int ehci_run (struct usb_hcd *hcd)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
|
int retval;
|
|
u32 temp;
|
|
u32 hcc_params;
|
|
|
|
hcd->uses_new_polling = 1;
|
|
hcd->poll_rh = 0;
|
|
|
|
/* EHCI spec section 4.1 */
|
|
if ((retval = ehci_reset(ehci)) != 0) {
|
|
ehci_mem_cleanup(ehci);
|
|
return retval;
|
|
}
|
|
ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
|
|
ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
|
|
|
|
/*
|
|
* hcc_params controls whether ehci->regs->segment must (!!!)
|
|
* be used; it constrains QH/ITD/SITD and QTD locations.
|
|
* pci_pool consistent memory always uses segment zero.
|
|
* streaming mappings for I/O buffers, like pci_map_single(),
|
|
* can return segments above 4GB, if the device allows.
|
|
*
|
|
* NOTE: the dma mask is visible through dma_supported(), so
|
|
* drivers can pass this info along ... like NETIF_F_HIGHDMA,
|
|
* Scsi_Host.highmem_io, and so forth. It's readonly to all
|
|
* host side drivers though.
|
|
*/
|
|
hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
|
|
if (HCC_64BIT_ADDR(hcc_params)) {
|
|
ehci_writel(ehci, 0, &ehci->regs->segment);
|
|
#if 0
|
|
// this is deeply broken on almost all architectures
|
|
if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
|
|
ehci_info(ehci, "enabled 64bit DMA\n");
|
|
#endif
|
|
}
|
|
|
|
|
|
// Philips, Intel, and maybe others need CMD_RUN before the
|
|
// root hub will detect new devices (why?); NEC doesn't
|
|
ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
|
|
ehci->command |= CMD_RUN;
|
|
ehci_writel(ehci, ehci->command, &ehci->regs->command);
|
|
dbg_cmd (ehci, "init", ehci->command);
|
|
|
|
/*
|
|
* Start, enabling full USB 2.0 functionality ... usb 1.1 devices
|
|
* are explicitly handed to companion controller(s), so no TT is
|
|
* involved with the root hub. (Except where one is integrated,
|
|
* and there's no companion controller unless maybe for USB OTG.)
|
|
*/
|
|
hcd->state = HC_STATE_RUNNING;
|
|
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
|
|
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
|
|
|
|
temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
|
|
ehci_info (ehci,
|
|
"USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
|
|
((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
|
|
temp >> 8, temp & 0xff, DRIVER_VERSION,
|
|
ignore_oc ? ", overcurrent ignored" : "");
|
|
|
|
ehci_writel(ehci, INTR_MASK,
|
|
&ehci->regs->intr_enable); /* Turn On Interrupts */
|
|
|
|
/* GRR this is run-once init(), being done every time the HC starts.
|
|
* So long as they're part of class devices, we can't do it init()
|
|
* since the class device isn't created that early.
|
|
*/
|
|
create_debug_files(ehci);
|
|
create_companion_file(ehci);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static irqreturn_t ehci_irq (struct usb_hcd *hcd)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
|
u32 status, pcd_status = 0;
|
|
int bh;
|
|
|
|
spin_lock (&ehci->lock);
|
|
|
|
status = ehci_readl(ehci, &ehci->regs->status);
|
|
|
|
/* e.g. cardbus physical eject */
|
|
if (status == ~(u32) 0) {
|
|
ehci_dbg (ehci, "device removed\n");
|
|
goto dead;
|
|
}
|
|
|
|
status &= INTR_MASK;
|
|
if (!status) { /* irq sharing? */
|
|
spin_unlock(&ehci->lock);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/* clear (just) interrupts */
|
|
ehci_writel(ehci, status, &ehci->regs->status);
|
|
ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */
|
|
bh = 0;
|
|
|
|
#ifdef EHCI_VERBOSE_DEBUG
|
|
/* unrequested/ignored: Frame List Rollover */
|
|
dbg_status (ehci, "irq", status);
|
|
#endif
|
|
|
|
/* INT, ERR, and IAA interrupt rates can be throttled */
|
|
|
|
/* normal [4.15.1.2] or error [4.15.1.1] completion */
|
|
if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
|
|
if (likely ((status & STS_ERR) == 0))
|
|
COUNT (ehci->stats.normal);
|
|
else
|
|
COUNT (ehci->stats.error);
|
|
bh = 1;
|
|
}
|
|
|
|
/* complete the unlinking of some qh [4.15.2.3] */
|
|
if (status & STS_IAA) {
|
|
COUNT (ehci->stats.reclaim);
|
|
ehci->reclaim_ready = 1;
|
|
bh = 1;
|
|
}
|
|
|
|
/* remote wakeup [4.3.1] */
|
|
if (status & STS_PCD) {
|
|
unsigned i = HCS_N_PORTS (ehci->hcs_params);
|
|
pcd_status = status;
|
|
|
|
/* resume root hub? */
|
|
if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN))
|
|
usb_hcd_resume_root_hub(hcd);
|
|
|
|
while (i--) {
|
|
int pstatus = ehci_readl(ehci,
|
|
&ehci->regs->port_status [i]);
|
|
|
|
if (pstatus & PORT_OWNER)
|
|
continue;
|
|
if (!(pstatus & PORT_RESUME)
|
|
|| ehci->reset_done [i] != 0)
|
|
continue;
|
|
|
|
/* start 20 msec resume signaling from this port,
|
|
* and make khubd collect PORT_STAT_C_SUSPEND to
|
|
* stop that signaling.
|
|
*/
|
|
ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
|
|
ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
|
|
mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
|
|
}
|
|
}
|
|
|
|
/* PCI errors [4.15.2.4] */
|
|
if (unlikely ((status & STS_FATAL) != 0)) {
|
|
/* bogus "fatal" IRQs appear on some chips... why? */
|
|
status = ehci_readl(ehci, &ehci->regs->status);
|
|
dbg_cmd (ehci, "fatal", ehci_readl(ehci,
|
|
&ehci->regs->command));
|
|
dbg_status (ehci, "fatal", status);
|
|
if (status & STS_HALT) {
|
|
ehci_err (ehci, "fatal error\n");
|
|
dead:
|
|
ehci_reset (ehci);
|
|
ehci_writel(ehci, 0, &ehci->regs->configured_flag);
|
|
/* generic layer kills/unlinks all urbs, then
|
|
* uses ehci_stop to clean up the rest
|
|
*/
|
|
bh = 1;
|
|
}
|
|
}
|
|
|
|
if (bh)
|
|
ehci_work (ehci);
|
|
spin_unlock (&ehci->lock);
|
|
if (pcd_status & STS_PCD)
|
|
usb_hcd_poll_rh_status(hcd);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* non-error returns are a promise to giveback() the urb later
|
|
* we drop ownership so next owner (or urb unlink) can get it
|
|
*
|
|
* urb + dev is in hcd.self.controller.urb_list
|
|
* we're queueing TDs onto software and hardware lists
|
|
*
|
|
* hcd-specific init for hcpriv hasn't been done yet
|
|
*
|
|
* NOTE: control, bulk, and interrupt share the same code to append TDs
|
|
* to a (possibly active) QH, and the same QH scanning code.
|
|
*/
|
|
static int ehci_urb_enqueue (
|
|
struct usb_hcd *hcd,
|
|
struct usb_host_endpoint *ep,
|
|
struct urb *urb,
|
|
gfp_t mem_flags
|
|
) {
|
|
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
|
struct list_head qtd_list;
|
|
|
|
INIT_LIST_HEAD (&qtd_list);
|
|
|
|
switch (usb_pipetype (urb->pipe)) {
|
|
// case PIPE_CONTROL:
|
|
// case PIPE_BULK:
|
|
default:
|
|
if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
|
|
return -ENOMEM;
|
|
return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
|
|
|
|
case PIPE_INTERRUPT:
|
|
if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
|
|
return -ENOMEM;
|
|
return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
|
|
|
|
case PIPE_ISOCHRONOUS:
|
|
if (urb->dev->speed == USB_SPEED_HIGH)
|
|
return itd_submit (ehci, urb, mem_flags);
|
|
else
|
|
return sitd_submit (ehci, urb, mem_flags);
|
|
}
|
|
}
|
|
|
|
static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
|
|
{
|
|
/* if we need to use IAA and it's busy, defer */
|
|
if (qh->qh_state == QH_STATE_LINKED
|
|
&& ehci->reclaim
|
|
&& HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
|
|
struct ehci_qh *last;
|
|
|
|
for (last = ehci->reclaim;
|
|
last->reclaim;
|
|
last = last->reclaim)
|
|
continue;
|
|
qh->qh_state = QH_STATE_UNLINK_WAIT;
|
|
last->reclaim = qh;
|
|
|
|
/* bypass IAA if the hc can't care */
|
|
} else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
|
|
end_unlink_async (ehci);
|
|
|
|
/* something else might have unlinked the qh by now */
|
|
if (qh->qh_state == QH_STATE_LINKED)
|
|
start_unlink_async (ehci, qh);
|
|
}
|
|
|
|
/* remove from hardware lists
|
|
* completions normally happen asynchronously
|
|
*/
|
|
|
|
static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
|
struct ehci_qh *qh;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave (&ehci->lock, flags);
|
|
switch (usb_pipetype (urb->pipe)) {
|
|
// case PIPE_CONTROL:
|
|
// case PIPE_BULK:
|
|
default:
|
|
qh = (struct ehci_qh *) urb->hcpriv;
|
|
if (!qh)
|
|
break;
|
|
unlink_async (ehci, qh);
|
|
break;
|
|
|
|
case PIPE_INTERRUPT:
|
|
qh = (struct ehci_qh *) urb->hcpriv;
|
|
if (!qh)
|
|
break;
|
|
switch (qh->qh_state) {
|
|
case QH_STATE_LINKED:
|
|
intr_deschedule (ehci, qh);
|
|
/* FALL THROUGH */
|
|
case QH_STATE_IDLE:
|
|
qh_completions (ehci, qh);
|
|
break;
|
|
default:
|
|
ehci_dbg (ehci, "bogus qh %p state %d\n",
|
|
qh, qh->qh_state);
|
|
goto done;
|
|
}
|
|
|
|
/* reschedule QH iff another request is queued */
|
|
if (!list_empty (&qh->qtd_list)
|
|
&& HC_IS_RUNNING (hcd->state)) {
|
|
int status;
|
|
|
|
status = qh_schedule (ehci, qh);
|
|
spin_unlock_irqrestore (&ehci->lock, flags);
|
|
|
|
if (status != 0) {
|
|
// shouldn't happen often, but ...
|
|
// FIXME kill those tds' urbs
|
|
err ("can't reschedule qh %p, err %d",
|
|
qh, status);
|
|
}
|
|
return status;
|
|
}
|
|
break;
|
|
|
|
case PIPE_ISOCHRONOUS:
|
|
// itd or sitd ...
|
|
|
|
// wait till next completion, do it then.
|
|
// completion irqs can wait up to 1024 msec,
|
|
break;
|
|
}
|
|
done:
|
|
spin_unlock_irqrestore (&ehci->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
// bulk qh holds the data toggle
|
|
|
|
static void
|
|
ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
|
unsigned long flags;
|
|
struct ehci_qh *qh, *tmp;
|
|
|
|
/* ASSERT: any requests/urbs are being unlinked */
|
|
/* ASSERT: nobody can be submitting urbs for this any more */
|
|
|
|
rescan:
|
|
spin_lock_irqsave (&ehci->lock, flags);
|
|
qh = ep->hcpriv;
|
|
if (!qh)
|
|
goto done;
|
|
|
|
/* endpoints can be iso streams. for now, we don't
|
|
* accelerate iso completions ... so spin a while.
|
|
*/
|
|
if (qh->hw_info1 == 0) {
|
|
ehci_vdbg (ehci, "iso delay\n");
|
|
goto idle_timeout;
|
|
}
|
|
|
|
if (!HC_IS_RUNNING (hcd->state))
|
|
qh->qh_state = QH_STATE_IDLE;
|
|
switch (qh->qh_state) {
|
|
case QH_STATE_LINKED:
|
|
for (tmp = ehci->async->qh_next.qh;
|
|
tmp && tmp != qh;
|
|
tmp = tmp->qh_next.qh)
|
|
continue;
|
|
/* periodic qh self-unlinks on empty */
|
|
if (!tmp)
|
|
goto nogood;
|
|
unlink_async (ehci, qh);
|
|
/* FALL THROUGH */
|
|
case QH_STATE_UNLINK: /* wait for hw to finish? */
|
|
idle_timeout:
|
|
spin_unlock_irqrestore (&ehci->lock, flags);
|
|
schedule_timeout_uninterruptible(1);
|
|
goto rescan;
|
|
case QH_STATE_IDLE: /* fully unlinked */
|
|
if (list_empty (&qh->qtd_list)) {
|
|
qh_put (qh);
|
|
break;
|
|
}
|
|
/* else FALL THROUGH */
|
|
default:
|
|
nogood:
|
|
/* caller was supposed to have unlinked any requests;
|
|
* that's not our job. just leak this memory.
|
|
*/
|
|
ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
|
|
qh, ep->desc.bEndpointAddress, qh->qh_state,
|
|
list_empty (&qh->qtd_list) ? "" : "(has tds)");
|
|
break;
|
|
}
|
|
ep->hcpriv = NULL;
|
|
done:
|
|
spin_unlock_irqrestore (&ehci->lock, flags);
|
|
return;
|
|
}
|
|
|
|
static int ehci_get_frame (struct usb_hcd *hcd)
|
|
{
|
|
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
|
return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
|
|
ehci->periodic_size;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
|
|
|
|
MODULE_DESCRIPTION (DRIVER_INFO);
|
|
MODULE_AUTHOR (DRIVER_AUTHOR);
|
|
MODULE_LICENSE ("GPL");
|
|
|
|
#ifdef CONFIG_PCI
|
|
#include "ehci-pci.c"
|
|
#define PCI_DRIVER ehci_pci_driver
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_EHCI_FSL
|
|
#include "ehci-fsl.c"
|
|
#define PLATFORM_DRIVER ehci_fsl_driver
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AU1200
|
|
#include "ehci-au1xxx.c"
|
|
#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
|
|
#endif
|
|
|
|
#ifdef CONFIG_PPC_PS3
|
|
#include "ehci-ps3.c"
|
|
#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
|
|
#endif
|
|
|
|
#ifdef CONFIG_440EPX
|
|
#include "ehci-ppc-soc.c"
|
|
#define PLATFORM_DRIVER ehci_ppc_soc_driver
|
|
#endif
|
|
|
|
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
|
|
!defined(PS3_SYSTEM_BUS_DRIVER)
|
|
#error "missing bus glue for ehci-hcd"
|
|
#endif
|
|
|
|
static int __init ehci_hcd_init(void)
|
|
{
|
|
int retval = 0;
|
|
|
|
pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
|
|
hcd_name,
|
|
sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
|
|
sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
|
|
|
|
#ifdef PLATFORM_DRIVER
|
|
retval = platform_driver_register(&PLATFORM_DRIVER);
|
|
if (retval < 0)
|
|
return retval;
|
|
#endif
|
|
|
|
#ifdef PCI_DRIVER
|
|
retval = pci_register_driver(&PCI_DRIVER);
|
|
if (retval < 0) {
|
|
#ifdef PLATFORM_DRIVER
|
|
platform_driver_unregister(&PLATFORM_DRIVER);
|
|
#endif
|
|
return retval;
|
|
}
|
|
#endif
|
|
|
|
#ifdef PS3_SYSTEM_BUS_DRIVER
|
|
retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
|
|
if (retval < 0) {
|
|
#ifdef PLATFORM_DRIVER
|
|
platform_driver_unregister(&PLATFORM_DRIVER);
|
|
#endif
|
|
#ifdef PCI_DRIVER
|
|
pci_unregister_driver(&PCI_DRIVER);
|
|
#endif
|
|
return retval;
|
|
}
|
|
#endif
|
|
|
|
return retval;
|
|
}
|
|
module_init(ehci_hcd_init);
|
|
|
|
static void __exit ehci_hcd_cleanup(void)
|
|
{
|
|
#ifdef PLATFORM_DRIVER
|
|
platform_driver_unregister(&PLATFORM_DRIVER);
|
|
#endif
|
|
#ifdef PCI_DRIVER
|
|
pci_unregister_driver(&PCI_DRIVER);
|
|
#endif
|
|
#ifdef PS3_SYSTEM_BUS_DRIVER
|
|
ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
|
|
#endif
|
|
}
|
|
module_exit(ehci_hcd_cleanup);
|
|
|