![Dale Farnsworth](/assets/img/avatar_default.png)
Convert the Marvell mv64xxx I2C driver to use the new i2c infrastructure, by calling i2c_add_numbered_adapter(). This allows clients to be registered before the bus is instantiated. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
601 lines
17 KiB
C
601 lines
17 KiB
C
/*
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* Driver for the i2c controller on the Marvell line of host bridges for MIPS
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* and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2005 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mv643xx.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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/* Register defines */
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#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
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#define MV64XXX_I2C_REG_DATA 0x04
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#define MV64XXX_I2C_REG_CONTROL 0x08
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#define MV64XXX_I2C_REG_STATUS 0x0c
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#define MV64XXX_I2C_REG_BAUD 0x0c
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#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
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#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
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#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
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#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
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#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
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#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
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#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
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#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
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/* Ctlr status values */
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#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
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#define MV64XXX_I2C_STATUS_MAST_START 0x08
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#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
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#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
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#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
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#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
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#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
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#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
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#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
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#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
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#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
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#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
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#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
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#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
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#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
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#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
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#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
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/* Driver states */
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enum {
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MV64XXX_I2C_STATE_INVALID,
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MV64XXX_I2C_STATE_IDLE,
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MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
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MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
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MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
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MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
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MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
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};
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/* Driver actions */
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enum {
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MV64XXX_I2C_ACTION_INVALID,
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MV64XXX_I2C_ACTION_CONTINUE,
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MV64XXX_I2C_ACTION_SEND_START,
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MV64XXX_I2C_ACTION_SEND_ADDR_1,
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MV64XXX_I2C_ACTION_SEND_ADDR_2,
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MV64XXX_I2C_ACTION_SEND_DATA,
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MV64XXX_I2C_ACTION_RCV_DATA,
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MV64XXX_I2C_ACTION_RCV_DATA_STOP,
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MV64XXX_I2C_ACTION_SEND_STOP,
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};
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struct mv64xxx_i2c_data {
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int irq;
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u32 state;
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u32 action;
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u32 aborting;
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u32 cntl_bits;
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void __iomem *reg_base;
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u32 reg_base_p;
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u32 addr1;
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u32 addr2;
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u32 bytes_left;
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u32 byte_posn;
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u32 block;
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int rc;
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u32 freq_m;
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u32 freq_n;
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wait_queue_head_t waitq;
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spinlock_t lock;
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struct i2c_msg *msg;
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struct i2c_adapter adapter;
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};
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/*
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*****************************************************************************
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*
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* Finite State Machine & Interrupt Routines
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*
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*****************************************************************************
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*/
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static void
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mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
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{
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/*
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* If state is idle, then this is likely the remnants of an old
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* operation that driver has given up on or the user has killed.
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* If so, issue the stop condition and go to idle.
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*/
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if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
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return;
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}
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/* The status from the ctlr [mostly] tells us what to do next */
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switch (status) {
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/* Start condition interrupt */
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case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
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case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
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drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
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drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
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break;
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/* Performing a write */
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case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
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if (drv_data->msg->flags & I2C_M_TEN) {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
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drv_data->state =
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MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
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break;
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}
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/* FALLTHRU */
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case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
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case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
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if ((drv_data->bytes_left == 0)
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|| (drv_data->aborting
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&& (drv_data->byte_posn != 0))) {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
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drv_data->state = MV64XXX_I2C_STATE_IDLE;
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} else {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
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drv_data->state =
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MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
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drv_data->bytes_left--;
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}
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break;
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/* Performing a read */
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case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
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if (drv_data->msg->flags & I2C_M_TEN) {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
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drv_data->state =
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MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
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break;
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}
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/* FALLTHRU */
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case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
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if (drv_data->bytes_left == 0) {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
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drv_data->state = MV64XXX_I2C_STATE_IDLE;
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break;
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}
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/* FALLTHRU */
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case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
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if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
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drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
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else {
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drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
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drv_data->bytes_left--;
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}
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drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
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if ((drv_data->bytes_left == 1) || drv_data->aborting)
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drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
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break;
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case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
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drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
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drv_data->state = MV64XXX_I2C_STATE_IDLE;
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break;
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case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
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case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
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case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
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/* Doesn't seem to be a device at other end */
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drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
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drv_data->state = MV64XXX_I2C_STATE_IDLE;
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drv_data->rc = -ENODEV;
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break;
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default:
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dev_err(&drv_data->adapter.dev,
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"mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
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"status: 0x%x, addr: 0x%x, flags: 0x%x\n",
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drv_data->state, status, drv_data->msg->addr,
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drv_data->msg->flags);
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drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
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drv_data->state = MV64XXX_I2C_STATE_IDLE;
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drv_data->rc = -EIO;
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}
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}
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static void
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mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
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{
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switch(drv_data->action) {
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case MV64XXX_I2C_ACTION_CONTINUE:
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writel(drv_data->cntl_bits,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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break;
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case MV64XXX_I2C_ACTION_SEND_START:
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writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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break;
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case MV64XXX_I2C_ACTION_SEND_ADDR_1:
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writel(drv_data->addr1,
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drv_data->reg_base + MV64XXX_I2C_REG_DATA);
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writel(drv_data->cntl_bits,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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break;
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case MV64XXX_I2C_ACTION_SEND_ADDR_2:
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writel(drv_data->addr2,
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drv_data->reg_base + MV64XXX_I2C_REG_DATA);
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writel(drv_data->cntl_bits,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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break;
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case MV64XXX_I2C_ACTION_SEND_DATA:
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writel(drv_data->msg->buf[drv_data->byte_posn++],
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drv_data->reg_base + MV64XXX_I2C_REG_DATA);
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writel(drv_data->cntl_bits,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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break;
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case MV64XXX_I2C_ACTION_RCV_DATA:
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drv_data->msg->buf[drv_data->byte_posn++] =
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readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
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writel(drv_data->cntl_bits,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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break;
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case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
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drv_data->msg->buf[drv_data->byte_posn++] =
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readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
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drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
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writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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drv_data->block = 0;
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wake_up_interruptible(&drv_data->waitq);
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break;
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case MV64XXX_I2C_ACTION_INVALID:
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default:
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dev_err(&drv_data->adapter.dev,
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"mv64xxx_i2c_do_action: Invalid action: %d\n",
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drv_data->action);
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drv_data->rc = -EIO;
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/* FALLTHRU */
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case MV64XXX_I2C_ACTION_SEND_STOP:
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drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
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writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
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drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
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drv_data->block = 0;
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wake_up_interruptible(&drv_data->waitq);
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break;
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}
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}
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static int
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mv64xxx_i2c_intr(int irq, void *dev_id)
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{
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struct mv64xxx_i2c_data *drv_data = dev_id;
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unsigned long flags;
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u32 status;
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int rc = IRQ_NONE;
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spin_lock_irqsave(&drv_data->lock, flags);
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while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
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MV64XXX_I2C_REG_CONTROL_IFLG) {
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status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
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mv64xxx_i2c_fsm(drv_data, status);
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mv64xxx_i2c_do_action(drv_data);
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rc = IRQ_HANDLED;
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}
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spin_unlock_irqrestore(&drv_data->lock, flags);
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return rc;
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}
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/*
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*****************************************************************************
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*
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* I2C Msg Execution Routines
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*
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*****************************************************************************
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*/
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static void
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mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
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struct i2c_msg *msg)
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{
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u32 dir = 0;
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drv_data->msg = msg;
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drv_data->byte_posn = 0;
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drv_data->bytes_left = msg->len;
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drv_data->aborting = 0;
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drv_data->rc = 0;
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drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
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MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
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if (msg->flags & I2C_M_RD)
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dir = 1;
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if (msg->flags & I2C_M_REV_DIR_ADDR)
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dir ^= 1;
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if (msg->flags & I2C_M_TEN) {
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drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
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drv_data->addr2 = (u32)msg->addr & 0xff;
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} else {
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drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
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drv_data->addr2 = 0;
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}
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}
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static void
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mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
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{
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long time_left;
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unsigned long flags;
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char abort = 0;
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time_left = wait_event_interruptible_timeout(drv_data->waitq,
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!drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));
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spin_lock_irqsave(&drv_data->lock, flags);
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if (!time_left) { /* Timed out */
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drv_data->rc = -ETIMEDOUT;
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abort = 1;
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} else if (time_left < 0) { /* Interrupted/Error */
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drv_data->rc = time_left; /* errno value */
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abort = 1;
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}
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if (abort && drv_data->block) {
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drv_data->aborting = 1;
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spin_unlock_irqrestore(&drv_data->lock, flags);
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time_left = wait_event_timeout(drv_data->waitq,
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!drv_data->block,
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msecs_to_jiffies(drv_data->adapter.timeout));
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if ((time_left <= 0) && drv_data->block) {
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drv_data->state = MV64XXX_I2C_STATE_IDLE;
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dev_err(&drv_data->adapter.dev,
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"mv64xxx: I2C bus locked, block: %d, "
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"time_left: %d\n", drv_data->block,
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(int)time_left);
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}
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} else
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spin_unlock_irqrestore(&drv_data->lock, flags);
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}
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static int
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mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
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{
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unsigned long flags;
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spin_lock_irqsave(&drv_data->lock, flags);
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mv64xxx_i2c_prepare_for_io(drv_data, msg);
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if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
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if (drv_data->msg->flags & I2C_M_RD) {
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/* No action to do, wait for slave to send a byte */
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drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
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drv_data->state =
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MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
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} else {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
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drv_data->state =
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MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
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drv_data->bytes_left--;
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}
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} else {
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drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
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drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
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}
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drv_data->block = 1;
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mv64xxx_i2c_do_action(drv_data);
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spin_unlock_irqrestore(&drv_data->lock, flags);
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mv64xxx_i2c_wait_for_completion(drv_data);
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return drv_data->rc;
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}
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/*
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*****************************************************************************
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*
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* I2C Core Support Routines (Interface to higher level I2C code)
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*
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*****************************************************************************
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*/
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static u32
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mv64xxx_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
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}
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static int
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mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
|
|
struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
|
|
int i, rc;
|
|
|
|
for (i=0; i<num; i++)
|
|
if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0)
|
|
return rc;
|
|
|
|
return num;
|
|
}
|
|
|
|
static const struct i2c_algorithm mv64xxx_i2c_algo = {
|
|
.master_xfer = mv64xxx_i2c_xfer,
|
|
.functionality = mv64xxx_i2c_functionality,
|
|
};
|
|
|
|
/*
|
|
*****************************************************************************
|
|
*
|
|
* Driver Interface & Early Init Routines
|
|
*
|
|
*****************************************************************************
|
|
*/
|
|
static void __devinit
|
|
mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
|
|
{
|
|
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
|
|
writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
|
|
drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
|
|
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
|
|
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
|
|
writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
|
|
drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
|
|
drv_data->state = MV64XXX_I2C_STATE_IDLE;
|
|
}
|
|
|
|
static int __devinit
|
|
mv64xxx_i2c_map_regs(struct platform_device *pd,
|
|
struct mv64xxx_i2c_data *drv_data)
|
|
{
|
|
struct resource *r;
|
|
|
|
if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) &&
|
|
request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE,
|
|
drv_data->adapter.name)) {
|
|
|
|
drv_data->reg_base = ioremap(r->start,
|
|
MV64XXX_I2C_REG_BLOCK_SIZE);
|
|
drv_data->reg_base_p = r->start;
|
|
} else
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __devexit
|
|
mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
|
|
{
|
|
if (drv_data->reg_base) {
|
|
iounmap(drv_data->reg_base);
|
|
release_mem_region(drv_data->reg_base_p,
|
|
MV64XXX_I2C_REG_BLOCK_SIZE);
|
|
}
|
|
|
|
drv_data->reg_base = NULL;
|
|
drv_data->reg_base_p = 0;
|
|
}
|
|
|
|
static int __devinit
|
|
mv64xxx_i2c_probe(struct platform_device *pd)
|
|
{
|
|
struct mv64xxx_i2c_data *drv_data;
|
|
struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
|
|
int rc;
|
|
|
|
if ((pd->id != 0) || !pdata)
|
|
return -ENODEV;
|
|
|
|
drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
|
|
if (!drv_data)
|
|
return -ENOMEM;
|
|
|
|
if (mv64xxx_i2c_map_regs(pd, drv_data)) {
|
|
rc = -ENODEV;
|
|
goto exit_kfree;
|
|
}
|
|
|
|
strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
|
|
sizeof(drv_data->adapter.name));
|
|
|
|
init_waitqueue_head(&drv_data->waitq);
|
|
spin_lock_init(&drv_data->lock);
|
|
|
|
drv_data->freq_m = pdata->freq_m;
|
|
drv_data->freq_n = pdata->freq_n;
|
|
drv_data->irq = platform_get_irq(pd, 0);
|
|
if (drv_data->irq < 0) {
|
|
rc = -ENXIO;
|
|
goto exit_unmap_regs;
|
|
}
|
|
drv_data->adapter.dev.parent = &pd->dev;
|
|
drv_data->adapter.id = I2C_HW_MV64XXX;
|
|
drv_data->adapter.algo = &mv64xxx_i2c_algo;
|
|
drv_data->adapter.owner = THIS_MODULE;
|
|
drv_data->adapter.class = I2C_CLASS_HWMON;
|
|
drv_data->adapter.timeout = pdata->timeout;
|
|
drv_data->adapter.retries = pdata->retries;
|
|
drv_data->adapter.nr = pd->id;
|
|
platform_set_drvdata(pd, drv_data);
|
|
i2c_set_adapdata(&drv_data->adapter, drv_data);
|
|
|
|
mv64xxx_i2c_hw_init(drv_data);
|
|
|
|
if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
|
|
MV64XXX_I2C_CTLR_NAME, drv_data)) {
|
|
dev_err(&drv_data->adapter.dev,
|
|
"mv64xxx: Can't register intr handler irq: %d\n",
|
|
drv_data->irq);
|
|
rc = -EINVAL;
|
|
goto exit_unmap_regs;
|
|
} else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
|
|
dev_err(&drv_data->adapter.dev,
|
|
"mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
|
|
goto exit_free_irq;
|
|
}
|
|
|
|
return 0;
|
|
|
|
exit_free_irq:
|
|
free_irq(drv_data->irq, drv_data);
|
|
exit_unmap_regs:
|
|
mv64xxx_i2c_unmap_regs(drv_data);
|
|
exit_kfree:
|
|
kfree(drv_data);
|
|
return rc;
|
|
}
|
|
|
|
static int __devexit
|
|
mv64xxx_i2c_remove(struct platform_device *dev)
|
|
{
|
|
struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
|
|
int rc;
|
|
|
|
rc = i2c_del_adapter(&drv_data->adapter);
|
|
free_irq(drv_data->irq, drv_data);
|
|
mv64xxx_i2c_unmap_regs(drv_data);
|
|
kfree(drv_data);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static struct platform_driver mv64xxx_i2c_driver = {
|
|
.probe = mv64xxx_i2c_probe,
|
|
.remove = mv64xxx_i2c_remove,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = MV64XXX_I2C_CTLR_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init
|
|
mv64xxx_i2c_init(void)
|
|
{
|
|
return platform_driver_register(&mv64xxx_i2c_driver);
|
|
}
|
|
|
|
static void __exit
|
|
mv64xxx_i2c_exit(void)
|
|
{
|
|
platform_driver_unregister(&mv64xxx_i2c_driver);
|
|
}
|
|
|
|
module_init(mv64xxx_i2c_init);
|
|
module_exit(mv64xxx_i2c_exit);
|
|
|
|
MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
|
|
MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
|
|
MODULE_LICENSE("GPL");
|