![Oleg Ryjkov](/assets/img/avatar_default.png)
Add an ability to utilize the internal SRAM buffer on ICH4 and newer host controllers to speed up execution of block operations. I've split the code so that it is more clear which block transaction is performed. First of all the host controller's type is identified. isich4 is set when we think that the controller has the internal buffer. Then, before every block transaction, if isich4 is set, we attempt to enable the E32B bit in SMBAUXCTL register. Signed-off-by: Oleg Ryjkov <olegr@google.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
686 lines
19 KiB
C
686 lines
19 KiB
C
/*
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i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
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monitoring
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Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
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Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
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<mdsxyz123@yahoo.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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SUPPORTED DEVICES PCI ID
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82801AA 2413
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82801AB 2423
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82801BA 2443
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82801CA/CAM 2483
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82801DB 24C3 (HW PEC supported)
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82801EB 24D3 (HW PEC supported)
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6300ESB 25A4
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ICH6 266A
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ICH7 27DA
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ESB2 269B
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ICH8 283E
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ICH9 2930
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This driver supports several versions of Intel's I/O Controller Hubs (ICH).
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For SMBus support, they are similar to the PIIX4 and are part
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of Intel's '810' and other chipsets.
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See the file Documentation/i2c/busses/i2c-i801 for details.
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I2C Block Read and Process Call are not supported.
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*/
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/* Note: we assume there can only be one I801, with one SMBus interface */
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <asm/io.h>
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/* I801 SMBus address offsets */
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#define SMBHSTSTS (0 + i801_smba)
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#define SMBHSTCNT (2 + i801_smba)
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#define SMBHSTCMD (3 + i801_smba)
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#define SMBHSTADD (4 + i801_smba)
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#define SMBHSTDAT0 (5 + i801_smba)
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#define SMBHSTDAT1 (6 + i801_smba)
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#define SMBBLKDAT (7 + i801_smba)
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#define SMBPEC (8 + i801_smba) /* ICH4 only */
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#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
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#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
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/* PCI Address Constants */
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#define SMBBAR 4
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#define SMBHSTCFG 0x040
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/* Host configuration bits for SMBHSTCFG */
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#define SMBHSTCFG_HST_EN 1
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#define SMBHSTCFG_SMB_SMI_EN 2
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#define SMBHSTCFG_I2C_EN 4
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/* Auxillary control register bits, ICH4+ only */
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#define SMBAUXCTL_CRC 1
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#define SMBAUXCTL_E32B 2
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/* kill bit for SMBHSTCNT */
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#define SMBHSTCNT_KILL 2
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/* Other settings */
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#define MAX_TIMEOUT 100
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#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
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/* I801 command constants */
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#define I801_QUICK 0x00
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#define I801_BYTE 0x04
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#define I801_BYTE_DATA 0x08
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#define I801_WORD_DATA 0x0C
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#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
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#define I801_BLOCK_DATA 0x14
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#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
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#define I801_BLOCK_LAST 0x34
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#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
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#define I801_START 0x40
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#define I801_PEC_EN 0x80 /* ICH4 only */
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/* I801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE 0x80
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#define SMBHSTSTS_INUSE_STS 0x40
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#define SMBHSTSTS_SMBALERT_STS 0x20
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#define SMBHSTSTS_FAILED 0x10
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#define SMBHSTSTS_BUS_ERR 0x08
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#define SMBHSTSTS_DEV_ERR 0x04
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#define SMBHSTSTS_INTR 0x02
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#define SMBHSTSTS_HOST_BUSY 0x01
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static unsigned long i801_smba;
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static unsigned char i801_original_hstcfg;
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static struct pci_driver i801_driver;
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static struct pci_dev *I801_dev;
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static int isich4;
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static int i801_transaction(int xact)
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{
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int temp;
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int result = 0;
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int timeout = 0;
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dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
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inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
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inb_p(SMBHSTDAT1));
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/* Make sure the SMBus host is ready to start transmitting */
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/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
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if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
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dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
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temp);
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outb_p(temp, SMBHSTSTS);
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if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
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dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
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return -1;
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} else {
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dev_dbg(&I801_dev->dev, "Successful!\n");
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}
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}
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/* the current contents of SMBHSTCNT can be overwritten, since PEC,
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* INTREN, SMBSCMD are passed in xact */
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outb_p(xact | I801_START, SMBHSTCNT);
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/* We will always wait for a fraction of a second! */
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do {
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msleep(1);
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temp = inb_p(SMBHSTSTS);
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} while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
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/* If the SMBus is still busy, we give up */
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if (timeout >= MAX_TIMEOUT) {
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dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
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result = -1;
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/* try to stop the current command */
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dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
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outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
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msleep(1);
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outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
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}
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if (temp & SMBHSTSTS_FAILED) {
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result = -1;
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dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
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}
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if (temp & SMBHSTSTS_BUS_ERR) {
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result = -1;
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dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
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"until next hard reset. (sorry!)\n");
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/* Clock stops and slave is stuck in mid-transmission */
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}
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if (temp & SMBHSTSTS_DEV_ERR) {
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result = -1;
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dev_dbg(&I801_dev->dev, "Error: no response!\n");
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}
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if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
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outb_p(inb(SMBHSTSTS), SMBHSTSTS);
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if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
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dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
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"(%02x)\n", temp);
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}
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dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
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inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
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inb_p(SMBHSTDAT1));
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return result;
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}
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/* wait for INTR bit as advised by Intel */
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static void i801_wait_hwpec(void)
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{
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int timeout = 0;
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int temp;
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do {
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msleep(1);
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temp = inb_p(SMBHSTSTS);
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} while ((!(temp & SMBHSTSTS_INTR))
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&& (timeout++ < MAX_TIMEOUT));
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if (timeout >= MAX_TIMEOUT) {
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dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
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}
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outb_p(temp, SMBHSTSTS);
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}
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static int i801_block_transaction_by_block(union i2c_smbus_data *data,
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char read_write, int hwpec)
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{
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int i, len;
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inb_p(SMBHSTCNT); /* reset the data buffer index */
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/* Use 32-byte buffer to process this transaction */
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if (read_write == I2C_SMBUS_WRITE) {
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len = data->block[0];
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outb_p(len, SMBHSTDAT0);
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for (i = 0; i < len; i++)
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outb_p(data->block[i+1], SMBBLKDAT);
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}
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if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
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I801_PEC_EN * hwpec))
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return -1;
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if (read_write == I2C_SMBUS_READ) {
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len = inb_p(SMBHSTDAT0);
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if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
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return -1;
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data->block[0] = len;
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for (i = 0; i < len; i++)
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data->block[i + 1] = inb_p(SMBBLKDAT);
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}
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return 0;
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}
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static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
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char read_write, int hwpec)
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{
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int i, len;
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int smbcmd;
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int temp;
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int result = 0;
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int timeout;
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unsigned char errmask;
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len = data->block[0];
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if (read_write == I2C_SMBUS_WRITE) {
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outb_p(len, SMBHSTDAT0);
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outb_p(data->block[1], SMBBLKDAT);
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}
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for (i = 1; i <= len; i++) {
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if (i == len && read_write == I2C_SMBUS_READ)
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smbcmd = I801_BLOCK_LAST;
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else
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smbcmd = I801_BLOCK_DATA;
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outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
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dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
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inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
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inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
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/* Make sure the SMBus host is ready to start transmitting */
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temp = inb_p(SMBHSTSTS);
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if (i == 1) {
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/* Erronenous conditions before transaction:
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* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
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errmask = 0x9f;
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} else {
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/* Erronenous conditions during transaction:
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* Failed, Bus_Err, Dev_Err, Intr */
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errmask = 0x1e;
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}
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if (temp & errmask) {
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dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
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"Resetting...\n", temp);
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outb_p(temp, SMBHSTSTS);
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if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
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dev_err(&I801_dev->dev,
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"Reset failed! (%02x)\n", temp);
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return -1;
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}
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if (i != 1)
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/* if die in middle of block transaction, fail */
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return -1;
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}
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if (i == 1)
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outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
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/* We will always wait for a fraction of a second! */
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timeout = 0;
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do {
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msleep(1);
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temp = inb_p(SMBHSTSTS);
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}
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while ((!(temp & SMBHSTSTS_BYTE_DONE))
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&& (timeout++ < MAX_TIMEOUT));
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/* If the SMBus is still busy, we give up */
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if (timeout >= MAX_TIMEOUT) {
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/* try to stop the current command */
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dev_dbg(&I801_dev->dev, "Terminating the current "
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"operation\n");
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outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
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msleep(1);
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outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
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SMBHSTCNT);
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result = -1;
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dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
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}
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if (temp & SMBHSTSTS_FAILED) {
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result = -1;
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dev_dbg(&I801_dev->dev,
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"Error: Failed bus transaction\n");
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} else if (temp & SMBHSTSTS_BUS_ERR) {
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result = -1;
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dev_err(&I801_dev->dev, "Bus collision!\n");
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} else if (temp & SMBHSTSTS_DEV_ERR) {
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result = -1;
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dev_dbg(&I801_dev->dev, "Error: no response!\n");
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}
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if (i == 1 && read_write == I2C_SMBUS_READ) {
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len = inb_p(SMBHSTDAT0);
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if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
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return -1;
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data->block[0] = len;
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}
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/* Retrieve/store value in SMBBLKDAT */
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if (read_write == I2C_SMBUS_READ)
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data->block[i] = inb_p(SMBBLKDAT);
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if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
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outb_p(data->block[i+1], SMBBLKDAT);
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if ((temp & 0x9e) != 0x00)
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outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
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if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
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dev_dbg(&I801_dev->dev,
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"Bad status (%02x) at end of transaction\n",
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temp);
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}
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dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
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inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
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inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
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if (result < 0)
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return result;
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}
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return result;
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}
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static int i801_set_block_buffer_mode(void)
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{
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outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
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if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
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return -1;
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return 0;
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}
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/* Block transaction function */
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static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
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int command, int hwpec)
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{
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int result = 0;
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unsigned char hostc;
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if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
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if (read_write == I2C_SMBUS_WRITE) {
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/* set I2C_EN bit in configuration register */
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pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
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pci_write_config_byte(I801_dev, SMBHSTCFG,
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hostc | SMBHSTCFG_I2C_EN);
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} else {
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dev_err(&I801_dev->dev,
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"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
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return -1;
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}
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}
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if (read_write == I2C_SMBUS_WRITE) {
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if (data->block[0] < 1)
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data->block[0] = 1;
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if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
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data->block[0] = I2C_SMBUS_BLOCK_MAX;
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} else {
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data->block[0] = 32; /* max for reads */
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}
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if (isich4 && i801_set_block_buffer_mode() == 0 )
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result = i801_block_transaction_by_block(data, read_write,
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hwpec);
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else
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result = i801_block_transaction_byte_by_byte(data, read_write,
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hwpec);
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if (result == 0 && hwpec)
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i801_wait_hwpec();
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if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
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/* restore saved configuration register value */
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pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
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}
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return result;
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}
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/* Return -1 on error. */
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static s32 i801_access(struct i2c_adapter * adap, u16 addr,
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unsigned short flags, char read_write, u8 command,
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int size, union i2c_smbus_data * data)
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{
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int hwpec;
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int block = 0;
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int ret, xact = 0;
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hwpec = isich4 && (flags & I2C_CLIENT_PEC)
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&& size != I2C_SMBUS_QUICK
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&& size != I2C_SMBUS_I2C_BLOCK_DATA;
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switch (size) {
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case I2C_SMBUS_QUICK:
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outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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SMBHSTADD);
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xact = I801_QUICK;
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break;
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case I2C_SMBUS_BYTE:
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outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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SMBHSTADD);
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if (read_write == I2C_SMBUS_WRITE)
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outb_p(command, SMBHSTCMD);
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xact = I801_BYTE;
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break;
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case I2C_SMBUS_BYTE_DATA:
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outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
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SMBHSTADD);
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outb_p(command, SMBHSTCMD);
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if (read_write == I2C_SMBUS_WRITE)
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outb_p(data->byte, SMBHSTDAT0);
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xact = I801_BYTE_DATA;
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break;
|
|
case I2C_SMBUS_WORD_DATA:
|
|
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
|
SMBHSTADD);
|
|
outb_p(command, SMBHSTCMD);
|
|
if (read_write == I2C_SMBUS_WRITE) {
|
|
outb_p(data->word & 0xff, SMBHSTDAT0);
|
|
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
|
|
}
|
|
xact = I801_WORD_DATA;
|
|
break;
|
|
case I2C_SMBUS_BLOCK_DATA:
|
|
case I2C_SMBUS_I2C_BLOCK_DATA:
|
|
outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
|
|
SMBHSTADD);
|
|
outb_p(command, SMBHSTCMD);
|
|
block = 1;
|
|
break;
|
|
case I2C_SMBUS_PROC_CALL:
|
|
default:
|
|
dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
|
|
return -1;
|
|
}
|
|
|
|
if (hwpec) /* enable/disable hardware PEC */
|
|
outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
|
|
else
|
|
outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
|
|
|
|
if(block)
|
|
ret = i801_block_transaction(data, read_write, size, hwpec);
|
|
else
|
|
ret = i801_transaction(xact | ENABLE_INT9);
|
|
|
|
/* Some BIOSes don't like it when PEC is enabled at reboot or resume
|
|
time, so we forcibly disable it after every transaction. Turn off
|
|
E32B for the same reason. */
|
|
if (hwpec)
|
|
outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
|
|
SMBAUXCTL);
|
|
|
|
if(block)
|
|
return ret;
|
|
if(ret)
|
|
return -1;
|
|
if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
|
|
return 0;
|
|
|
|
switch (xact & 0x7f) {
|
|
case I801_BYTE: /* Result put in SMBHSTDAT0 */
|
|
case I801_BYTE_DATA:
|
|
data->byte = inb_p(SMBHSTDAT0);
|
|
break;
|
|
case I801_WORD_DATA:
|
|
data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static u32 i801_func(struct i2c_adapter *adapter)
|
|
{
|
|
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
|
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
|
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
|
|
| (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
|
|
}
|
|
|
|
static const struct i2c_algorithm smbus_algorithm = {
|
|
.smbus_xfer = i801_access,
|
|
.functionality = i801_func,
|
|
};
|
|
|
|
static struct i2c_adapter i801_adapter = {
|
|
.owner = THIS_MODULE,
|
|
.id = I2C_HW_SMBUS_I801,
|
|
.class = I2C_CLASS_HWMON,
|
|
.algo = &smbus_algorithm,
|
|
};
|
|
|
|
static struct pci_device_id i801_ids[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
|
|
{ 0, }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE (pci, i801_ids);
|
|
|
|
static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
unsigned char temp;
|
|
int err;
|
|
|
|
I801_dev = dev;
|
|
switch (dev->device) {
|
|
case PCI_DEVICE_ID_INTEL_82801DB_3:
|
|
case PCI_DEVICE_ID_INTEL_82801EB_3:
|
|
case PCI_DEVICE_ID_INTEL_ESB_4:
|
|
case PCI_DEVICE_ID_INTEL_ICH6_16:
|
|
case PCI_DEVICE_ID_INTEL_ICH7_17:
|
|
case PCI_DEVICE_ID_INTEL_ESB2_17:
|
|
case PCI_DEVICE_ID_INTEL_ICH8_5:
|
|
case PCI_DEVICE_ID_INTEL_ICH9_6:
|
|
isich4 = 1;
|
|
break;
|
|
default:
|
|
isich4 = 0;
|
|
}
|
|
|
|
err = pci_enable_device(dev);
|
|
if (err) {
|
|
dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
|
|
err);
|
|
goto exit;
|
|
}
|
|
|
|
/* Determine the address of the SMBus area */
|
|
i801_smba = pci_resource_start(dev, SMBBAR);
|
|
if (!i801_smba) {
|
|
dev_err(&dev->dev, "SMBus base address uninitialized, "
|
|
"upgrade BIOS\n");
|
|
err = -ENODEV;
|
|
goto exit;
|
|
}
|
|
|
|
err = pci_request_region(dev, SMBBAR, i801_driver.name);
|
|
if (err) {
|
|
dev_err(&dev->dev, "Failed to request SMBus region "
|
|
"0x%lx-0x%Lx\n", i801_smba,
|
|
(unsigned long long)pci_resource_end(dev, SMBBAR));
|
|
goto exit;
|
|
}
|
|
|
|
pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
|
|
i801_original_hstcfg = temp;
|
|
temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
|
|
if (!(temp & SMBHSTCFG_HST_EN)) {
|
|
dev_info(&dev->dev, "Enabling SMBus device\n");
|
|
temp |= SMBHSTCFG_HST_EN;
|
|
}
|
|
pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
|
|
|
|
if (temp & SMBHSTCFG_SMB_SMI_EN)
|
|
dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
|
|
else
|
|
dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
|
|
|
|
/* set up the sysfs linkage to our parent device */
|
|
i801_adapter.dev.parent = &dev->dev;
|
|
|
|
snprintf(i801_adapter.name, sizeof(i801_adapter.name),
|
|
"SMBus I801 adapter at %04lx", i801_smba);
|
|
err = i2c_add_adapter(&i801_adapter);
|
|
if (err) {
|
|
dev_err(&dev->dev, "Failed to add SMBus adapter\n");
|
|
goto exit_release;
|
|
}
|
|
return 0;
|
|
|
|
exit_release:
|
|
pci_release_region(dev, SMBBAR);
|
|
exit:
|
|
return err;
|
|
}
|
|
|
|
static void __devexit i801_remove(struct pci_dev *dev)
|
|
{
|
|
i2c_del_adapter(&i801_adapter);
|
|
pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
|
|
pci_release_region(dev, SMBBAR);
|
|
/*
|
|
* do not call pci_disable_device(dev) since it can cause hard hangs on
|
|
* some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
|
|
*/
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
|
|
{
|
|
pci_save_state(dev);
|
|
pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
|
|
pci_set_power_state(dev, pci_choose_state(dev, mesg));
|
|
return 0;
|
|
}
|
|
|
|
static int i801_resume(struct pci_dev *dev)
|
|
{
|
|
pci_set_power_state(dev, PCI_D0);
|
|
pci_restore_state(dev);
|
|
return pci_enable_device(dev);
|
|
}
|
|
#else
|
|
#define i801_suspend NULL
|
|
#define i801_resume NULL
|
|
#endif
|
|
|
|
static struct pci_driver i801_driver = {
|
|
.name = "i801_smbus",
|
|
.id_table = i801_ids,
|
|
.probe = i801_probe,
|
|
.remove = __devexit_p(i801_remove),
|
|
.suspend = i801_suspend,
|
|
.resume = i801_resume,
|
|
};
|
|
|
|
static int __init i2c_i801_init(void)
|
|
{
|
|
return pci_register_driver(&i801_driver);
|
|
}
|
|
|
|
static void __exit i2c_i801_exit(void)
|
|
{
|
|
pci_unregister_driver(&i801_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
|
|
"Philip Edelbrock <phil@netroedge.com>, "
|
|
"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
|
|
MODULE_DESCRIPTION("I801 SMBus driver");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
module_init(i2c_i801_init);
|
|
module_exit(i2c_i801_exit);
|