454 lines
12 KiB
C
454 lines
12 KiB
C
/*
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module/mite.h
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Hardware driver for NI Mite PCI interface chip
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COMEDI - Linux Control and Measurement Device Interface
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Copyright (C) 1999 David A. Schleef <ds@schleef.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _MITE_H_
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#define _MITE_H_
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#include <linux/pci.h>
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#include "../comedidev.h"
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#define PCI_VENDOR_ID_NATINST 0x1093
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/* #define DEBUG_MITE */
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#define PCIMIO_COMPAT
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#ifdef DEBUG_MITE
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#define MDPRINTK(format, args...) printk(format , ## args)
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#else
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#define MDPRINTK(format, args...)
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#endif
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#define MAX_MITE_DMA_CHANNELS 8
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struct mite_dma_descriptor {
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u32 count;
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u32 addr;
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u32 next;
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u32 dar;
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};
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struct mite_dma_descriptor_ring {
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struct device *hw_dev;
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unsigned int n_links;
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struct mite_dma_descriptor *descriptors;
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dma_addr_t descriptors_dma_addr;
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};
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struct mite_channel {
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struct mite_struct *mite;
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unsigned channel;
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int dir;
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int done;
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struct mite_dma_descriptor_ring *ring;
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};
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struct mite_struct {
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struct mite_struct *next;
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int used;
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struct pci_dev *pcidev;
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resource_size_t mite_phys_addr;
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void *mite_io_addr;
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resource_size_t daq_phys_addr;
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void *daq_io_addr;
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struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
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short channel_allocated[MAX_MITE_DMA_CHANNELS];
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int num_channels;
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unsigned fifo_size;
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spinlock_t lock;
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};
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static inline struct mite_dma_descriptor_ring *mite_alloc_ring(struct
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mite_struct *mite)
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{
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struct mite_dma_descriptor_ring *ring =
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kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
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if (ring == NULL)
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return ring;
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ring->hw_dev = get_device(&mite->pcidev->dev);
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if (ring->hw_dev == NULL) {
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kfree(ring);
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return NULL;
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}
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ring->n_links = 0;
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ring->descriptors = NULL;
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ring->descriptors_dma_addr = 0;
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return ring;
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};
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static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
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{
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if (ring) {
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if (ring->descriptors) {
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dma_free_coherent(ring->hw_dev,
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ring->n_links *
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sizeof(struct mite_dma_descriptor),
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ring->descriptors, ring->descriptors_dma_addr);
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}
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put_device(ring->hw_dev);
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kfree(ring);
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}
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};
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extern struct mite_struct *mite_devices;
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static inline unsigned int mite_irq(struct mite_struct *mite)
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{
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return mite->pcidev->irq;
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};
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static inline unsigned int mite_device_id(struct mite_struct *mite)
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{
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return mite->pcidev->device;
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};
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void mite_init(void);
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void mite_cleanup(void);
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int mite_setup(struct mite_struct *mite);
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int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
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void mite_unsetup(struct mite_struct *mite);
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void mite_list_devices(void);
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struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
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struct mite_dma_descriptor_ring *ring, unsigned min_channel,
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unsigned max_channel);
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static inline struct mite_channel *mite_request_channel(struct mite_struct
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*mite, struct mite_dma_descriptor_ring *ring)
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{
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return mite_request_channel_in_range(mite, ring, 0,
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mite->num_channels - 1);
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}
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void mite_release_channel(struct mite_channel *mite_chan);
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unsigned mite_dma_tcr(struct mite_channel *mite_chan);
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void mite_dma_arm(struct mite_channel *mite_chan);
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void mite_dma_disarm(struct mite_channel *mite_chan);
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int mite_sync_input_dma(struct mite_channel *mite_chan, struct comedi_async * async);
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int mite_sync_output_dma(struct mite_channel *mite_chan, struct comedi_async * async);
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u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
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u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
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u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
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u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
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u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
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unsigned mite_get_status(struct mite_channel *mite_chan);
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int mite_done(struct mite_channel *mite_chan);
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#if 0
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unsigned long mite_ll_from_kvmem(struct mite_struct *mite, struct comedi_async * async,
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int len);
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void mite_setregs(struct mite_struct *mite, unsigned long ll_start, int chan,
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int dir);
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#endif
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void mite_prep_dma(struct mite_channel *mite_chan,
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unsigned int num_device_bits, unsigned int num_memory_bits);
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int mite_buf_change(struct mite_dma_descriptor_ring *ring,
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struct comedi_async *async);
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#ifdef DEBUG_MITE
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void mite_print_chsr(unsigned int chsr);
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void mite_dump_regs(struct mite_channel *mite_chan);
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#endif
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static inline int CHAN_OFFSET(int channel)
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{
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return 0x500 + 0x100 * channel;
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};
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enum mite_registers {
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/* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
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written and read back. The bits 0x1f always read as 1.
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The rest always read as zero. */
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MITE_UNKNOWN_DMA_BURST_REG = 0x28,
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MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
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MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
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MITE_IODWCR_1 = 0xf4,
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MITE_PCI_CONFIG_OFFSET = 0x300,
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MITE_CSIGR = 0x460 /* chip signature */
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};
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static inline int MITE_CHOR(int channel) /* channel operation */
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{
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return CHAN_OFFSET(channel) + 0x0;
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};
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static inline int MITE_CHCR(int channel) /* channel control */
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{
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return CHAN_OFFSET(channel) + 0x4;
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};
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static inline int MITE_TCR(int channel) /* transfer count */
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{
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return CHAN_OFFSET(channel) + 0x8;
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};
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static inline int MITE_MCR(int channel) /* memory configuration */
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{
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return CHAN_OFFSET(channel) + 0xc;
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};
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static inline int MITE_MAR(int channel) /* memory address */
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{
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return CHAN_OFFSET(channel) + 0x10;
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};
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static inline int MITE_DCR(int channel) /* device configuration */
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{
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return CHAN_OFFSET(channel) + 0x14;
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};
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static inline int MITE_DAR(int channel) /* device address */
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{
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return CHAN_OFFSET(channel) + 0x18;
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};
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static inline int MITE_LKCR(int channel) /* link configuration */
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{
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return CHAN_OFFSET(channel) + 0x1c;
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};
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static inline int MITE_LKAR(int channel) /* link address */
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{
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return CHAN_OFFSET(channel) + 0x20;
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};
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static inline int MITE_LLKAR(int channel) /* see mite section of tnt5002 manual */
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{
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return CHAN_OFFSET(channel) + 0x24;
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};
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static inline int MITE_BAR(int channel) /* base address */
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{
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return CHAN_OFFSET(channel) + 0x28;
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};
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static inline int MITE_BCR(int channel) /* base count */
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{
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return CHAN_OFFSET(channel) + 0x2c;
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};
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static inline int MITE_SAR(int channel) /* ? address */
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{
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return CHAN_OFFSET(channel) + 0x30;
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};
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static inline int MITE_WSCR(int channel) /* ? */
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{
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return CHAN_OFFSET(channel) + 0x34;
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};
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static inline int MITE_WSER(int channel) /* ? */
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{
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return CHAN_OFFSET(channel) + 0x38;
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};
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static inline int MITE_CHSR(int channel) /* channel status */
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{
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return CHAN_OFFSET(channel) + 0x3c;
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};
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static inline int MITE_FCR(int channel) /* fifo count */
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{
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return CHAN_OFFSET(channel) + 0x40;
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};
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enum MITE_IODWBSR_bits {
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WENAB = 0x80, /* window enable */
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};
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static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
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{
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unsigned order = 0;
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while (size >>= 1)
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++order;
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BUG_ON(order < 1);
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return (order - 1) & 0x1f;
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}
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enum MITE_UNKNOWN_DMA_BURST_bits {
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UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
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};
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static inline int mite_csigr_version(u32 csigr_bits)
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{
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return csigr_bits & 0xf;
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};
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static inline int mite_csigr_type(u32 csigr_bits)
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{ /* original mite = 0, minimite = 1 */
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return (csigr_bits >> 4) & 0xf;
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};
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static inline int mite_csigr_mmode(u32 csigr_bits)
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{ /* mite mode, minimite = 1 */
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return (csigr_bits >> 8) & 0x3;
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};
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static inline int mite_csigr_imode(u32 csigr_bits)
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{ /* cpu port interface mode, pci = 0x3 */
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return (csigr_bits >> 12) & 0x3;
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};
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static inline int mite_csigr_dmac(u32 csigr_bits)
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{ /* number of dma channels */
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return (csigr_bits >> 16) & 0xf;
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};
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static inline int mite_csigr_wpdep(u32 csigr_bits)
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{ /* write post fifo depth */
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unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
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if (wpdep_bits == 0)
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return 0;
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else
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return 1 << (wpdep_bits - 1);
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};
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static inline int mite_csigr_wins(u32 csigr_bits)
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{
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return (csigr_bits >> 24) & 0x1f;
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};
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static inline int mite_csigr_iowins(u32 csigr_bits)
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{ /* number of io windows */
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return (csigr_bits >> 29) & 0x7;
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};
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enum MITE_MCR_bits {
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MCRPON = 0,
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};
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enum MITE_DCR_bits {
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DCR_NORMAL = (1 << 29),
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DCRPON = 0,
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};
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enum MITE_CHOR_bits {
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CHOR_DMARESET = (1 << 31),
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CHOR_SET_SEND_TC = (1 << 11),
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CHOR_CLR_SEND_TC = (1 << 10),
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CHOR_SET_LPAUSE = (1 << 9),
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CHOR_CLR_LPAUSE = (1 << 8),
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CHOR_CLRDONE = (1 << 7),
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CHOR_CLRRB = (1 << 6),
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CHOR_CLRLC = (1 << 5),
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CHOR_FRESET = (1 << 4),
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CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
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CHOR_STOP = (1 << 2), /* stop after emptying fifo */
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CHOR_CONT = (1 << 1),
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CHOR_START = (1 << 0),
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CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
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};
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enum MITE_CHCR_bits {
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CHCR_SET_DMA_IE = (1 << 31),
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CHCR_CLR_DMA_IE = (1 << 30),
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CHCR_SET_LINKP_IE = (1 << 29),
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CHCR_CLR_LINKP_IE = (1 << 28),
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CHCR_SET_SAR_IE = (1 << 27),
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CHCR_CLR_SAR_IE = (1 << 26),
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CHCR_SET_DONE_IE = (1 << 25),
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CHCR_CLR_DONE_IE = (1 << 24),
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CHCR_SET_MRDY_IE = (1 << 23),
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CHCR_CLR_MRDY_IE = (1 << 22),
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CHCR_SET_DRDY_IE = (1 << 21),
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CHCR_CLR_DRDY_IE = (1 << 20),
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CHCR_SET_LC_IE = (1 << 19),
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CHCR_CLR_LC_IE = (1 << 18),
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CHCR_SET_CONT_RB_IE = (1 << 17),
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CHCR_CLR_CONT_RB_IE = (1 << 16),
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CHCR_FIFODIS = (1 << 15),
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CHCR_FIFO_ON = 0,
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CHCR_BURSTEN = (1 << 14),
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CHCR_NO_BURSTEN = 0,
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CHCR_BYTE_SWAP_DEVICE = (1 << 6),
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CHCR_BYTE_SWAP_MEMORY = (1 << 4),
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CHCR_DIR = (1 << 3),
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CHCR_DEV_TO_MEM = CHCR_DIR,
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CHCR_MEM_TO_DEV = 0,
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CHCR_NORMAL = (0 << 0),
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CHCR_CONTINUE = (1 << 0),
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CHCR_RINGBUFF = (2 << 0),
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CHCR_LINKSHORT = (4 << 0),
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CHCR_LINKLONG = (5 << 0),
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CHCRPON =
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(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
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CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
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CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
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};
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enum ConfigRegister_bits {
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CR_REQS_MASK = 0x7 << 16,
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CR_ASEQDONT = 0x0 << 10,
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CR_ASEQUP = 0x1 << 10,
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CR_ASEQDOWN = 0x2 << 10,
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CR_ASEQ_MASK = 0x3 << 10,
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CR_PSIZE8 = (1 << 8),
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CR_PSIZE16 = (2 << 8),
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CR_PSIZE32 = (3 << 8),
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CR_PORTCPU = (0 << 6),
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CR_PORTIO = (1 << 6),
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CR_PORTVXI = (2 << 6),
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CR_PORTMXI = (3 << 6),
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CR_AMDEVICE = (1 << 0),
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};
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static inline int CR_REQS(int source)
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{
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return (source & 0x7) << 16;
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};
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static inline int CR_REQSDRQ(unsigned drq_line)
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{
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/* This also works on m-series when
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using channels (drq_line) 4 or 5. */
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return CR_REQS((drq_line & 0x3) | 0x4);
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}
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static inline int CR_RL(unsigned int retry_limit)
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{
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int value = 0;
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while (retry_limit) {
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retry_limit >>= 1;
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value++;
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}
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if (value > 0x7)
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printk("comedi: bug! retry_limit too large\n");
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return (value & 0x7) << 21;
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}
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enum CHSR_bits {
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CHSR_INT = (1 << 31),
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CHSR_LPAUSES = (1 << 29),
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CHSR_SARS = (1 << 27),
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CHSR_DONE = (1 << 25),
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CHSR_MRDY = (1 << 23),
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CHSR_DRDY = (1 << 21),
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CHSR_LINKC = (1 << 19),
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CHSR_CONTS_RB = (1 << 17),
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CHSR_ERROR = (1 << 15),
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CHSR_SABORT = (1 << 14),
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CHSR_HABORT = (1 << 13),
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CHSR_STOPS = (1 << 12),
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CHSR_OPERR_mask = (3 << 10),
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CHSR_OPERR_NOERROR = (0 << 10),
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CHSR_OPERR_FIFOERROR = (1 << 10),
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CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
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CHSR_XFERR = (1 << 9),
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CHSR_END = (1 << 8),
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CHSR_DRQ1 = (1 << 7),
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CHSR_DRQ0 = (1 << 6),
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CHSR_LxERR_mask = (3 << 4),
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CHSR_LBERR = (1 << 4),
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CHSR_LRERR = (2 << 4),
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CHSR_LOERR = (3 << 4),
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CHSR_MxERR_mask = (3 << 2),
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CHSR_MBERR = (1 << 2),
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CHSR_MRERR = (2 << 2),
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CHSR_MOERR = (3 << 2),
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CHSR_DxERR_mask = (3 << 0),
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CHSR_DBERR = (1 << 0),
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CHSR_DRERR = (2 << 0),
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CHSR_DOERR = (3 << 0),
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};
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static inline void mite_dma_reset(struct mite_channel *mite_chan)
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{
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writel(CHOR_DMARESET | CHOR_FRESET,
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mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
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};
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#endif
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