![Chris Lalancette](/assets/img/avatar_default.png)
The current implementation of get_user_desc() sign extends the return value because of integer promotion rules. For the most part, this doesn't matter, because the top bit of base2 is usually 0. If, however, that bit is 1, then the entire value will be 0xffff... which is probably not what the caller intended. This patch casts the entire thing to unsigned before returning, which generates almost the same assembly as the current code but replaces the final "cltq" (sign extend) with a "mov %eax %eax" (zero-extend). This fixes booting certain guests under KVM. Signed-off-by: Chris Lalancette <clalance@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
396 lines
9.8 KiB
C
396 lines
9.8 KiB
C
#ifndef _ASM_X86_DESC_H
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#define _ASM_X86_DESC_H
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#include <asm/desc_defs.h>
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#include <asm/ldt.h>
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#include <asm/mmu.h>
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#include <linux/smp.h>
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static inline void fill_ldt(struct desc_struct *desc,
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const struct user_desc *info)
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{
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desc->limit0 = info->limit & 0x0ffff;
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desc->base0 = info->base_addr & 0x0000ffff;
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desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
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desc->type = (info->read_exec_only ^ 1) << 1;
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desc->type |= info->contents << 2;
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desc->s = 1;
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desc->dpl = 0x3;
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desc->p = info->seg_not_present ^ 1;
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desc->limit = (info->limit & 0xf0000) >> 16;
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desc->avl = info->useable;
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desc->d = info->seg_32bit;
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desc->g = info->limit_in_pages;
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desc->base2 = (info->base_addr & 0xff000000) >> 24;
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/*
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* Don't allow setting of the lm bit. It is useless anyway
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* because 64bit system calls require __USER_CS:
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*/
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desc->l = 0;
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}
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extern struct desc_ptr idt_descr;
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extern gate_desc idt_table[];
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struct gdt_page {
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struct desc_struct gdt[GDT_ENTRIES];
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} __attribute__((aligned(PAGE_SIZE)));
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DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
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static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
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{
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return per_cpu(gdt_page, cpu).gdt;
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}
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#ifdef CONFIG_X86_64
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static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
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unsigned dpl, unsigned ist, unsigned seg)
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{
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gate->offset_low = PTR_LOW(func);
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gate->segment = __KERNEL_CS;
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gate->ist = ist;
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gate->p = 1;
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gate->dpl = dpl;
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gate->zero0 = 0;
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gate->zero1 = 0;
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gate->type = type;
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gate->offset_middle = PTR_MIDDLE(func);
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gate->offset_high = PTR_HIGH(func);
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}
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#else
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static inline void pack_gate(gate_desc *gate, unsigned char type,
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unsigned long base, unsigned dpl, unsigned flags,
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unsigned short seg)
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{
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gate->a = (seg << 16) | (base & 0xffff);
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gate->b = (base & 0xffff0000) |
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(((0x80 | type | (dpl << 5)) & 0xff) << 8);
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}
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#endif
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static inline int desc_empty(const void *ptr)
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{
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const u32 *desc = ptr;
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return !(desc[0] | desc[1]);
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define load_TR_desc() native_load_tr_desc()
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#define load_gdt(dtr) native_load_gdt(dtr)
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#define load_idt(dtr) native_load_idt(dtr)
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#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
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#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
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#define store_gdt(dtr) native_store_gdt(dtr)
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#define store_idt(dtr) native_store_idt(dtr)
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#define store_tr(tr) (tr = native_store_tr())
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#define load_TLS(t, cpu) native_load_tls(t, cpu)
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#define set_ldt native_set_ldt
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#define write_ldt_entry(dt, entry, desc) \
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native_write_ldt_entry(dt, entry, desc)
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#define write_gdt_entry(dt, entry, desc, type) \
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native_write_gdt_entry(dt, entry, desc, type)
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#define write_idt_entry(dt, entry, g) \
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native_write_idt_entry(dt, entry, g)
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static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
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{
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}
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static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
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{
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}
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#endif /* CONFIG_PARAVIRT */
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#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
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static inline void native_write_idt_entry(gate_desc *idt, int entry,
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const gate_desc *gate)
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{
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memcpy(&idt[entry], gate, sizeof(*gate));
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}
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static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
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const void *desc)
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{
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memcpy(&ldt[entry], desc, 8);
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}
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static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
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const void *desc, int type)
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{
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unsigned int size;
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switch (type) {
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case DESC_TSS:
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size = sizeof(tss_desc);
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break;
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case DESC_LDT:
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size = sizeof(ldt_desc);
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break;
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default:
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size = sizeof(struct desc_struct);
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break;
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}
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memcpy(&gdt[entry], desc, size);
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}
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static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
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unsigned long limit, unsigned char type,
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unsigned char flags)
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{
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desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
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desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
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(limit & 0x000f0000) | ((type & 0xff) << 8) |
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((flags & 0xf) << 20);
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desc->p = 1;
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}
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static inline void set_tssldt_descriptor(void *d, unsigned long addr,
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unsigned type, unsigned size)
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{
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#ifdef CONFIG_X86_64
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struct ldttss_desc64 *desc = d;
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memset(desc, 0, sizeof(*desc));
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desc->limit0 = size & 0xFFFF;
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desc->base0 = PTR_LOW(addr);
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desc->base1 = PTR_MIDDLE(addr) & 0xFF;
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desc->type = type;
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desc->p = 1;
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desc->limit1 = (size >> 16) & 0xF;
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desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
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desc->base3 = PTR_HIGH(addr);
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#else
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pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
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#endif
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}
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static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
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{
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struct desc_struct *d = get_cpu_gdt_table(cpu);
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tss_desc tss;
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/*
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* sizeof(unsigned long) coming from an extra "long" at the end
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* of the iobitmap. See tss_struct definition in processor.h
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*
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* -1? seg base+limit should be pointing to the address of the
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* last valid byte
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*/
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set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
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IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
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sizeof(unsigned long) - 1);
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write_gdt_entry(d, entry, &tss, DESC_TSS);
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}
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#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
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static inline void native_set_ldt(const void *addr, unsigned int entries)
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{
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if (likely(entries == 0))
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asm volatile("lldt %w0"::"q" (0));
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else {
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unsigned cpu = smp_processor_id();
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ldt_desc ldt;
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set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
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entries * LDT_ENTRY_SIZE - 1);
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write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
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&ldt, DESC_LDT);
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asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
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}
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}
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static inline void native_load_tr_desc(void)
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{
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asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
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}
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static inline void native_load_gdt(const struct desc_ptr *dtr)
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{
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asm volatile("lgdt %0"::"m" (*dtr));
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}
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static inline void native_load_idt(const struct desc_ptr *dtr)
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{
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asm volatile("lidt %0"::"m" (*dtr));
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}
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static inline void native_store_gdt(struct desc_ptr *dtr)
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{
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asm volatile("sgdt %0":"=m" (*dtr));
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}
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static inline void native_store_idt(struct desc_ptr *dtr)
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{
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asm volatile("sidt %0":"=m" (*dtr));
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}
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static inline unsigned long native_store_tr(void)
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{
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unsigned long tr;
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asm volatile("str %0":"=r" (tr));
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return tr;
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}
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static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
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{
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unsigned int i;
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struct desc_struct *gdt = get_cpu_gdt_table(cpu);
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for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
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gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
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}
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#define _LDT_empty(info) \
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((info)->base_addr == 0 && \
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(info)->limit == 0 && \
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(info)->contents == 0 && \
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(info)->read_exec_only == 1 && \
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(info)->seg_32bit == 0 && \
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(info)->limit_in_pages == 0 && \
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(info)->seg_not_present == 1 && \
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(info)->useable == 0)
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#ifdef CONFIG_X86_64
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#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
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#else
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#define LDT_empty(info) (_LDT_empty(info))
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#endif
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static inline void clear_LDT(void)
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{
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set_ldt(NULL, 0);
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}
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/*
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* load one particular LDT into the current CPU
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*/
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static inline void load_LDT_nolock(mm_context_t *pc)
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{
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set_ldt(pc->ldt, pc->size);
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}
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static inline void load_LDT(mm_context_t *pc)
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{
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preempt_disable();
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load_LDT_nolock(pc);
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preempt_enable();
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}
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static inline unsigned long get_desc_base(const struct desc_struct *desc)
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{
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return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
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}
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static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
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{
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desc->base0 = base & 0xffff;
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desc->base1 = (base >> 16) & 0xff;
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desc->base2 = (base >> 24) & 0xff;
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}
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static inline unsigned long get_desc_limit(const struct desc_struct *desc)
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{
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return desc->limit0 | (desc->limit << 16);
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}
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static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
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{
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desc->limit0 = limit & 0xffff;
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desc->limit = (limit >> 16) & 0xf;
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}
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static inline void _set_gate(int gate, unsigned type, void *addr,
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unsigned dpl, unsigned ist, unsigned seg)
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{
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gate_desc s;
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pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
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/*
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* does not need to be atomic because it is only done once at
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* setup time
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*/
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write_idt_entry(idt_table, gate, &s);
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}
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/*
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* This needs to use 'idt_table' rather than 'idt', and
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* thus use the _nonmapped_ version of the IDT, as the
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* Pentium F0 0F bugfix can have resulted in the mapped
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* IDT being write-protected.
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*/
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static inline void set_intr_gate(unsigned int n, void *addr)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
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}
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extern int first_system_vector;
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/* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
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extern unsigned long used_vectors[];
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static inline void alloc_system_vector(int vector)
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{
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if (!test_bit(vector, used_vectors)) {
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set_bit(vector, used_vectors);
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if (first_system_vector > vector)
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first_system_vector = vector;
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} else
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BUG();
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}
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static inline void alloc_intr_gate(unsigned int n, void *addr)
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{
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alloc_system_vector(n);
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set_intr_gate(n, addr);
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}
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/*
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* This routine sets up an interrupt gate at directory privilege level 3.
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*/
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static inline void set_system_intr_gate(unsigned int n, void *addr)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
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}
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static inline void set_system_trap_gate(unsigned int n, void *addr)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
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}
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static inline void set_trap_gate(unsigned int n, void *addr)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
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}
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static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
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}
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static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
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}
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static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
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{
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BUG_ON((unsigned)n > 0xFF);
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_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
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}
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#endif /* _ASM_X86_DESC_H */
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