![Joe Perches](/assets/img/avatar_default.png)
Found these while looking at printk uses. Add missing newlines to dev_<level> uses Add missing KERN_<level> prefixes to multiline dev_<level>s Fixed a wierd->weird spelling typo Added a newline to a printk Signed-off-by: Joe Perches <joe@perches.com> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Jens Axboe <jens.axboe@oracle.com> Cc: Mark M. Hoffman <mhoffman@lightlink.com> Cc: Roland Dreier <rolandd@cisco.com> Cc: Tilman Schmidt <tilman@imap.cc> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jeff Garzik <jeff@garzik.org> Cc: Stephen Hemminger <shemminger@linux-foundation.org> Cc: Greg KH <greg@kroah.com> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: David Brownell <david-b@pacbell.net> Cc: James Smart <James.Smart@Emulex.Com> Cc: Andrew Vasquez <andrew.vasquez@qlogic.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Jaroslav Kysela <perex@suse.cz> Cc: Takashi Iwai <tiwai@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
704 lines
19 KiB
C
704 lines
19 KiB
C
/*
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* Provides I2C support for Philips PNX010x/PNX4008 boards.
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*
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* Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
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* Vitaly Wool <vwool@ru.mvista.com>
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*
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* 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/timer.h>
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/i2c-pnx.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#define I2C_PNX_TIMEOUT 10 /* msec */
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#define I2C_PNX_SPEED_KHZ 100
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#define I2C_PNX_REGION_SIZE 0x100
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#define PNX_DEFAULT_FREQ 13 /* MHz */
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static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
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{
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while (timeout > 0 &&
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(ioread32(I2C_REG_STS(data)) & mstatus_active)) {
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mdelay(1);
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timeout--;
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}
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return (timeout <= 0);
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}
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static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
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{
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while (timeout > 0 &&
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(ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
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mdelay(1);
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timeout--;
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}
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return (timeout <= 0);
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}
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static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap)
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{
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struct i2c_pnx_algo_data *data = adap->algo_data;
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struct timer_list *timer = &data->mif.timer;
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int expires = I2C_PNX_TIMEOUT / (1000 / HZ);
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del_timer_sync(timer);
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dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n",
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jiffies, expires);
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timer->expires = jiffies + expires;
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timer->data = (unsigned long)adap;
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add_timer(timer);
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}
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/**
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* i2c_pnx_start - start a device
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* @slave_addr: slave address
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* @adap: pointer to adapter structure
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*
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* Generate a START signal in the desired mode.
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*/
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static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap)
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{
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __FUNCTION__,
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slave_addr, alg_data->mif.mode);
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/* Check for 7 bit slave addresses only */
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if (slave_addr & ~0x7f) {
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dev_err(&adap->dev, "%s: Invalid slave address %x. "
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"Only 7-bit addresses are supported\n",
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adap->name, slave_addr);
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return -EINVAL;
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}
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/* First, make sure bus is idle */
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if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
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/* Somebody else is monopolizing the bus */
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dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, "
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"cntrl = %x, stat = %x\n",
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adap->name, slave_addr,
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ioread32(I2C_REG_CTL(alg_data)),
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ioread32(I2C_REG_STS(alg_data)));
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return -EBUSY;
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} else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
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/* Sorry, we lost the bus */
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dev_err(&adap->dev, "%s: Arbitration failure. "
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"Slave addr = %02x\n", adap->name, slave_addr);
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return -EIO;
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}
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/*
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* OK, I2C is enabled and we have the bus.
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* Clear the current TDI and AFI status flags.
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*/
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iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
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I2C_REG_STS(alg_data));
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dev_dbg(&adap->dev, "%s(): sending %#x\n", __FUNCTION__,
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(slave_addr << 1) | start_bit | alg_data->mif.mode);
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/* Write the slave address, START bit and R/W bit */
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iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
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I2C_REG_TX(alg_data));
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dev_dbg(&adap->dev, "%s(): exit\n", __FUNCTION__);
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return 0;
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}
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/**
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* i2c_pnx_stop - stop a device
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* @adap: pointer to I2C adapter structure
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*
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* Generate a STOP signal to terminate the master transaction.
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*/
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static void i2c_pnx_stop(struct i2c_adapter *adap)
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{
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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/* Only 1 msec max timeout due to interrupt context */
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long timeout = 1000;
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dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
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/* Write a STOP bit to TX FIFO */
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iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
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/* Wait until the STOP is seen. */
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while (timeout > 0 &&
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(ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
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/* may be called from interrupt context */
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udelay(1);
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timeout--;
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}
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dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
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}
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/**
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* i2c_pnx_master_xmit - transmit data to slave
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* @adap: pointer to I2C adapter structure
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*
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* Sends one byte of data to the slave
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*/
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static int i2c_pnx_master_xmit(struct i2c_adapter *adap)
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{
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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u32 val;
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dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
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if (alg_data->mif.len > 0) {
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/* We still have something to talk about... */
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val = *alg_data->mif.buf++;
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if (alg_data->mif.len == 1) {
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val |= stop_bit;
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if (!alg_data->last)
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val |= start_bit;
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}
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alg_data->mif.len--;
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iowrite32(val, I2C_REG_TX(alg_data));
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dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __FUNCTION__,
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val, alg_data->mif.len + 1);
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if (alg_data->mif.len == 0) {
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if (alg_data->last) {
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/* Wait until the STOP is seen. */
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if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
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dev_err(&adap->dev, "The bus is still "
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"active after timeout\n");
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}
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/* Disable master interrupts */
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
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~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
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I2C_REG_CTL(alg_data));
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del_timer_sync(&alg_data->mif.timer);
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dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n",
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__FUNCTION__);
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complete(&alg_data->mif.complete);
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}
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} else if (alg_data->mif.len == 0) {
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/* zero-sized transfer */
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i2c_pnx_stop(adap);
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/* Disable master interrupts. */
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
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~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
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I2C_REG_CTL(alg_data));
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/* Stop timer. */
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del_timer_sync(&alg_data->mif.timer);
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dev_dbg(&adap->dev, "%s(): Waking up xfer routine after "
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"zero-xfer.\n", __FUNCTION__);
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complete(&alg_data->mif.complete);
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}
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dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
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return 0;
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}
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/**
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* i2c_pnx_master_rcv - receive data from slave
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* @adap: pointer to I2C adapter structure
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*
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* Reads one byte data from the slave
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*/
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static int i2c_pnx_master_rcv(struct i2c_adapter *adap)
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{
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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unsigned int val = 0;
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u32 ctl = 0;
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dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
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/* Check, whether there is already data,
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* or we didn't 'ask' for it yet.
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*/
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if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
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dev_dbg(&adap->dev, "%s(): Write dummy data to fill "
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"Rx-fifo...\n", __FUNCTION__);
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if (alg_data->mif.len == 1) {
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/* Last byte, do not acknowledge next rcv. */
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val |= stop_bit;
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if (!alg_data->last)
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val |= start_bit;
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/*
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* Enable interrupt RFDAIE (data in Rx fifo),
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* and disable DRMIE (need data for Tx)
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*/
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl |= mcntrl_rffie | mcntrl_daie;
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ctl &= ~mcntrl_drmie;
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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}
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/*
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* Now we'll 'ask' for data:
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* For each byte we want to receive, we must
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* write a (dummy) byte to the Tx-FIFO.
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*/
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iowrite32(val, I2C_REG_TX(alg_data));
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return 0;
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}
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/* Handle data. */
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if (alg_data->mif.len > 0) {
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val = ioread32(I2C_REG_RX(alg_data));
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*alg_data->mif.buf++ = (u8) (val & 0xff);
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dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __FUNCTION__, val,
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alg_data->mif.len);
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alg_data->mif.len--;
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if (alg_data->mif.len == 0) {
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if (alg_data->last)
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/* Wait until the STOP is seen. */
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if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
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dev_err(&adap->dev, "The bus is still "
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"active after timeout\n");
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/* Disable master interrupts */
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
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mcntrl_drmie | mcntrl_daie);
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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/* Kill timer. */
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del_timer_sync(&alg_data->mif.timer);
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complete(&alg_data->mif.complete);
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}
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}
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dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
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return 0;
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}
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static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
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{
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u32 stat, ctl;
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struct i2c_adapter *adap = dev_id;
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n",
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__FUNCTION__,
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ioread32(I2C_REG_STS(alg_data)),
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ioread32(I2C_REG_CTL(alg_data)),
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alg_data->mif.mode);
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stat = ioread32(I2C_REG_STS(alg_data));
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/* let's see what kind of event this is */
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if (stat & mstatus_afi) {
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/* We lost arbitration in the midst of a transfer */
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alg_data->mif.ret = -EIO;
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/* Disable master interrupts. */
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
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mcntrl_drmie);
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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/* Stop timer, to prevent timeout. */
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del_timer_sync(&alg_data->mif.timer);
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complete(&alg_data->mif.complete);
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} else if (stat & mstatus_nai) {
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/* Slave did not acknowledge, generate a STOP */
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dev_dbg(&adap->dev, "%s(): "
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"Slave did not acknowledge, generating a STOP.\n",
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__FUNCTION__);
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i2c_pnx_stop(adap);
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/* Disable master interrupts. */
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
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mcntrl_drmie);
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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/* Our return value. */
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alg_data->mif.ret = -EIO;
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/* Stop timer, to prevent timeout. */
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del_timer_sync(&alg_data->mif.timer);
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complete(&alg_data->mif.complete);
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} else {
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/*
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* Two options:
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* - Master Tx needs data.
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* - There is data in the Rx-fifo
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* The latter is only the case if we have requested for data,
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* via a dummy write. (See 'i2c_pnx_master_rcv'.)
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* We therefore check, as a sanity check, whether that interrupt
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* has been enabled.
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*/
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if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
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if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
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i2c_pnx_master_xmit(adap);
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} else if (alg_data->mif.mode == I2C_SMBUS_READ) {
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i2c_pnx_master_rcv(adap);
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}
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}
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}
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/* Clear TDI and AFI bits */
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stat = ioread32(I2C_REG_STS(alg_data));
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iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
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dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n",
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__FUNCTION__, ioread32(I2C_REG_STS(alg_data)),
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ioread32(I2C_REG_CTL(alg_data)));
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return IRQ_HANDLED;
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}
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static void i2c_pnx_timeout(unsigned long data)
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{
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struct i2c_adapter *adap = (struct i2c_adapter *)data;
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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u32 ctl;
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dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. "
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"Resetting master...\n",
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ioread32(I2C_REG_STS(alg_data)),
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ioread32(I2C_REG_CTL(alg_data)));
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/* Reset master and disable interrupts */
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ctl = ioread32(I2C_REG_CTL(alg_data));
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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ctl |= mcntrl_reset;
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iowrite32(ctl, I2C_REG_CTL(alg_data));
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wait_reset(I2C_PNX_TIMEOUT, alg_data);
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alg_data->mif.ret = -EIO;
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complete(&alg_data->mif.complete);
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}
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static inline void bus_reset_if_active(struct i2c_adapter *adap)
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{
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struct i2c_pnx_algo_data *alg_data = adap->algo_data;
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u32 stat;
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if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
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dev_err(&adap->dev,
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"%s: Bus is still active after xfer. Reset it...\n",
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adap->name);
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
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I2C_REG_CTL(alg_data));
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wait_reset(I2C_PNX_TIMEOUT, alg_data);
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} else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
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/* If there is data in the fifo's after transfer,
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* flush fifo's by reset.
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*/
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
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I2C_REG_CTL(alg_data));
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wait_reset(I2C_PNX_TIMEOUT, alg_data);
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} else if (stat & mstatus_nai) {
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
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I2C_REG_CTL(alg_data));
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wait_reset(I2C_PNX_TIMEOUT, alg_data);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* i2c_pnx_xfer - generic transfer entry point
|
|
* @adap: pointer to I2C adapter structure
|
|
* @msgs: array of messages
|
|
* @num: number of messages
|
|
*
|
|
* Initiates the transfer
|
|
*/
|
|
static int
|
|
i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct i2c_msg *pmsg;
|
|
int rc = 0, completed = 0, i;
|
|
struct i2c_pnx_algo_data *alg_data = adap->algo_data;
|
|
u32 stat = ioread32(I2C_REG_STS(alg_data));
|
|
|
|
dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n",
|
|
__FUNCTION__, num, ioread32(I2C_REG_STS(alg_data)));
|
|
|
|
bus_reset_if_active(adap);
|
|
|
|
/* Process transactions in a loop. */
|
|
for (i = 0; rc >= 0 && i < num; i++) {
|
|
u8 addr;
|
|
|
|
pmsg = &msgs[i];
|
|
addr = pmsg->addr;
|
|
|
|
if (pmsg->flags & I2C_M_TEN) {
|
|
dev_err(&adap->dev,
|
|
"%s: 10 bits addr not supported!\n",
|
|
adap->name);
|
|
rc = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
alg_data->mif.buf = pmsg->buf;
|
|
alg_data->mif.len = pmsg->len;
|
|
alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
|
|
I2C_SMBUS_READ : I2C_SMBUS_WRITE;
|
|
alg_data->mif.ret = 0;
|
|
alg_data->last = (i == num - 1);
|
|
|
|
dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __FUNCTION__,
|
|
alg_data->mif.mode,
|
|
alg_data->mif.len);
|
|
|
|
i2c_pnx_arm_timer(adap);
|
|
|
|
/* initialize the completion var */
|
|
init_completion(&alg_data->mif.complete);
|
|
|
|
/* Enable master interrupt */
|
|
iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
|
|
mcntrl_naie | mcntrl_drmie,
|
|
I2C_REG_CTL(alg_data));
|
|
|
|
/* Put start-code and slave-address on the bus. */
|
|
rc = i2c_pnx_start(addr, adap);
|
|
if (rc < 0)
|
|
break;
|
|
|
|
/* Wait for completion */
|
|
wait_for_completion(&alg_data->mif.complete);
|
|
|
|
if (!(rc = alg_data->mif.ret))
|
|
completed++;
|
|
dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n",
|
|
__FUNCTION__, rc);
|
|
|
|
/* Clear TDI and AFI bits in case they are set. */
|
|
if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
|
|
dev_dbg(&adap->dev,
|
|
"%s: TDI still set... clearing now.\n",
|
|
adap->name);
|
|
iowrite32(stat, I2C_REG_STS(alg_data));
|
|
}
|
|
if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
|
|
dev_dbg(&adap->dev,
|
|
"%s: AFI still set... clearing now.\n",
|
|
adap->name);
|
|
iowrite32(stat, I2C_REG_STS(alg_data));
|
|
}
|
|
}
|
|
|
|
bus_reset_if_active(adap);
|
|
|
|
/* Cleanup to be sure... */
|
|
alg_data->mif.buf = NULL;
|
|
alg_data->mif.len = 0;
|
|
|
|
dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n",
|
|
__FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
|
|
|
|
if (completed != num)
|
|
return ((rc < 0) ? rc : -EREMOTEIO);
|
|
|
|
return num;
|
|
}
|
|
|
|
static u32 i2c_pnx_func(struct i2c_adapter *adapter)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static struct i2c_algorithm pnx_algorithm = {
|
|
.master_xfer = i2c_pnx_xfer,
|
|
.functionality = i2c_pnx_func,
|
|
};
|
|
|
|
static int i2c_pnx_controller_suspend(struct platform_device *pdev,
|
|
pm_message_t state)
|
|
{
|
|
struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev);
|
|
return i2c_pnx->suspend(pdev, state);
|
|
}
|
|
|
|
static int i2c_pnx_controller_resume(struct platform_device *pdev)
|
|
{
|
|
struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev);
|
|
return i2c_pnx->resume(pdev);
|
|
}
|
|
|
|
static int __devinit i2c_pnx_probe(struct platform_device *pdev)
|
|
{
|
|
unsigned long tmp;
|
|
int ret = 0;
|
|
struct i2c_pnx_algo_data *alg_data;
|
|
int freq_mhz;
|
|
struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
|
|
|
|
if (!i2c_pnx || !i2c_pnx->adapter) {
|
|
dev_err(&pdev->dev, "%s: no platform data supplied\n",
|
|
__FUNCTION__);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, i2c_pnx);
|
|
|
|
if (i2c_pnx->calculate_input_freq)
|
|
freq_mhz = i2c_pnx->calculate_input_freq(pdev);
|
|
else {
|
|
freq_mhz = PNX_DEFAULT_FREQ;
|
|
dev_info(&pdev->dev, "Setting bus frequency to default value: "
|
|
"%d MHz\n", freq_mhz);
|
|
}
|
|
|
|
i2c_pnx->adapter->algo = &pnx_algorithm;
|
|
|
|
alg_data = i2c_pnx->adapter->algo_data;
|
|
init_timer(&alg_data->mif.timer);
|
|
alg_data->mif.timer.function = i2c_pnx_timeout;
|
|
alg_data->mif.timer.data = (unsigned long)i2c_pnx->adapter;
|
|
|
|
/* Register I/O resource */
|
|
if (!request_region(alg_data->base, I2C_PNX_REGION_SIZE, pdev->name)) {
|
|
dev_err(&pdev->dev,
|
|
"I/O region 0x%08x for I2C already in use.\n",
|
|
alg_data->base);
|
|
ret = -ENODEV;
|
|
goto out_drvdata;
|
|
}
|
|
|
|
if (!(alg_data->ioaddr =
|
|
(u32)ioremap(alg_data->base, I2C_PNX_REGION_SIZE))) {
|
|
dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
|
|
ret = -ENOMEM;
|
|
goto out_release;
|
|
}
|
|
|
|
i2c_pnx->set_clock_run(pdev);
|
|
|
|
/*
|
|
* Clock Divisor High This value is the number of system clocks
|
|
* the serial clock (SCL) will be high.
|
|
* For example, if the system clock period is 50 ns and the maximum
|
|
* desired serial period is 10000 ns (100 kHz), then CLKHI would be
|
|
* set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
|
|
* programmed into CLKHI will vary from this slightly due to
|
|
* variations in the output pad's rise and fall times as well as
|
|
* the deglitching filter length.
|
|
*/
|
|
|
|
tmp = ((freq_mhz * 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
|
|
iowrite32(tmp, I2C_REG_CKH(alg_data));
|
|
iowrite32(tmp, I2C_REG_CKL(alg_data));
|
|
|
|
iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
|
|
if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
|
|
ret = -ENODEV;
|
|
goto out_unmap;
|
|
}
|
|
init_completion(&alg_data->mif.complete);
|
|
|
|
ret = request_irq(alg_data->irq, i2c_pnx_interrupt,
|
|
0, pdev->name, i2c_pnx->adapter);
|
|
if (ret)
|
|
goto out_clock;
|
|
|
|
/* Register this adapter with the I2C subsystem */
|
|
i2c_pnx->adapter->dev.parent = &pdev->dev;
|
|
ret = i2c_add_adapter(i2c_pnx->adapter);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "I2C: Failed to add bus\n");
|
|
goto out_irq;
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
|
|
i2c_pnx->adapter->name, alg_data->base, alg_data->irq);
|
|
|
|
return 0;
|
|
|
|
out_irq:
|
|
free_irq(alg_data->irq, alg_data);
|
|
out_clock:
|
|
i2c_pnx->set_clock_stop(pdev);
|
|
out_unmap:
|
|
iounmap((void *)alg_data->ioaddr);
|
|
out_release:
|
|
release_region(alg_data->base, I2C_PNX_REGION_SIZE);
|
|
out_drvdata:
|
|
platform_set_drvdata(pdev, NULL);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit i2c_pnx_remove(struct platform_device *pdev)
|
|
{
|
|
struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev);
|
|
struct i2c_adapter *adap = i2c_pnx->adapter;
|
|
struct i2c_pnx_algo_data *alg_data = adap->algo_data;
|
|
|
|
free_irq(alg_data->irq, alg_data);
|
|
i2c_del_adapter(adap);
|
|
i2c_pnx->set_clock_stop(pdev);
|
|
iounmap((void *)alg_data->ioaddr);
|
|
release_region(alg_data->base, I2C_PNX_REGION_SIZE);
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver i2c_pnx_driver = {
|
|
.driver = {
|
|
.name = "pnx-i2c",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = i2c_pnx_probe,
|
|
.remove = __devexit_p(i2c_pnx_remove),
|
|
.suspend = i2c_pnx_controller_suspend,
|
|
.resume = i2c_pnx_controller_resume,
|
|
};
|
|
|
|
static int __init i2c_adap_pnx_init(void)
|
|
{
|
|
return platform_driver_register(&i2c_pnx_driver);
|
|
}
|
|
|
|
static void __exit i2c_adap_pnx_exit(void)
|
|
{
|
|
platform_driver_unregister(&i2c_pnx_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
|
|
MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
/* We need to make sure I2C is initialized before USB */
|
|
subsys_initcall(i2c_adap_pnx_init);
|
|
module_exit(i2c_adap_pnx_exit);
|