![Kalle Pokki](/assets/img/avatar_default.png)
All the users of this driver explicitly specify the I2C bus numbers to be used in their platform data. Make the driver respect that. Signed-off-by: Kalle Pokki <kalle.pokki@eke.fi> Cc: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
630 lines
16 KiB
C
630 lines
16 KiB
C
/*
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* drivers/i2c/busses/i2c-bfin-twi.c
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*
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* Description: Driver for Blackfin Two Wire Interface
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*
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* Author: sonicz <sonic.zhang@analog.com>
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*
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* Copyright (c) 2005-2007 Analog Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/mm.h>
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#include <linux/timer.h>
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#include <linux/spinlock.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <asm/blackfin.h>
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#include <asm/irq.h>
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#define POLL_TIMEOUT (2 * HZ)
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/* SMBus mode*/
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#define TWI_I2C_MODE_STANDARD 0x01
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#define TWI_I2C_MODE_STANDARDSUB 0x02
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#define TWI_I2C_MODE_COMBINED 0x04
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struct bfin_twi_iface {
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int irq;
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spinlock_t lock;
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char read_write;
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u8 command;
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u8 *transPtr;
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int readNum;
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int writeNum;
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int cur_mode;
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int manual_stop;
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int result;
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int timeout_count;
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struct timer_list timeout_timer;
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struct i2c_adapter adap;
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struct completion complete;
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};
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static struct bfin_twi_iface twi_iface;
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static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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{
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unsigned short twi_int_status = bfin_read_TWI_INT_STAT();
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unsigned short mast_stat = bfin_read_TWI_MASTER_STAT();
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if (twi_int_status & XMTSERV) {
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/* Transmit next data */
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if (iface->writeNum > 0) {
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bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
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iface->writeNum--;
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}
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/* start receive immediately after complete sending in
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* combine mode.
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*/
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else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| MDIR | RSTART);
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} else if (iface->manual_stop)
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| STOP);
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SSYNC();
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/* Clear status */
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bfin_write_TWI_INT_STAT(XMTSERV);
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SSYNC();
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}
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if (twi_int_status & RCVSERV) {
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if (iface->readNum > 0) {
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/* Receive next data */
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*(iface->transPtr) = bfin_read_TWI_RCV_DATA8();
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if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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/* Change combine mode into sub mode after
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* read first data.
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*/
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iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
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/* Get read number from first byte in block
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* combine mode.
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*/
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if (iface->readNum == 1 && iface->manual_stop)
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iface->readNum = *iface->transPtr + 1;
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}
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iface->transPtr++;
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iface->readNum--;
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} else if (iface->manual_stop) {
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
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| STOP);
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SSYNC();
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}
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/* Clear interrupt source */
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bfin_write_TWI_INT_STAT(RCVSERV);
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SSYNC();
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}
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if (twi_int_status & MERR) {
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bfin_write_TWI_INT_STAT(MERR);
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bfin_write_TWI_INT_MASK(0);
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bfin_write_TWI_MASTER_STAT(0x3e);
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bfin_write_TWI_MASTER_CTL(0);
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SSYNC();
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iface->result = -1;
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/* if both err and complete int stats are set, return proper
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* results.
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*/
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if (twi_int_status & MCOMP) {
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bfin_write_TWI_INT_STAT(MCOMP);
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bfin_write_TWI_INT_MASK(0);
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bfin_write_TWI_MASTER_CTL(0);
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SSYNC();
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/* If it is a quick transfer, only address bug no data,
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* not an err, return 1.
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*/
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if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
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iface->result = 1;
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/* If address not acknowledged return -1,
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* else return 0.
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*/
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else if (!(mast_stat & ANAK))
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iface->result = 0;
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}
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complete(&iface->complete);
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return;
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}
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if (twi_int_status & MCOMP) {
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bfin_write_TWI_INT_STAT(MCOMP);
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SSYNC();
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if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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if (iface->readNum == 0) {
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/* set the read number to 1 and ask for manual
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* stop in block combine mode
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*/
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iface->readNum = 1;
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iface->manual_stop = 1;
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bfin_write_TWI_MASTER_CTL(
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bfin_read_TWI_MASTER_CTL()
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| (0xff << 6));
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} else {
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/* set the readd number in other
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* combine mode.
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*/
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bfin_write_TWI_MASTER_CTL(
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(bfin_read_TWI_MASTER_CTL() &
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(~(0xff << 6))) |
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( iface->readNum << 6));
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}
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/* remove restart bit and enable master receive */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() &
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~RSTART);
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
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MEN | MDIR);
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SSYNC();
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} else {
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iface->result = 1;
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bfin_write_TWI_INT_MASK(0);
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bfin_write_TWI_MASTER_CTL(0);
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SSYNC();
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complete(&iface->complete);
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}
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}
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}
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/* Interrupt handler */
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static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
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{
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struct bfin_twi_iface *iface = dev_id;
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unsigned long flags;
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spin_lock_irqsave(&iface->lock, flags);
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del_timer(&iface->timeout_timer);
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bfin_twi_handle_interrupt(iface);
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spin_unlock_irqrestore(&iface->lock, flags);
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return IRQ_HANDLED;
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}
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static void bfin_twi_timeout(unsigned long data)
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{
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struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
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unsigned long flags;
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spin_lock_irqsave(&iface->lock, flags);
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bfin_twi_handle_interrupt(iface);
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if (iface->result == 0) {
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iface->timeout_count--;
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if (iface->timeout_count > 0) {
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iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
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add_timer(&iface->timeout_timer);
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} else {
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iface->result = -1;
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complete(&iface->complete);
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}
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}
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spin_unlock_irqrestore(&iface->lock, flags);
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}
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/*
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* Generic i2c master transfer entrypoint
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*/
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static int bfin_twi_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct bfin_twi_iface *iface = adap->algo_data;
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struct i2c_msg *pmsg;
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int i, ret;
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int rc = 0;
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if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
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return -ENXIO;
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while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) {
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yield();
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}
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ret = 0;
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for (i = 0; rc >= 0 && i < num; i++) {
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pmsg = &msgs[i];
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if (pmsg->flags & I2C_M_TEN) {
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dev_err(&(adap->dev), "i2c-bfin-twi: 10 bits addr "
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"not supported !\n");
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rc = -EINVAL;
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break;
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}
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iface->cur_mode = TWI_I2C_MODE_STANDARD;
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iface->manual_stop = 0;
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iface->transPtr = pmsg->buf;
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iface->writeNum = iface->readNum = pmsg->len;
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iface->result = 0;
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iface->timeout_count = 10;
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/* Set Transmit device address */
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bfin_write_TWI_MASTER_ADDR(pmsg->addr);
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/* FIFO Initiation. Data in FIFO should be
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* discarded before start a new operation.
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*/
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bfin_write_TWI_FIFO_CTL(0x3);
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SSYNC();
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bfin_write_TWI_FIFO_CTL(0);
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SSYNC();
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if (pmsg->flags & I2C_M_RD)
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iface->read_write = I2C_SMBUS_READ;
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else {
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iface->read_write = I2C_SMBUS_WRITE;
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/* Transmit first data */
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if (iface->writeNum > 0) {
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bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
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iface->writeNum--;
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SSYNC();
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}
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}
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/* clear int stat */
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bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV);
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/* Interrupt mask . Enable XMT, RCV interrupt */
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bfin_write_TWI_INT_MASK(MCOMP | MERR |
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((iface->read_write == I2C_SMBUS_READ)?
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RCVSERV : XMTSERV));
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SSYNC();
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if (pmsg->len > 0 && pmsg->len <= 255)
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bfin_write_TWI_MASTER_CTL(pmsg->len << 6);
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else if (pmsg->len > 255) {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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} else
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break;
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iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
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add_timer(&iface->timeout_timer);
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/* Master enable */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
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((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
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((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
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SSYNC();
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wait_for_completion(&iface->complete);
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rc = iface->result;
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if (rc == 1)
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ret++;
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else if (rc == -1)
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break;
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}
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return ret;
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}
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/*
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* SMBus type transfer entrypoint
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*/
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int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
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unsigned short flags, char read_write,
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u8 command, int size, union i2c_smbus_data *data)
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{
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struct bfin_twi_iface *iface = adap->algo_data;
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int rc = 0;
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if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
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return -ENXIO;
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while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) {
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yield();
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}
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iface->writeNum = 0;
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iface->readNum = 0;
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/* Prepare datas & select mode */
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switch (size) {
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case I2C_SMBUS_QUICK:
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iface->transPtr = NULL;
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iface->cur_mode = TWI_I2C_MODE_STANDARD;
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break;
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case I2C_SMBUS_BYTE:
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if (data == NULL)
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iface->transPtr = NULL;
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else {
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if (read_write == I2C_SMBUS_READ)
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iface->readNum = 1;
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else
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iface->writeNum = 1;
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iface->transPtr = &data->byte;
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}
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iface->cur_mode = TWI_I2C_MODE_STANDARD;
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break;
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case I2C_SMBUS_BYTE_DATA:
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if (read_write == I2C_SMBUS_READ) {
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iface->readNum = 1;
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iface->cur_mode = TWI_I2C_MODE_COMBINED;
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} else {
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iface->writeNum = 1;
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iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
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}
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iface->transPtr = &data->byte;
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break;
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case I2C_SMBUS_WORD_DATA:
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if (read_write == I2C_SMBUS_READ) {
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iface->readNum = 2;
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iface->cur_mode = TWI_I2C_MODE_COMBINED;
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} else {
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iface->writeNum = 2;
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iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
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}
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iface->transPtr = (u8 *)&data->word;
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break;
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case I2C_SMBUS_PROC_CALL:
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iface->writeNum = 2;
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iface->readNum = 2;
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iface->cur_mode = TWI_I2C_MODE_COMBINED;
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iface->transPtr = (u8 *)&data->word;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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if (read_write == I2C_SMBUS_READ) {
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iface->readNum = 0;
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iface->cur_mode = TWI_I2C_MODE_COMBINED;
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} else {
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iface->writeNum = data->block[0] + 1;
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iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
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}
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iface->transPtr = data->block;
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break;
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default:
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return -1;
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}
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iface->result = 0;
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iface->manual_stop = 0;
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iface->read_write = read_write;
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iface->command = command;
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iface->timeout_count = 10;
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/* FIFO Initiation. Data in FIFO should be discarded before
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* start a new operation.
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*/
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bfin_write_TWI_FIFO_CTL(0x3);
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SSYNC();
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bfin_write_TWI_FIFO_CTL(0);
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/* clear int stat */
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bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV);
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/* Set Transmit device address */
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bfin_write_TWI_MASTER_ADDR(addr);
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SSYNC();
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iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
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add_timer(&iface->timeout_timer);
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switch (iface->cur_mode) {
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case TWI_I2C_MODE_STANDARDSUB:
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bfin_write_TWI_XMT_DATA8(iface->command);
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bfin_write_TWI_INT_MASK(MCOMP | MERR |
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((iface->read_write == I2C_SMBUS_READ) ?
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RCVSERV : XMTSERV));
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SSYNC();
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if (iface->writeNum + 1 <= 255)
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bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6);
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else {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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}
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/* Master enable */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
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((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
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break;
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case TWI_I2C_MODE_COMBINED:
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bfin_write_TWI_XMT_DATA8(iface->command);
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bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV);
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SSYNC();
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if (iface->writeNum > 0)
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bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6);
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else
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bfin_write_TWI_MASTER_CTL(0x1 << 6);
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/* Master enable */
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bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
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((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
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break;
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default:
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bfin_write_TWI_MASTER_CTL(0);
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if (size != I2C_SMBUS_QUICK) {
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/* Don't access xmit data register when this is a
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* read operation.
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*/
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if (iface->read_write != I2C_SMBUS_READ) {
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if (iface->writeNum > 0) {
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bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
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if (iface->writeNum <= 255)
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bfin_write_TWI_MASTER_CTL(iface->writeNum << 6);
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else {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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}
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iface->writeNum--;
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} else {
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bfin_write_TWI_XMT_DATA8(iface->command);
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bfin_write_TWI_MASTER_CTL(1 << 6);
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}
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} else {
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if (iface->readNum > 0 && iface->readNum <= 255)
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bfin_write_TWI_MASTER_CTL(iface->readNum << 6);
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else if (iface->readNum > 255) {
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bfin_write_TWI_MASTER_CTL(0xff << 6);
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iface->manual_stop = 1;
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} else {
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del_timer(&iface->timeout_timer);
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break;
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}
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}
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}
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bfin_write_TWI_INT_MASK(MCOMP | MERR |
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((iface->read_write == I2C_SMBUS_READ) ?
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RCVSERV : XMTSERV));
|
|
SSYNC();
|
|
|
|
/* Master enable */
|
|
bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
|
|
((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
|
|
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
|
|
break;
|
|
}
|
|
SSYNC();
|
|
|
|
wait_for_completion(&iface->complete);
|
|
|
|
rc = (iface->result >= 0) ? 0 : -1;
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Return what the adapter supports
|
|
*/
|
|
static u32 bfin_twi_functionality(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
|
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
|
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
|
|
I2C_FUNC_I2C;
|
|
}
|
|
|
|
|
|
static struct i2c_algorithm bfin_twi_algorithm = {
|
|
.master_xfer = bfin_twi_master_xfer,
|
|
.smbus_xfer = bfin_twi_smbus_xfer,
|
|
.functionality = bfin_twi_functionality,
|
|
};
|
|
|
|
|
|
static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/
|
|
|
|
/* Disable TWI */
|
|
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA);
|
|
SSYNC();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_bfin_twi_resume(struct platform_device *dev)
|
|
{
|
|
/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/
|
|
|
|
/* Enable TWI */
|
|
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
|
|
SSYNC();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_bfin_twi_probe(struct platform_device *dev)
|
|
{
|
|
struct bfin_twi_iface *iface = &twi_iface;
|
|
struct i2c_adapter *p_adap;
|
|
int rc;
|
|
|
|
spin_lock_init(&(iface->lock));
|
|
init_completion(&(iface->complete));
|
|
iface->irq = IRQ_TWI;
|
|
|
|
init_timer(&(iface->timeout_timer));
|
|
iface->timeout_timer.function = bfin_twi_timeout;
|
|
iface->timeout_timer.data = (unsigned long)iface;
|
|
|
|
p_adap = &iface->adap;
|
|
p_adap->id = I2C_HW_BLACKFIN;
|
|
p_adap->nr = dev->id;
|
|
strlcpy(p_adap->name, dev->name, sizeof(p_adap->name));
|
|
p_adap->algo = &bfin_twi_algorithm;
|
|
p_adap->algo_data = iface;
|
|
p_adap->class = I2C_CLASS_ALL;
|
|
p_adap->dev.parent = &dev->dev;
|
|
|
|
rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
|
|
IRQF_DISABLED, dev->name, iface);
|
|
if (rc) {
|
|
dev_err(&(p_adap->dev), "i2c-bfin-twi: can't get IRQ %d !\n",
|
|
iface->irq);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Set TWI internal clock as 10MHz */
|
|
bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
|
|
|
|
/* Set Twi interface clock as specified */
|
|
bfin_write_TWI_CLKDIV((( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ )
|
|
<< 8) | (( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ )
|
|
& 0xFF));
|
|
|
|
/* Enable TWI */
|
|
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
|
|
SSYNC();
|
|
|
|
rc = i2c_add_numbered_adapter(p_adap);
|
|
if (rc < 0)
|
|
free_irq(iface->irq, iface);
|
|
else
|
|
platform_set_drvdata(dev, iface);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int i2c_bfin_twi_remove(struct platform_device *pdev)
|
|
{
|
|
struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
i2c_del_adapter(&(iface->adap));
|
|
free_irq(iface->irq, iface);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver i2c_bfin_twi_driver = {
|
|
.probe = i2c_bfin_twi_probe,
|
|
.remove = i2c_bfin_twi_remove,
|
|
.suspend = i2c_bfin_twi_suspend,
|
|
.resume = i2c_bfin_twi_resume,
|
|
.driver = {
|
|
.name = "i2c-bfin-twi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init i2c_bfin_twi_init(void)
|
|
{
|
|
pr_info("I2C: Blackfin I2C TWI driver\n");
|
|
|
|
return platform_driver_register(&i2c_bfin_twi_driver);
|
|
}
|
|
|
|
static void __exit i2c_bfin_twi_exit(void)
|
|
{
|
|
platform_driver_unregister(&i2c_bfin_twi_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
|
|
MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
module_init(i2c_bfin_twi_init);
|
|
module_exit(i2c_bfin_twi_exit);
|