![David Gibson](/assets/img/avatar_default.png)
The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
1406 lines
28 KiB
ArmAsm
1406 lines
28 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_8xx
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#define ISYNC_8xx isync
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#else
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#define ISYNC_8xx
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#endif
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.text
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.align 5
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_GLOBAL(__delay)
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cmpwi 0,r3,0
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mtctr r3
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beqlr
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1: bdnz 1b
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blr
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/*
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* Returns (address we're running at) - (address we were linked at)
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* for use before the text and data are mapped to KERNELBASE.
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*/
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_GLOBAL(reloc_offset)
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mflr r0
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bl 1f
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1: mflr r3
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r3,r4,r3
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mtlr r0
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blr
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/*
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* add_reloc_offset(x) returns x + reloc_offset().
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*/
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_GLOBAL(add_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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add r3,r3,r5
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mtlr r0
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blr
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/*
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* sub_reloc_offset(x) returns x - reloc_offset().
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*/
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_GLOBAL(sub_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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subf r3,r5,r3
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mtlr r0
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blr
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/*
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* reloc_got2 runs through the .got2 section adding an offset
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* to each entry.
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*/
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_GLOBAL(reloc_got2)
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mflr r11
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lis r7,__got2_start@ha
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addi r7,r7,__got2_start@l
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lis r8,__got2_end@ha
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addi r8,r8,__got2_end@l
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subf r8,r7,r8
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srwi. r8,r8,2
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beqlr
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mtctr r8
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bl 1f
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1: mflr r0
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r0,r4,r0
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add r7,r0,r7
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2: lwz r0,0(r7)
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add r0,r0,r3
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stw r0,0(r7)
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addi r7,r7,4
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bdnz 2b
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mtlr r11
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blr
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/*
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* identify_cpu,
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* called with r3 = data offset and r4 = CPU number
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* doesn't change r3
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*/
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_GLOBAL(identify_cpu)
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addis r8,r3,cpu_specs@ha
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addi r8,r8,cpu_specs@l
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mfpvr r7
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1:
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lwz r5,CPU_SPEC_PVR_MASK(r8)
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and r5,r5,r7
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lwz r6,CPU_SPEC_PVR_VALUE(r8)
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cmplw 0,r6,r5
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beq 1f
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addi r8,r8,CPU_SPEC_ENTRY_SIZE
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b 1b
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1:
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addis r6,r3,cur_cpu_spec@ha
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addi r6,r6,cur_cpu_spec@l
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sub r8,r8,r3
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stw r8,0(r6)
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blr
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/*
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* do_cpu_ftr_fixups - goes through the list of CPU feature fixups
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* and writes nop's over sections of code that don't apply for this cpu.
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* r3 = data offset (not changed)
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*/
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_GLOBAL(do_cpu_ftr_fixups)
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/* Get CPU 0 features */
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addis r6,r3,cur_cpu_spec@ha
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addi r6,r6,cur_cpu_spec@l
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lwz r4,0(r6)
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add r4,r4,r3
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lwz r4,CPU_SPEC_FEATURES(r4)
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/* Get the fixup table */
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addis r6,r3,__start___ftr_fixup@ha
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addi r6,r6,__start___ftr_fixup@l
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addis r7,r3,__stop___ftr_fixup@ha
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addi r7,r7,__stop___ftr_fixup@l
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/* Do the fixup */
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1: cmplw 0,r6,r7
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bgelr
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addi r6,r6,16
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lwz r8,-16(r6) /* mask */
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and r8,r8,r4
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lwz r9,-12(r6) /* value */
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cmplw 0,r8,r9
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beq 1b
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lwz r8,-8(r6) /* section begin */
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lwz r9,-4(r6) /* section end */
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subf. r9,r8,r9
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beq 1b
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/* write nops over the section of code */
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/* todo: if large section, add a branch at the start of it */
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srwi r9,r9,2
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mtctr r9
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add r8,r8,r3
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lis r0,0x60000000@h /* nop */
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3: stw r0,0(r8)
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andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
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beq 2f
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dcbst 0,r8 /* suboptimal, but simpler */
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sync
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icbi 0,r8
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2: addi r8,r8,4
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bdnz 3b
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sync /* additional sync needed on g4 */
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isync
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b 1b
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/*
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* call_setup_cpu - call the setup_cpu function for this cpu
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* r3 = data offset, r24 = cpu number
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*
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* Setup function is called with:
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* r3 = data offset
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* r4 = ptr to CPU spec (relocated)
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*/
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_GLOBAL(call_setup_cpu)
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addis r4,r3,cur_cpu_spec@ha
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addi r4,r4,cur_cpu_spec@l
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lwz r4,0(r4)
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add r4,r4,r3
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lwz r5,CPU_SPEC_SETUP(r4)
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cmpi 0,r5,0
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add r5,r5,r3
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beqlr
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mtctr r5
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bctr
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#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
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/* This gets called by via-pmu.c to switch the PLL selection
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* on 750fx CPU. This function should really be moved to some
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* other place (as most of the cpufreq code in via-pmu
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*/
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_GLOBAL(low_choose_750fx_pll)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* If switching to PLL1, disable HID0:BTIC */
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cmplwi cr0,r3,0
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beq 1f
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mfspr r5,SPRN_HID0
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rlwinm r5,r5,0,27,25
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
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rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
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rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
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or r4,r4,r5
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mtspr SPRN_HID1,r4
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/* Store new HID1 image */
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rlwinm r6,r1,0,0,18
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lwz r6,TI_CPU(r6)
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slwi r6,r6,2
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addis r6,r6,nap_save_hid1@ha
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stw r4,nap_save_hid1@l(r6)
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/* If switching to PLL0, enable HID0:BTIC */
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cmplwi cr0,r3,0
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bne 1f
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mfspr r5,SPRN_HID0
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ori r5,r5,HID0_BTIC
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Return */
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mtmsr r7
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blr
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_GLOBAL(low_choose_7447a_dfs)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1
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insrwi r4,r3,1,9 /* insert parameter into bit 9 */
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sync
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mtspr SPRN_HID1,r4
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sync
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isync
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/* Return */
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mtmsr r7
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blr
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#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
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/*
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* complement mask on the msr then "or" some values on.
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* _nmask_and_or_msr(nmask, value_to_or)
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*/
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_GLOBAL(_nmask_and_or_msr)
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mfmsr r0 /* Get current msr */
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andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
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or r0,r0,r4 /* Or on the bits in r4 (second parm) */
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SYNC /* Some chip revs have problems here... */
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mtmsr r0 /* Update machine state */
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isync
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blr /* Done */
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/*
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* Flush MMU TLB
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*/
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_GLOBAL(_tlbia)
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#if defined(CONFIG_40x)
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sync /* Flush to memory before changing mapping */
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tlbia
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isync /* Flush shadow TLB */
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#elif defined(CONFIG_44x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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#elif defined(CONFIG_FSL_BOOKE)
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/* Invalidate all entries in TLB0 */
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li r3, 0x04
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tlbivax 0,3
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/* Invalidate all entries in TLB1 */
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li r3, 0x0c
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tlbivax 0,3
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/* Invalidate all entries in TLB2 */
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li r3, 0x14
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tlbivax 0,3
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/* Invalidate all entries in TLB3 */
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li r3, 0x1c
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tlbivax 0,3
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msync
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#ifdef CONFIG_SMP
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,18
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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sync
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tlbia
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! defined(CONFIG_40x) */
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blr
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/*
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* Flush MMU TLB for a particular address
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*/
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_GLOBAL(_tlbie)
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#if defined(CONFIG_40x)
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tlbsx. r3, 0, r3
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
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* Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
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* the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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10:
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#elif defined(CONFIG_44x)
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mfspr r4,SPRN_MMUCR
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mfspr r5,SPRN_PID /* Get PID */
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rlwimi r4,r5,0,24,31 /* Set TID */
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mtspr SPRN_MMUCR,r4
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tlbsx. r3, 0, r3
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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* which means bit 22, is clear. Since 22 is
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* the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r3, r3, PPC44x_TLB_PAGEID
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isync
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10:
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#elif defined(CONFIG_FSL_BOOKE)
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rlwinm r4, r3, 0, 0, 19
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ori r5, r4, 0x08 /* TLBSEL = 1 */
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ori r6, r4, 0x10 /* TLBSEL = 2 */
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ori r7, r4, 0x18 /* TLBSEL = 3 */
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tlbivax 0, r4
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tlbivax 0, r5
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tlbivax 0, r6
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tlbivax 0, r7
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msync
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#if defined(CONFIG_SMP)
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,18
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lwz r8,TI_CPU(r8)
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oris r8,r8,11
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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tlbie r3
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! CONFIG_40x */
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blr
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/*
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* Flush instruction cache.
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* This is a no-op on the 601.
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*/
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_GLOBAL(flush_instruction_cache)
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#if defined(CONFIG_8xx)
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isync
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lis r5, IDC_INVALL@h
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mtspr SPRN_IC_CST, r5
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#elif defined(CONFIG_4xx)
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#ifdef CONFIG_403GCX
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li r3, 512
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mtctr r3
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lis r4, KERNELBASE@h
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1: iccci 0, r4
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addi r4, r4, 16
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bdnz 1b
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#else
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lis r3, KERNELBASE@h
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iccci 0,r3
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#endif
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#elif CONFIG_FSL_BOOKE
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|
BEGIN_FTR_SECTION
|
|
mfspr r3,SPRN_L1CSR0
|
|
ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
|
|
/* msync; isync recommended here */
|
|
mtspr SPRN_L1CSR0,r3
|
|
isync
|
|
blr
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
mfspr r3,SPRN_L1CSR1
|
|
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
|
|
mtspr SPRN_L1CSR1,r3
|
|
#else
|
|
mfspr r3,SPRN_PVR
|
|
rlwinm r3,r3,16,16,31
|
|
cmpwi 0,r3,1
|
|
beqlr /* for 601, do nothing */
|
|
/* 603/604 processor - use invalidate-all bit in HID0 */
|
|
mfspr r3,SPRN_HID0
|
|
ori r3,r3,HID0_ICFI
|
|
mtspr SPRN_HID0,r3
|
|
#endif /* CONFIG_8xx/4xx */
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Write any modified data cache blocks out to memory
|
|
* and invalidate the corresponding instruction cache blocks.
|
|
* This is a no-op on the 601.
|
|
*
|
|
* __flush_icache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(__flush_icache_range)
|
|
BEGIN_FTR_SECTION
|
|
blr /* for 601, do nothing */
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
mr r6,r3
|
|
1: dcbst 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
mtctr r4
|
|
2: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 2b
|
|
sync /* additional sync needed on g4 */
|
|
isync
|
|
blr
|
|
/*
|
|
* Write any modified data cache blocks out to memory.
|
|
* Does not invalidate the corresponding cache lines (especially for
|
|
* any corresponding instruction cache).
|
|
*
|
|
* clean_dcache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(clean_dcache_range)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
|
|
1: dcbst 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
blr
|
|
|
|
/*
|
|
* Write any modified data cache blocks out to memory and invalidate them.
|
|
* Does not invalidate the corresponding instruction cache blocks.
|
|
*
|
|
* flush_dcache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(flush_dcache_range)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
|
|
1: dcbf 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
blr
|
|
|
|
/*
|
|
* Like above, but invalidate the D-cache. This is used by the 8xx
|
|
* to invalidate the cache so the PPC core doesn't get stale data
|
|
* from the CPM (no cache snooping here :-).
|
|
*
|
|
* invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(invalidate_dcache_range)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
|
|
1: dcbi 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbi's to get to ram */
|
|
blr
|
|
|
|
#ifdef CONFIG_NOT_COHERENT_CACHE
|
|
/*
|
|
* 40x cores have 8K or 16K dcache and 32 byte line size.
|
|
* 44x has a 32K dcache and 32 byte line size.
|
|
* 8xx has 1, 2, 4, 8K variants.
|
|
* For now, cover the worst case of the 44x.
|
|
* Must be called with external interrupts disabled.
|
|
*/
|
|
#define CACHE_NWAYS 64
|
|
#define CACHE_NLINES 16
|
|
|
|
_GLOBAL(flush_dcache_all)
|
|
li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
|
|
mtctr r4
|
|
lis r5, KERNELBASE@h
|
|
1: lwz r3, 0(r5) /* Load one word from every line */
|
|
addi r5, r5, L1_CACHE_BYTES
|
|
bdnz 1b
|
|
blr
|
|
#endif /* CONFIG_NOT_COHERENT_CACHE */
|
|
|
|
/*
|
|
* Flush a particular page from the data cache to RAM.
|
|
* Note: this is necessary because the instruction cache does *not*
|
|
* snoop from the data cache.
|
|
* This is a no-op on the 601 which has a unified cache.
|
|
*
|
|
* void __flush_dcache_icache(void *page)
|
|
*/
|
|
_GLOBAL(__flush_dcache_icache)
|
|
BEGIN_FTR_SECTION
|
|
blr /* for 601, do nothing */
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
|
mtctr r4
|
|
mr r6,r3
|
|
0: dcbst 0,r3 /* Write line to ram */
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 0b
|
|
sync
|
|
mtctr r4
|
|
1: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Flush a particular page from the data cache to RAM, identified
|
|
* by its physical address. We turn off the MMU so we can just use
|
|
* the physical address (this may be a highmem page without a kernel
|
|
* mapping).
|
|
*
|
|
* void __flush_dcache_icache_phys(unsigned long physaddr)
|
|
*/
|
|
_GLOBAL(__flush_dcache_icache_phys)
|
|
BEGIN_FTR_SECTION
|
|
blr /* for 601, do nothing */
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
mfmsr r10
|
|
rlwinm r0,r10,0,28,26 /* clear DR */
|
|
mtmsr r0
|
|
isync
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
|
mtctr r4
|
|
mr r6,r3
|
|
0: dcbst 0,r3 /* Write line to ram */
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 0b
|
|
sync
|
|
mtctr r4
|
|
1: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync
|
|
mtmsr r10 /* restore DR */
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Clear pages using the dcbz instruction, which doesn't cause any
|
|
* memory traffic (except to write out any cache lines which get
|
|
* displaced). This only works on cacheable memory.
|
|
*
|
|
* void clear_pages(void *page, int order) ;
|
|
*/
|
|
_GLOBAL(clear_pages)
|
|
li r0,4096/L1_CACHE_BYTES
|
|
slw r0,r0,r4
|
|
mtctr r0
|
|
#ifdef CONFIG_8xx
|
|
li r4, 0
|
|
1: stw r4, 0(r3)
|
|
stw r4, 4(r3)
|
|
stw r4, 8(r3)
|
|
stw r4, 12(r3)
|
|
#else
|
|
1: dcbz 0,r3
|
|
#endif
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
/*
|
|
* Copy a whole page. We use the dcbz instruction on the destination
|
|
* to reduce memory traffic (it eliminates the unnecessary reads of
|
|
* the destination into cache). This requires that the destination
|
|
* is cacheable.
|
|
*/
|
|
#define COPY_16_BYTES \
|
|
lwz r6,4(r4); \
|
|
lwz r7,8(r4); \
|
|
lwz r8,12(r4); \
|
|
lwzu r9,16(r4); \
|
|
stw r6,4(r3); \
|
|
stw r7,8(r3); \
|
|
stw r8,12(r3); \
|
|
stwu r9,16(r3)
|
|
|
|
_GLOBAL(copy_page)
|
|
addi r3,r3,-4
|
|
addi r4,r4,-4
|
|
|
|
#ifdef CONFIG_8xx
|
|
/* don't use prefetch on 8xx */
|
|
li r0,4096/L1_CACHE_BYTES
|
|
mtctr r0
|
|
1: COPY_16_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
#else /* not 8xx, we can prefetch */
|
|
li r5,4
|
|
|
|
#if MAX_COPY_PREFETCH > 1
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
mtctr r0
|
|
11: dcbt r11,r4
|
|
addi r11,r11,L1_CACHE_BYTES
|
|
bdnz 11b
|
|
#else /* MAX_COPY_PREFETCH == 1 */
|
|
dcbt r5,r4
|
|
li r11,L1_CACHE_BYTES+4
|
|
#endif /* MAX_COPY_PREFETCH */
|
|
li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
|
|
crclr 4*cr0+eq
|
|
2:
|
|
mtctr r0
|
|
1:
|
|
dcbt r11,r4
|
|
dcbz r5,r3
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 32
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 64
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 128
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#endif
|
|
#endif
|
|
#endif
|
|
bdnz 1b
|
|
beqlr
|
|
crnot 4*cr0+eq,4*cr0+eq
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
b 2b
|
|
#endif /* CONFIG_8xx */
|
|
|
|
/*
|
|
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
|
|
* void atomic_set_mask(atomic_t mask, atomic_t *addr);
|
|
*/
|
|
_GLOBAL(atomic_clear_mask)
|
|
10: lwarx r5,0,r4
|
|
andc r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
_GLOBAL(atomic_set_mask)
|
|
10: lwarx r5,0,r4
|
|
or r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
|
|
/*
|
|
* I/O string operations
|
|
*
|
|
* insb(port, buf, len)
|
|
* outsb(port, buf, len)
|
|
* insw(port, buf, len)
|
|
* outsw(port, buf, len)
|
|
* insl(port, buf, len)
|
|
* outsl(port, buf, len)
|
|
* insw_ns(port, buf, len)
|
|
* outsw_ns(port, buf, len)
|
|
* insl_ns(port, buf, len)
|
|
* outsl_ns(port, buf, len)
|
|
*
|
|
* The *_ns versions don't do byte-swapping.
|
|
*/
|
|
_GLOBAL(_insb)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,1
|
|
blelr-
|
|
00: lbz r5,0(r3)
|
|
01: eieio
|
|
02: stbu r5,1(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_outsb)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,1
|
|
blelr-
|
|
00: lbzu r5,1(r4)
|
|
01: stb r5,0(r3)
|
|
02: eieio
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_insw)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,2
|
|
blelr-
|
|
00: lhbrx r5,0,r3
|
|
01: eieio
|
|
02: sthu r5,2(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_outsw)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,2
|
|
blelr-
|
|
00: lhzu r5,2(r4)
|
|
01: eieio
|
|
02: sthbrx r5,0,r3
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_insl)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,4
|
|
blelr-
|
|
00: lwbrx r5,0,r3
|
|
01: eieio
|
|
02: stwu r5,4(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_outsl)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,4
|
|
blelr-
|
|
00: lwzu r5,4(r4)
|
|
01: stwbrx r5,0,r3
|
|
02: eieio
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(__ide_mm_insw)
|
|
_GLOBAL(_insw_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,2
|
|
blelr-
|
|
00: lhz r5,0(r3)
|
|
01: eieio
|
|
02: sthu r5,2(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(__ide_mm_outsw)
|
|
_GLOBAL(_outsw_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,2
|
|
blelr-
|
|
00: lhzu r5,2(r4)
|
|
01: sth r5,0(r3)
|
|
02: eieio
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(__ide_mm_insl)
|
|
_GLOBAL(_insl_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,4
|
|
blelr-
|
|
00: lwz r5,0(r3)
|
|
01: eieio
|
|
02: stwu r5,4(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(__ide_mm_outsl)
|
|
_GLOBAL(_outsl_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,4
|
|
blelr-
|
|
00: lwzu r5,4(r4)
|
|
01: stw r5,0(r3)
|
|
02: eieio
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ISYNC_8xx
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.section .fixup,"ax"
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03: blr
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.text
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.section __ex_table, "a"
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.align 2
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.long 00b, 03b
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.long 01b, 03b
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.long 02b, 03b
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.text
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bdnz 00b
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blr
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/*
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* Extended precision shifts.
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*
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* Updated to be valid for shift counts from 0 to 63 inclusive.
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* -- Gabriel
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*
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* R3/R4 has 64 bit value
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* R5 has shift count
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* result in R3/R4
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*
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* ashrdi3: arithmetic right shift (sign propagation)
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* lshrdi3: logical right shift
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* ashldi3: left shift
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*/
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_GLOBAL(__ashrdi3)
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subfic r6,r5,32
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srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
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addi r7,r5,32 # could be xori, or addi with -32
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slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
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rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
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sraw r7,r3,r7 # t2 = MSW >> (count-32)
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or r4,r4,r6 # LSW |= t1
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slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
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sraw r3,r3,r5 # MSW = MSW >> count
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or r4,r4,r7 # LSW |= t2
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blr
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_GLOBAL(__ashldi3)
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subfic r6,r5,32
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slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
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addi r7,r5,32 # could be xori, or addi with -32
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srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
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slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
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or r3,r3,r6 # MSW |= t1
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slw r4,r4,r5 # LSW = LSW << count
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or r3,r3,r7 # MSW |= t2
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blr
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_GLOBAL(__lshrdi3)
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subfic r6,r5,32
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srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
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addi r7,r5,32 # could be xori, or addi with -32
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slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
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srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
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or r4,r4,r6 # LSW |= t1
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srw r3,r3,r5 # MSW = MSW >> count
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or r4,r4,r7 # LSW |= t2
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blr
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_GLOBAL(abs)
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srawi r4,r3,31
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xor r3,r3,r4
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sub r3,r3,r4
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blr
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_GLOBAL(_get_SP)
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mr r3,r1 /* Close enough */
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blr
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/*
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* Create a kernel thread
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* kernel_thread(fn, arg, flags)
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*/
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_GLOBAL(kernel_thread)
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stwu r1,-16(r1)
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stw r30,8(r1)
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stw r31,12(r1)
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mr r30,r3 /* function */
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mr r31,r4 /* argument */
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ori r3,r5,CLONE_VM /* flags */
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oris r3,r3,CLONE_UNTRACED>>16
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li r4,0 /* new sp (unused) */
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li r0,__NR_clone
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sc
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cmpwi 0,r3,0 /* parent or child? */
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bne 1f /* return if parent */
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li r0,0 /* make top-level stack frame */
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stwu r0,-16(r1)
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mtlr r30 /* fn addr in lr */
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mr r3,r31 /* load arg and call fn */
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PPC440EP_ERR42
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blrl
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li r0,__NR_exit /* exit if function returns */
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li r3,0
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sc
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1: lwz r30,8(r1)
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lwz r31,12(r1)
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addi r1,r1,16
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blr
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/*
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* This routine is just here to keep GCC happy - sigh...
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*/
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_GLOBAL(__main)
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blr
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#define SYSCALL(name) \
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_GLOBAL(name) \
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li r0,__NR_##name; \
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sc; \
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bnslr; \
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lis r4,errno@ha; \
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stw r3,errno@l(r4); \
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li r3,-1; \
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blr
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SYSCALL(execve)
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/* Why isn't this a) automatic, b) written in 'C'? */
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.data
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.align 4
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_GLOBAL(sys_call_table)
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.long sys_restart_syscall /* 0 */
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.long sys_exit
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.long ppc_fork
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.long sys_read
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.long sys_write
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.long sys_open /* 5 */
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.long sys_close
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.long sys_waitpid
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.long sys_creat
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.long sys_link
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.long sys_unlink /* 10 */
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.long sys_execve
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.long sys_chdir
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.long sys_time
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.long sys_mknod
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.long sys_chmod /* 15 */
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.long sys_lchown
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.long sys_ni_syscall /* old break syscall holder */
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.long sys_stat
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.long sys_lseek
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.long sys_getpid /* 20 */
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.long sys_mount
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.long sys_oldumount
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.long sys_setuid
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.long sys_getuid
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.long sys_stime /* 25 */
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.long sys_ptrace
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.long sys_alarm
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.long sys_fstat
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.long sys_pause
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.long sys_utime /* 30 */
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.long sys_ni_syscall /* old stty syscall holder */
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.long sys_ni_syscall /* old gtty syscall holder */
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.long sys_access
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.long sys_nice
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.long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
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.long sys_sync
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.long sys_kill
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.long sys_rename
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.long sys_mkdir
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.long sys_rmdir /* 40 */
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.long sys_dup
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.long sys_pipe
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.long sys_times
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.long sys_ni_syscall /* old prof syscall holder */
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.long sys_brk /* 45 */
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.long sys_setgid
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.long sys_getgid
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.long sys_signal
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.long sys_geteuid
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.long sys_getegid /* 50 */
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.long sys_acct
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.long sys_umount /* recycled never used phys() */
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.long sys_ni_syscall /* old lock syscall holder */
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.long sys_ioctl
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.long sys_fcntl /* 55 */
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.long sys_ni_syscall /* old mpx syscall holder */
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.long sys_setpgid
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.long sys_ni_syscall /* old ulimit syscall holder */
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.long sys_olduname
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.long sys_umask /* 60 */
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.long sys_chroot
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.long sys_ustat
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.long sys_dup2
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.long sys_getppid
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.long sys_getpgrp /* 65 */
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.long sys_setsid
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.long sys_sigaction
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.long sys_sgetmask
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.long sys_ssetmask
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.long sys_setreuid /* 70 */
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.long sys_setregid
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.long ppc_sigsuspend
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.long sys_sigpending
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.long sys_sethostname
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.long sys_setrlimit /* 75 */
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.long sys_old_getrlimit
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.long sys_getrusage
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.long sys_gettimeofday
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.long sys_settimeofday
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.long sys_getgroups /* 80 */
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.long sys_setgroups
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.long ppc_select
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.long sys_symlink
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.long sys_lstat
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.long sys_readlink /* 85 */
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.long sys_uselib
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.long sys_swapon
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.long sys_reboot
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.long old_readdir
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.long sys_mmap /* 90 */
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.long sys_munmap
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.long sys_truncate
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.long sys_ftruncate
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.long sys_fchmod
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.long sys_fchown /* 95 */
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.long sys_getpriority
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.long sys_setpriority
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.long sys_ni_syscall /* old profil syscall holder */
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.long sys_statfs
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.long sys_fstatfs /* 100 */
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.long sys_ni_syscall
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.long sys_socketcall
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.long sys_syslog
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.long sys_setitimer
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.long sys_getitimer /* 105 */
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.long sys_newstat
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.long sys_newlstat
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.long sys_newfstat
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.long sys_uname
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.long sys_ni_syscall /* 110 */
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.long sys_vhangup
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.long sys_ni_syscall /* old 'idle' syscall */
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.long sys_ni_syscall
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.long sys_wait4
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.long sys_swapoff /* 115 */
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.long sys_sysinfo
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.long sys_ipc
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.long sys_fsync
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.long sys_sigreturn
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.long ppc_clone /* 120 */
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.long sys_setdomainname
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.long sys_newuname
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.long sys_ni_syscall
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.long sys_adjtimex
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.long sys_mprotect /* 125 */
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.long sys_sigprocmask
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.long sys_ni_syscall /* old sys_create_module */
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.long sys_init_module
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.long sys_delete_module
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.long sys_ni_syscall /* old sys_get_kernel_syms */ /* 130 */
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.long sys_quotactl
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.long sys_getpgid
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.long sys_fchdir
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.long sys_bdflush
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.long sys_sysfs /* 135 */
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.long sys_personality
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.long sys_ni_syscall /* for afs_syscall */
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.long sys_setfsuid
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.long sys_setfsgid
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.long sys_llseek /* 140 */
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.long sys_getdents
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.long ppc_select
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.long sys_flock
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.long sys_msync
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.long sys_readv /* 145 */
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.long sys_writev
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.long sys_getsid
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.long sys_fdatasync
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.long sys_sysctl
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.long sys_mlock /* 150 */
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.long sys_munlock
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.long sys_mlockall
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.long sys_munlockall
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.long sys_sched_setparam
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.long sys_sched_getparam /* 155 */
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.long sys_sched_setscheduler
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.long sys_sched_getscheduler
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.long sys_sched_yield
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.long sys_sched_get_priority_max
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.long sys_sched_get_priority_min /* 160 */
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.long sys_sched_rr_get_interval
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.long sys_nanosleep
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.long sys_mremap
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.long sys_setresuid
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.long sys_getresuid /* 165 */
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.long sys_ni_syscall /* old sys_query_module */
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.long sys_poll
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.long sys_nfsservctl
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.long sys_setresgid
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.long sys_getresgid /* 170 */
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.long sys_prctl
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.long sys_rt_sigreturn
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.long sys_rt_sigaction
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.long sys_rt_sigprocmask
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.long sys_rt_sigpending /* 175 */
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.long sys_rt_sigtimedwait
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.long sys_rt_sigqueueinfo
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.long ppc_rt_sigsuspend
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.long sys_pread64
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.long sys_pwrite64 /* 180 */
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.long sys_chown
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.long sys_getcwd
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.long sys_capget
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.long sys_capset
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.long sys_sigaltstack /* 185 */
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.long sys_sendfile
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.long sys_ni_syscall /* streams1 */
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.long sys_ni_syscall /* streams2 */
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.long ppc_vfork
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.long sys_getrlimit /* 190 */
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.long sys_readahead
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.long sys_mmap2
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.long sys_truncate64
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.long sys_ftruncate64
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.long sys_stat64 /* 195 */
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.long sys_lstat64
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.long sys_fstat64
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.long sys_pciconfig_read
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.long sys_pciconfig_write
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.long sys_pciconfig_iobase /* 200 */
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.long sys_ni_syscall /* 201 - reserved - MacOnLinux - new */
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.long sys_getdents64
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.long sys_pivot_root
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.long sys_fcntl64
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.long sys_madvise /* 205 */
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.long sys_mincore
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.long sys_gettid
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.long sys_tkill
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.long sys_setxattr
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.long sys_lsetxattr /* 210 */
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.long sys_fsetxattr
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.long sys_getxattr
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.long sys_lgetxattr
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.long sys_fgetxattr
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.long sys_listxattr /* 215 */
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.long sys_llistxattr
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.long sys_flistxattr
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.long sys_removexattr
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.long sys_lremovexattr
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.long sys_fremovexattr /* 220 */
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.long sys_futex
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.long sys_sched_setaffinity
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.long sys_sched_getaffinity
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.long sys_ni_syscall
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.long sys_ni_syscall /* 225 - reserved for Tux */
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.long sys_sendfile64
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.long sys_io_setup
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.long sys_io_destroy
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.long sys_io_getevents
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.long sys_io_submit /* 230 */
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.long sys_io_cancel
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.long sys_set_tid_address
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.long sys_fadvise64
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.long sys_exit_group
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.long sys_lookup_dcookie /* 235 */
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.long sys_epoll_create
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.long sys_epoll_ctl
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.long sys_epoll_wait
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.long sys_remap_file_pages
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.long sys_timer_create /* 240 */
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.long sys_timer_settime
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.long sys_timer_gettime
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.long sys_timer_getoverrun
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.long sys_timer_delete
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.long sys_clock_settime /* 245 */
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.long sys_clock_gettime
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.long sys_clock_getres
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.long sys_clock_nanosleep
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.long ppc_swapcontext
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.long sys_tgkill /* 250 */
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.long sys_utimes
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.long sys_statfs64
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.long sys_fstatfs64
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.long ppc_fadvise64_64
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.long sys_ni_syscall /* 255 - rtas (used on ppc64) */
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.long sys_debug_setcontext
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.long sys_ni_syscall /* 257 reserved for vserver */
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.long sys_ni_syscall /* 258 reserved for new sys_remap_file_pages */
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.long sys_ni_syscall /* 259 reserved for new sys_mbind */
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.long sys_ni_syscall /* 260 reserved for new sys_get_mempolicy */
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.long sys_ni_syscall /* 261 reserved for new sys_set_mempolicy */
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.long sys_mq_open
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.long sys_mq_unlink
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.long sys_mq_timedsend
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.long sys_mq_timedreceive /* 265 */
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.long sys_mq_notify
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.long sys_mq_getsetattr
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.long sys_kexec_load
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.long sys_add_key
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.long sys_request_key /* 270 */
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.long sys_keyctl
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.long sys_waitid
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.long sys_ioprio_set
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.long sys_ioprio_get
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.long sys_inotify_init /* 275 */
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.long sys_inotify_add_watch
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.long sys_inotify_rm_watch
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