cd7240c0b9
TSC's get reset after suspend/resume (even on cpu's with invariant TSC which runs at a constant rate across ACPI P-, C- and T-states). And in some systems BIOS seem to reinit TSC to arbitrary large value (still sync'd across cpu's) during resume. This leads to a scenario of scheduler rq->clock (sched_clock_cpu()) less than rq->age_stamp (introduced in 2.6.32). This leads to a big value returned by scale_rt_power() and the resulting big group power set by the update_group_power() is causing improper load balancing between busy and idle cpu's after suspend/resume. This resulted in multi-threaded workloads (like kernel-compilation) go slower after suspend/resume cycle on core i5 laptops. Fix this by recomputing cyc2ns_offset's during resume, so that sched_clock() continues from the point where it was left off during suspend. Reported-by: Florian Pritz <flo@xssn.at> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: <stable@kernel.org> # [v2.6.32+] Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1282262618.2675.24.camel@sbsiddha-MOBL3.sc.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
|
|
* x86 TSC related functions
|
|
*/
|
|
#ifndef _ASM_X86_TSC_H
|
|
#define _ASM_X86_TSC_H
|
|
|
|
#include <asm/processor.h>
|
|
|
|
#define NS_SCALE 10 /* 2^10, carefully chosen */
|
|
#define US_SCALE 32 /* 2^32, arbitralrily chosen */
|
|
|
|
/*
|
|
* Standard way to access the cycle counter.
|
|
*/
|
|
typedef unsigned long long cycles_t;
|
|
|
|
extern unsigned int cpu_khz;
|
|
extern unsigned int tsc_khz;
|
|
|
|
extern void disable_TSC(void);
|
|
|
|
static inline cycles_t get_cycles(void)
|
|
{
|
|
unsigned long long ret = 0;
|
|
|
|
#ifndef CONFIG_X86_TSC
|
|
if (!cpu_has_tsc)
|
|
return 0;
|
|
#endif
|
|
rdtscll(ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static __always_inline cycles_t vget_cycles(void)
|
|
{
|
|
/*
|
|
* We only do VDSOs on TSC capable CPUs, so this shouldnt
|
|
* access boot_cpu_data (which is not VDSO-safe):
|
|
*/
|
|
#ifndef CONFIG_X86_TSC
|
|
if (!cpu_has_tsc)
|
|
return 0;
|
|
#endif
|
|
return (cycles_t)__native_read_tsc();
|
|
}
|
|
|
|
extern void tsc_init(void);
|
|
extern void mark_tsc_unstable(char *reason);
|
|
extern int unsynchronized_tsc(void);
|
|
extern int check_tsc_unstable(void);
|
|
extern unsigned long native_calibrate_tsc(void);
|
|
|
|
/*
|
|
* Boot-time check whether the TSCs are synchronized across
|
|
* all CPUs/cores:
|
|
*/
|
|
extern void check_tsc_sync_source(int cpu);
|
|
extern void check_tsc_sync_target(void);
|
|
|
|
extern int notsc_setup(char *);
|
|
extern void save_sched_clock_state(void);
|
|
extern void restore_sched_clock_state(void);
|
|
|
|
#endif /* _ASM_X86_TSC_H */
|