180 lines
5.0 KiB
C
180 lines
5.0 KiB
C
// include/asm-arm/mach-omap/usb.h
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#ifndef __ASM_ARCH_OMAP_USB_H
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#define __ASM_ARCH_OMAP_USB_H
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/usb/musb.h>
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#define OMAP3_HS_USB_PORTS 3
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enum usbhs_omap_port_mode {
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OMAP_USBHS_PORT_MODE_UNUSED,
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OMAP_EHCI_PORT_MODE_PHY,
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OMAP_EHCI_PORT_MODE_TLL,
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OMAP_EHCI_PORT_MODE_HSIC,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
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};
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struct usbhs_omap_board_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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/* have to be valid if phy_reset is true and portx is in phy mode */
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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/* Set this to true for ES2.x silicon */
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unsigned es2_compatibility:1;
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unsigned phy_reset:1;
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/*
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* Regulators for USB PHYs.
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* Each PHY can have a separate regulator.
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*/
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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};
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#ifdef CONFIG_ARCH_OMAP2PLUS
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struct ehci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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unsigned phy_reset:1;
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};
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struct ohci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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unsigned es2_compatibility:1;
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};
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struct usbhs_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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struct ehci_hcd_omap_platform_data *ehci_data;
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struct ohci_hcd_omap_platform_data *ohci_data;
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};
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struct usbtll_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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};
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/*-------------------------------------------------------------------------*/
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struct omap_musb_board_data {
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u8 interface_type;
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u8 mode;
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u16 power;
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unsigned extvbus:1;
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void (*set_phy_power)(u8 on);
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void (*clear_irq)(void);
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void (*set_mode)(u8 mode);
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void (*reset)(void);
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};
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enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
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extern void usb_musb_init(struct omap_musb_board_data *board_data);
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extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
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extern int omap_tll_enable(void);
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extern int omap_tll_disable(void);
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extern int omap4430_phy_power(struct device *dev, int ID, int on);
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extern int omap4430_phy_set_clk(struct device *dev, int on);
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extern int omap4430_phy_init(struct device *dev);
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extern int omap4430_phy_exit(struct device *dev);
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extern int omap4430_phy_suspend(struct device *dev, int suspend);
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#endif
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extern void am35x_musb_reset(void);
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extern void am35x_musb_phy_power(u8 on);
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extern void am35x_musb_clear_irq(void);
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extern void am35x_set_mode(u8 musb_mode);
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extern void ti81xx_musb_phy_power(u8 on);
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/* AM35x */
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/* USB 2.0 PHY Control */
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#define CONF2_PHY_GPIOMODE (1 << 23)
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#define CONF2_OTGMODE (3 << 14)
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#define CONF2_NO_OVERRIDE (0 << 14)
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#define CONF2_FORCE_HOST (1 << 14)
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#define CONF2_FORCE_DEVICE (2 << 14)
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#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
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#define CONF2_SESENDEN (1 << 13)
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#define CONF2_VBDTCTEN (1 << 12)
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#define CONF2_REFFREQ_24MHZ (2 << 8)
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#define CONF2_REFFREQ_26MHZ (7 << 8)
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#define CONF2_REFFREQ_13MHZ (6 << 8)
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#define CONF2_REFFREQ (0xf << 8)
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#define CONF2_PHYCLKGD (1 << 7)
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#define CONF2_VBUSSENSE (1 << 6)
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#define CONF2_PHY_PLLON (1 << 5)
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#define CONF2_RESET (1 << 4)
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#define CONF2_PHYPWRDN (1 << 3)
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#define CONF2_OTGPWRDN (1 << 2)
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#define CONF2_DATPOL (1 << 1)
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/* TI81XX specific definitions */
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#define USBCTRL0 0x620
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#define USBSTAT0 0x624
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/* TI816X PHY controls bits */
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#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
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#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
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/* TI814X PHY controls bits */
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#define USBPHY_CM_PWRDN (1 << 0)
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#define USBPHY_OTG_PWRDN (1 << 1)
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#define USBPHY_CHGDET_DIS (1 << 2)
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#define USBPHY_CHGDET_RSTRT (1 << 3)
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#define USBPHY_SRCONDM (1 << 4)
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#define USBPHY_SINKONDP (1 << 5)
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#define USBPHY_CHGISINK_EN (1 << 6)
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#define USBPHY_CHGVSRC_EN (1 << 7)
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#define USBPHY_DMPULLUP (1 << 8)
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#define USBPHY_DPPULLUP (1 << 9)
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#define USBPHY_CDET_EXTCTL (1 << 10)
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#define USBPHY_GPIO_MODE (1 << 12)
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#define USBPHY_DPOPBUFCTL (1 << 13)
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#define USBPHY_DMOPBUFCTL (1 << 14)
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#define USBPHY_DPINPUT (1 << 15)
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#define USBPHY_DMINPUT (1 << 16)
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#define USBPHY_DPGPIO_PD (1 << 17)
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#define USBPHY_DMGPIO_PD (1 << 18)
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#define USBPHY_OTGVDET_EN (1 << 19)
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#define USBPHY_OTGSESSEND_EN (1 << 20)
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#define USBPHY_DATA_POLARITY (1 << 23)
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#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
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u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
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u32 omap1_usb1_init(unsigned nwires);
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u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
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#else
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static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
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{
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return 0;
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}
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static inline u32 omap1_usb1_init(unsigned nwires)
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{
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return 0;
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}
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static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
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{
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return 0;
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}
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#endif
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#endif /* __ASM_ARCH_OMAP_USB_H */
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