a875c01944
Always-on local APIC timer (ARAT) has been introduced to Medfield, along with the platform APB timers we have more timer configuration options between Moorestown and Medfield. This patch adds run-time detection of avaiable timer features so that we can treat Medfield as a variant of Moorestown and set up the optimal timer options for each platform. i.e. Medfield: per cpu always-on local APIC timer Moorestown: per cpu APB timer Manual override is possible via cmdline option x86_mrst_timer. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> LKML-Reference: <1274295685-6774-4-git-send-email-jacob.jun.pan@linux.intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
/*
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* apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare
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*
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* (C) Copyright 2009 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* Note:
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*/
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#ifndef ASM_X86_APBT_H
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#define ASM_X86_APBT_H
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#include <linux/sfi.h>
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#ifdef CONFIG_APB_TIMER
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/* Langwell DW APB timer registers */
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#define APBTMR_N_LOAD_COUNT 0x00
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#define APBTMR_N_CURRENT_VALUE 0x04
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#define APBTMR_N_CONTROL 0x08
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#define APBTMR_N_EOI 0x0c
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#define APBTMR_N_INT_STATUS 0x10
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#define APBTMRS_INT_STATUS 0xa0
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#define APBTMRS_EOI 0xa4
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#define APBTMRS_RAW_INT_STATUS 0xa8
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#define APBTMRS_COMP_VERSION 0xac
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#define APBTMRS_REG_SIZE 0x14
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/* register bits */
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#define APBTMR_CONTROL_ENABLE (1<<0)
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#define APBTMR_CONTROL_MODE_PERIODIC (1<<1) /*1: periodic 0:free running */
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#define APBTMR_CONTROL_INT (1<<2)
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/* default memory mapped register base */
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#define LNW_SCU_ADDR 0xFF100000
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#define LNW_EXT_TIMER_OFFSET 0x1B800
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#define APBT_DEFAULT_BASE (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)
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#define LNW_EXT_TIMER_PGOFFSET 0x800
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/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
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#define APBT_MAX_FREQ 50
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#define APBT_MIN_FREQ 1
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#define APBT_MMAP_SIZE 1024
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#define APBT_DEV_USED 1
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extern void apbt_time_init(void);
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extern struct clock_event_device *global_clock_event;
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extern unsigned long apbt_quick_calibrate(void);
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extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
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extern void apbt_setup_secondary_clock(void);
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extern unsigned int boot_cpu_id;
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extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
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extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
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extern int sfi_mtimer_num;
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#else /* CONFIG_APB_TIMER */
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static inline unsigned long apbt_quick_calibrate(void) {return 0; }
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static inline void apbt_time_init(void) {return 0; }
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#endif
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#endif /* ASM_X86_APBT_H */
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