7e8d5cd93f
The Freescale MX27 and MX31 SoCs have a EHCI controller onboard. The controller is capable of USB on the go. This patch adds a driver to support all three of them. Users have to pass details about serial interface configuration in the platform data. The USB OTG core used here is the ARC core, so the driver should be renamed and probably be merged with ehci-fsl.c eventually. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/mxc_ehci.h>
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#define USBCTRL_OTGBASE_OFFSET 0x600
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#define MX31_OTG_SIC_SHIFT 29
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#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT)
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#define MX31_OTG_PM_BIT (1 << 24)
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#define MX31_H2_SIC_SHIFT 21
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#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT)
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#define MX31_H2_PM_BIT (1 << 16)
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#define MX31_H2_DT_BIT (1 << 5)
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#define MX31_H1_SIC_SHIFT 13
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#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT)
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#define MX31_H1_PM_BIT (1 << 8)
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#define MX31_H1_DT_BIT (1 << 4)
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int mxc_set_usbcontrol(int port, unsigned int flags)
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{
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unsigned int v;
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if (cpu_is_mx31()) {
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v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_OTG_SIC_SHIFT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v |= MX31_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H1_SIC_SHIFT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v |= MX31_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H1_DT_BIT;
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break;
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case 2: /* H2 port */
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v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H2_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H2_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H2_DT_BIT;
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break;
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}
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writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR +
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USBCTRL_OTGBASE_OFFSET));
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return 0;
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}
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printk(KERN_WARNING
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"%s() unable to setup USBCONTROL for this CPU\n", __func__);
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return -EINVAL;
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}
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EXPORT_SYMBOL(mxc_set_usbcontrol);
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