![Thomas Gleixner](/assets/img/avatar_default.png)
The PIT has no dedicated mode for shut down. The only way to disable PIT is to put it into one shot mode. AMD implementations of PIT on Geode (also observed on Cyrix) are confused by an "empty" transition from CLOCK_EVT_MODE_UNUSED to CLOCK_EVT_MODE_SHUTDOWN, which puts the PIT into one shot mode momentarily. I realized after staring helpless at the bug report http://bugzilla.kernel.org/show_bug.cgi?id=8027 for quite a while, that the only change, which might influence the bogomips calibration, is the above transition during the PIT initialization. Avoiding the unnecessary switch to oneshot and later to periodic mode fixes the weird bogomips value and also the resulting slowness. The fix is confirmed on OLPC and another Geode based box. Note: this is unrelated to the Dual Core problem discussed here: http://lkml.org/lkml/2007/3/17/48 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
207 lines
5.4 KiB
C
207 lines
5.4 KiB
C
/*
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* i8253.c 8253/PIT functions
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*
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*/
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#include <linux/clockchips.h>
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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#include <linux/sysdev.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <asm/smp.h>
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#include <asm/delay.h>
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#include <asm/i8253.h>
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#include <asm/io.h>
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#include "io_ports.h"
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DEFINE_SPINLOCK(i8253_lock);
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EXPORT_SYMBOL(i8253_lock);
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/*
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* HPET replaces the PIT, when enabled. So we need to know, which of
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* the two timers is used
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*/
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struct clock_event_device *global_clock_event;
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/*
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* Initialize the PIT timer.
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*
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* This is also called after resume to bring the PIT into operation again.
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*/
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static void init_pit_timer(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8253_lock, flags);
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* binary, mode 2, LSB/MSB, ch 0 */
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outb_p(0x34, PIT_MODE);
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udelay(10);
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outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
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udelay(10);
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outb(LATCH >> 8 , PIT_CH0); /* MSB */
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break;
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/*
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* Avoid unnecessary state transitions, as it confuses
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* Geode / Cyrix based boxen.
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*/
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case CLOCK_EVT_MODE_SHUTDOWN:
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if (evt->mode == CLOCK_EVT_MODE_UNUSED)
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (evt->mode == CLOCK_EVT_MODE_SHUTDOWN)
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* One shot setup */
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outb_p(0x38, PIT_MODE);
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udelay(10);
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break;
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}
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spin_unlock_irqrestore(&i8253_lock, flags);
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}
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/*
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* Program the next event in oneshot mode
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*
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* Delta is given in PIT ticks
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*/
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static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8253_lock, flags);
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outb_p(delta & 0xff , PIT_CH0); /* LSB */
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outb(delta >> 8 , PIT_CH0); /* MSB */
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spin_unlock_irqrestore(&i8253_lock, flags);
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return 0;
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}
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/*
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* On UP the PIT can serve all of the possible timer functions. On SMP systems
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* it can be solely used for the global tick.
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*
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* The profiling and update capabilites are switched off once the local apic is
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* registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
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* !using_apic_timer decisions in do_timer_interrupt_hook()
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*/
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struct clock_event_device pit_clockevent = {
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.name = "pit",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = init_pit_timer,
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.set_next_event = pit_next_event,
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.shift = 32,
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.irq = 0,
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};
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/*
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* Initialize the conversion factor and the min/max deltas of the clock event
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* structure and register the clock event source with the framework.
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*/
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void __init setup_pit_timer(void)
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{
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/*
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* Start pit with the boot cpu mask and make it global after the
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* IO_APIC has been initialized.
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*/
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pit_clockevent.cpumask = cpumask_of_cpu(0);
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pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
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pit_clockevent.max_delta_ns =
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clockevent_delta2ns(0x7FFF, &pit_clockevent);
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pit_clockevent.min_delta_ns =
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clockevent_delta2ns(0xF, &pit_clockevent);
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clockevents_register_device(&pit_clockevent);
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global_clock_event = &pit_clockevent;
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}
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/*
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* Since the PIT overflows every tick, its not very useful
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* to just read by itself. So use jiffies to emulate a free
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* running counter:
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*/
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static cycle_t pit_read(void)
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{
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unsigned long flags;
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int count;
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u32 jifs;
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static int old_count;
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static u32 old_jifs;
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spin_lock_irqsave(&i8253_lock, flags);
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/*
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* Although our caller may have the read side of xtime_lock,
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* this is now a seqlock, and we are cheating in this routine
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* by having side effects on state that we cannot undo if
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* there is a collision on the seqlock and our caller has to
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* retry. (Namely, old_jifs and old_count.) So we must treat
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* jiffies as volatile despite the lock. We read jiffies
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* before latching the timer count to guarantee that although
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* the jiffies value might be older than the count (that is,
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* the counter may underflow between the last point where
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* jiffies was incremented and the point where we latch the
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* count), it cannot be newer.
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*/
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jifs = jiffies;
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outb_p(0x00, PIT_MODE); /* latch the count ASAP */
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count = inb_p(PIT_CH0); /* read the latched count */
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count |= inb_p(PIT_CH0) << 8;
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/* VIA686a test code... reset the latch if count > max + 1 */
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if (count > LATCH) {
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outb_p(0x34, PIT_MODE);
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outb_p(LATCH & 0xff, PIT_CH0);
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outb(LATCH >> 8, PIT_CH0);
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count = LATCH - 1;
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}
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/*
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* It's possible for count to appear to go the wrong way for a
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* couple of reasons:
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*
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* 1. The timer counter underflows, but we haven't handled the
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* resulting interrupt and incremented jiffies yet.
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* 2. Hardware problem with the timer, not giving us continuous time,
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* the counter does small "jumps" upwards on some Pentium systems,
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* (see c't 95/10 page 335 for Neptun bug.)
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*
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* Previous attempts to handle these cases intelligently were
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* buggy, so we just do the simple thing now.
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*/
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if (count > old_count && jifs == old_jifs) {
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count = old_count;
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}
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old_count = count;
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old_jifs = jifs;
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spin_unlock_irqrestore(&i8253_lock, flags);
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count = (LATCH - 1) - count;
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return (cycle_t)(jifs * LATCH) + count;
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}
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static struct clocksource clocksource_pit = {
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.name = "pit",
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.rating = 110,
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.read = pit_read,
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.mask = CLOCKSOURCE_MASK(32),
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.mult = 0,
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.shift = 20,
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};
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static int __init init_pit_clocksource(void)
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{
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if (num_possible_cpus() > 1) /* PIT does not scale! */
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return 0;
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clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
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return clocksource_register(&clocksource_pit);
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}
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arch_initcall(init_pit_clocksource);
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