![Eric W. Biederman](/assets/img/avatar_default.png)
The per cpu nmi watchdog timer is based on an event counter. idle cpus don't generate events so the NMI watchdog doesn't fire and the test to see if the watchdog is working fails. - Add nmi_cpu_busy so idle cpus don't mess up the test. - kmalloc prev_nmi_count to keep kernel stack usage bounded. - Improve the error message on failure so there is enough information to debug problems. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
622 lines
15 KiB
C
622 lines
15 KiB
C
/*
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* linux/arch/i386/nmi.c
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*
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* NMI watchdog support on APIC systems
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*
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* Started by Ingo Molnar <mingo@redhat.com>
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*
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* Fixes:
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* Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
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* Mikael Pettersson : Power Management for local APIC NMI watchdog.
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* Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
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* Pavel Machek and
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* Mikael Pettersson : PM converted to driver model. Disable/enable API.
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*/
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#include <linux/config.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/mc146818rtc.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/nmi.h>
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#include <linux/sysdev.h>
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#include <linux/sysctl.h>
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#include <asm/smp.h>
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#include <asm/div64.h>
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#include <asm/nmi.h>
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#include "mach_traps.h"
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unsigned int nmi_watchdog = NMI_NONE;
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extern int unknown_nmi_panic;
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static unsigned int nmi_hz = HZ;
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static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
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static unsigned int nmi_p4_cccr_val;
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extern void show_registers(struct pt_regs *regs);
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/*
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* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
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* - it may be reserved by some other driver, or not
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* - when not reserved by some other driver, it may be used for
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* the NMI watchdog, or not
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*
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* This is maintained separately from nmi_active because the NMI
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* watchdog may also be driven from the I/O APIC timer.
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*/
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static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
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static unsigned int lapic_nmi_owner;
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#define LAPIC_NMI_WATCHDOG (1<<0)
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#define LAPIC_NMI_RESERVED (1<<1)
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/* nmi_active:
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* +1: the lapic NMI watchdog is active, but can be disabled
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* 0: the lapic NMI watchdog has not been set up, and cannot
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* be enabled
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* -1: the lapic NMI watchdog is disabled, but can be enabled
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*/
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int nmi_active;
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#define K7_EVNTSEL_ENABLE (1 << 22)
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#define K7_EVNTSEL_INT (1 << 20)
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#define K7_EVNTSEL_OS (1 << 17)
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#define K7_EVNTSEL_USR (1 << 16)
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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#define P6_EVNTSEL0_ENABLE (1 << 22)
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#define P6_EVNTSEL_INT (1 << 20)
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#define P6_EVNTSEL_OS (1 << 17)
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#define P6_EVNTSEL_USR (1 << 16)
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#define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
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#define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
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#define MSR_P4_MISC_ENABLE 0x1A0
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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#define MSR_P4_PERFCTR0 0x300
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#define MSR_P4_CCCR0 0x360
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#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
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#define P4_ESCR_OS (1<<3)
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#define P4_ESCR_USR (1<<2)
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#define P4_CCCR_OVF_PMI0 (1<<26)
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#define P4_CCCR_OVF_PMI1 (1<<27)
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#define P4_CCCR_THRESHOLD(N) ((N)<<20)
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#define P4_CCCR_COMPLEMENT (1<<19)
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#define P4_CCCR_COMPARE (1<<18)
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#define P4_CCCR_REQUIRED (3<<16)
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#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
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#define P4_CCCR_ENABLE (1<<12)
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/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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CRU_ESCR0 (with any non-null event selector) through a complemented
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max threshold. [IA32-Vol3, Section 14.9.9] */
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#define MSR_P4_IQ_COUNTER0 0x30C
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#define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
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#define P4_NMI_IQ_CCCR0 \
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(P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
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P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
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#ifdef CONFIG_SMP
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/* The performance counters used by NMI_LOCAL_APIC don't trigger when
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* the CPU is idle. To make sure the NMI watchdog really ticks on all
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* CPUs during the test make them busy.
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*/
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static __init void nmi_cpu_busy(void *data)
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{
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volatile int *endflag = data;
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local_irq_enable();
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/* Intentionally don't use cpu_relax here. This is
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to make sure that the performance counter really ticks,
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even if there is a simulator or similar that catches the
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pause instruction. On a real HT machine this is fine because
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all other CPUs are busy with "useless" delay loops and don't
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care if they get somewhat less cycles. */
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while (*endflag == 0)
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barrier();
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}
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#endif
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static int __init check_nmi_watchdog(void)
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{
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volatile int endflag = 0;
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unsigned int *prev_nmi_count;
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int cpu;
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if (nmi_watchdog == NMI_NONE)
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return 0;
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prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
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if (!prev_nmi_count)
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return -1;
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printk(KERN_INFO "Testing NMI watchdog ... ");
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if (nmi_watchdog == NMI_LOCAL_APIC)
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smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
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for (cpu = 0; cpu < NR_CPUS; cpu++)
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prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
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local_irq_enable();
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mdelay((10*1000)/nmi_hz); // wait 10 ticks
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for (cpu = 0; cpu < NR_CPUS; cpu++) {
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#ifdef CONFIG_SMP
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/* Check cpu_callin_map here because that is set
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after the timer is started. */
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if (!cpu_isset(cpu, cpu_callin_map))
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continue;
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#endif
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if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
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endflag = 1;
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printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
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cpu,
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prev_nmi_count[cpu],
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nmi_count(cpu));
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nmi_active = 0;
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lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
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kfree(prev_nmi_count);
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return -1;
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}
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}
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endflag = 1;
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printk("OK.\n");
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/* now that we know it works we can reduce NMI frequency to
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something more reasonable; makes a difference in some configs */
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if (nmi_watchdog == NMI_LOCAL_APIC)
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nmi_hz = 1;
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kfree(prev_nmi_count);
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return 0;
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}
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/* This needs to happen later in boot so counters are working */
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late_initcall(check_nmi_watchdog);
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static int __init setup_nmi_watchdog(char *str)
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{
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int nmi;
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get_option(&str, &nmi);
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if (nmi >= NMI_INVALID)
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return 0;
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if (nmi == NMI_NONE)
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nmi_watchdog = nmi;
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/*
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* If any other x86 CPU has a local APIC, then
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* please test the NMI stuff there and send me the
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* missing bits. Right now Intel P6/P4 and AMD K7 only.
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*/
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if ((nmi == NMI_LOCAL_APIC) &&
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(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
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(boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
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nmi_watchdog = nmi;
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if ((nmi == NMI_LOCAL_APIC) &&
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(boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
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(boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
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nmi_watchdog = nmi;
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/*
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* We can enable the IO-APIC watchdog
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* unconditionally.
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*/
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if (nmi == NMI_IO_APIC) {
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nmi_active = 1;
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nmi_watchdog = nmi;
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}
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return 1;
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}
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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static void disable_lapic_nmi_watchdog(void)
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{
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if (nmi_active <= 0)
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return;
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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wrmsr(MSR_K7_EVNTSEL0, 0, 0);
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break;
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case X86_VENDOR_INTEL:
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switch (boot_cpu_data.x86) {
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case 6:
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if (boot_cpu_data.x86_model > 0xd)
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break;
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wrmsr(MSR_P6_EVNTSEL0, 0, 0);
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break;
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case 15:
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if (boot_cpu_data.x86_model > 0x4)
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break;
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wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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break;
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}
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break;
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}
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nmi_active = -1;
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/* tell do_nmi() and others that we're not active any more */
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nmi_watchdog = 0;
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}
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static void enable_lapic_nmi_watchdog(void)
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{
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if (nmi_active < 0) {
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nmi_watchdog = NMI_LOCAL_APIC;
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setup_apic_nmi_watchdog();
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}
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}
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int reserve_lapic_nmi(void)
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{
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unsigned int old_owner;
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spin_lock(&lapic_nmi_owner_lock);
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old_owner = lapic_nmi_owner;
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lapic_nmi_owner |= LAPIC_NMI_RESERVED;
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spin_unlock(&lapic_nmi_owner_lock);
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if (old_owner & LAPIC_NMI_RESERVED)
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return -EBUSY;
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if (old_owner & LAPIC_NMI_WATCHDOG)
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disable_lapic_nmi_watchdog();
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return 0;
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}
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void release_lapic_nmi(void)
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{
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unsigned int new_owner;
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spin_lock(&lapic_nmi_owner_lock);
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new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
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lapic_nmi_owner = new_owner;
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spin_unlock(&lapic_nmi_owner_lock);
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if (new_owner & LAPIC_NMI_WATCHDOG)
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enable_lapic_nmi_watchdog();
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}
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void disable_timer_nmi_watchdog(void)
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{
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if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
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return;
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unset_nmi_callback();
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nmi_active = -1;
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nmi_watchdog = NMI_NONE;
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}
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void enable_timer_nmi_watchdog(void)
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{
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if (nmi_active < 0) {
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nmi_watchdog = NMI_IO_APIC;
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touch_nmi_watchdog();
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nmi_active = 1;
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}
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}
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#ifdef CONFIG_PM
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static int nmi_pm_active; /* nmi_active before suspend */
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static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
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{
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nmi_pm_active = nmi_active;
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disable_lapic_nmi_watchdog();
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return 0;
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}
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static int lapic_nmi_resume(struct sys_device *dev)
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{
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if (nmi_pm_active > 0)
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enable_lapic_nmi_watchdog();
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return 0;
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}
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static struct sysdev_class nmi_sysclass = {
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set_kset_name("lapic_nmi"),
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.resume = lapic_nmi_resume,
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.suspend = lapic_nmi_suspend,
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};
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static struct sys_device device_lapic_nmi = {
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.id = 0,
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.cls = &nmi_sysclass,
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};
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static int __init init_lapic_nmi_sysfs(void)
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{
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int error;
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if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
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return 0;
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error = sysdev_class_register(&nmi_sysclass);
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if (!error)
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error = sysdev_register(&device_lapic_nmi);
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return error;
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}
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/* must come after the local APIC's device_initcall() */
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late_initcall(init_lapic_nmi_sysfs);
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#endif /* CONFIG_PM */
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/*
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* Activate the NMI watchdog via the local APIC.
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* Original code written by Keith Owens.
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*/
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static void clear_msr_range(unsigned int base, unsigned int n)
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{
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unsigned int i;
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for(i = 0; i < n; ++i)
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wrmsr(base+i, 0, 0);
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}
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static inline void write_watchdog_counter(const char *descr)
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{
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u64 count = (u64)cpu_khz * 1000;
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do_div(count, nmi_hz);
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if(descr)
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Dprintk("setting %s to -0x%08Lx\n", descr, count);
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wrmsrl(nmi_perfctr_msr, 0 - count);
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}
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static void setup_k7_watchdog(void)
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{
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unsigned int evntsel;
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nmi_perfctr_msr = MSR_K7_PERFCTR0;
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clear_msr_range(MSR_K7_EVNTSEL0, 4);
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clear_msr_range(MSR_K7_PERFCTR0, 4);
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evntsel = K7_EVNTSEL_INT
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| K7_EVNTSEL_OS
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| K7_EVNTSEL_USR
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| K7_NMI_EVENT;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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write_watchdog_counter("K7_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= K7_EVNTSEL_ENABLE;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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}
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static void setup_p6_watchdog(void)
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{
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unsigned int evntsel;
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nmi_perfctr_msr = MSR_P6_PERFCTR0;
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clear_msr_range(MSR_P6_EVNTSEL0, 2);
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clear_msr_range(MSR_P6_PERFCTR0, 2);
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evntsel = P6_EVNTSEL_INT
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| P6_EVNTSEL_OS
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| P6_EVNTSEL_USR
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| P6_NMI_EVENT;
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wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
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write_watchdog_counter("P6_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= P6_EVNTSEL0_ENABLE;
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wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
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}
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static int setup_p4_watchdog(void)
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{
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unsigned int misc_enable, dummy;
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rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
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if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
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return 0;
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nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
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nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
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#ifdef CONFIG_SMP
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if (smp_num_siblings == 2)
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nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
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#endif
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if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
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clear_msr_range(0x3F1, 2);
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/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
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docs doesn't fully define it, so leave it alone for now. */
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if (boot_cpu_data.x86_model >= 0x3) {
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/* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
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clear_msr_range(0x3A0, 26);
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clear_msr_range(0x3BC, 3);
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} else {
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clear_msr_range(0x3A0, 31);
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}
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clear_msr_range(0x3C0, 6);
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clear_msr_range(0x3C8, 6);
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clear_msr_range(0x3E0, 2);
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clear_msr_range(MSR_P4_CCCR0, 18);
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clear_msr_range(MSR_P4_PERFCTR0, 18);
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wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
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wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
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write_watchdog_counter("P4_IQ_COUNTER0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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return 1;
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}
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void setup_apic_nmi_watchdog (void)
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{
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
|
|
return;
|
|
setup_k7_watchdog();
|
|
break;
|
|
case X86_VENDOR_INTEL:
|
|
switch (boot_cpu_data.x86) {
|
|
case 6:
|
|
if (boot_cpu_data.x86_model > 0xd)
|
|
return;
|
|
|
|
setup_p6_watchdog();
|
|
break;
|
|
case 15:
|
|
if (boot_cpu_data.x86_model > 0x4)
|
|
return;
|
|
|
|
if (!setup_p4_watchdog())
|
|
return;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
|
|
nmi_active = 1;
|
|
}
|
|
|
|
/*
|
|
* the best way to detect whether a CPU has a 'hard lockup' problem
|
|
* is to check it's local APIC timer IRQ counts. If they are not
|
|
* changing then that CPU has some problem.
|
|
*
|
|
* as these watchdog NMI IRQs are generated on every CPU, we only
|
|
* have to check the current processor.
|
|
*
|
|
* since NMIs don't listen to _any_ locks, we have to be extremely
|
|
* careful not to rely on unsafe variables. The printk might lock
|
|
* up though, so we have to break up any console locks first ...
|
|
* [when there will be more tty-related locks, break them up
|
|
* here too!]
|
|
*/
|
|
|
|
static unsigned int
|
|
last_irq_sums [NR_CPUS],
|
|
alert_counter [NR_CPUS];
|
|
|
|
void touch_nmi_watchdog (void)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Just reset the alert counters, (other CPUs might be
|
|
* spinning on locks we hold):
|
|
*/
|
|
for (i = 0; i < NR_CPUS; i++)
|
|
alert_counter[i] = 0;
|
|
|
|
/*
|
|
* Tickle the softlockup detector too:
|
|
*/
|
|
touch_softlockup_watchdog();
|
|
}
|
|
|
|
extern void die_nmi(struct pt_regs *, const char *msg);
|
|
|
|
void nmi_watchdog_tick (struct pt_regs * regs)
|
|
{
|
|
|
|
/*
|
|
* Since current_thread_info()-> is always on the stack, and we
|
|
* always switch the stack NMI-atomically, it's safe to use
|
|
* smp_processor_id().
|
|
*/
|
|
int sum, cpu = smp_processor_id();
|
|
|
|
sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
|
|
|
|
if (last_irq_sums[cpu] == sum) {
|
|
/*
|
|
* Ayiee, looks like this CPU is stuck ...
|
|
* wait a few IRQs (5 seconds) before doing the oops ...
|
|
*/
|
|
alert_counter[cpu]++;
|
|
if (alert_counter[cpu] == 5*nmi_hz)
|
|
/*
|
|
* die_nmi will return ONLY if NOTIFY_STOP happens..
|
|
*/
|
|
die_nmi(regs, "NMI Watchdog detected LOCKUP");
|
|
|
|
last_irq_sums[cpu] = sum;
|
|
alert_counter[cpu] = 0;
|
|
}
|
|
if (nmi_perfctr_msr) {
|
|
if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
|
|
/*
|
|
* P4 quirks:
|
|
* - An overflown perfctr will assert its interrupt
|
|
* until the OVF flag in its CCCR is cleared.
|
|
* - LVTPC is masked on interrupt and must be
|
|
* unmasked by the LVTPC handler.
|
|
*/
|
|
wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
|
}
|
|
else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
|
|
/* Only P6 based Pentium M need to re-unmask
|
|
* the apic vector but it doesn't hurt
|
|
* other P6 variant */
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
|
}
|
|
write_watchdog_counter(NULL);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SYSCTL
|
|
|
|
static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
|
|
{
|
|
unsigned char reason = get_nmi_reason();
|
|
char buf[64];
|
|
|
|
if (!(reason & 0xc0)) {
|
|
sprintf(buf, "NMI received for unknown reason %02x\n", reason);
|
|
die_nmi(regs, buf);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* proc handler for /proc/sys/kernel/unknown_nmi_panic
|
|
*/
|
|
int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
|
|
void __user *buffer, size_t *length, loff_t *ppos)
|
|
{
|
|
int old_state;
|
|
|
|
old_state = unknown_nmi_panic;
|
|
proc_dointvec(table, write, file, buffer, length, ppos);
|
|
if (!!old_state == !!unknown_nmi_panic)
|
|
return 0;
|
|
|
|
if (unknown_nmi_panic) {
|
|
if (reserve_lapic_nmi() < 0) {
|
|
unknown_nmi_panic = 0;
|
|
return -EBUSY;
|
|
} else {
|
|
set_nmi_callback(unknown_nmi_panic_callback);
|
|
}
|
|
} else {
|
|
release_lapic_nmi();
|
|
unset_nmi_callback();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
EXPORT_SYMBOL(nmi_active);
|
|
EXPORT_SYMBOL(nmi_watchdog);
|
|
EXPORT_SYMBOL(reserve_lapic_nmi);
|
|
EXPORT_SYMBOL(release_lapic_nmi);
|
|
EXPORT_SYMBOL(disable_timer_nmi_watchdog);
|
|
EXPORT_SYMBOL(enable_timer_nmi_watchdog);
|