196 lines
5.0 KiB
C
196 lines
5.0 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/gpio.h>
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struct nv50_gpio_priv {
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struct nouveau_gpio base;
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};
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static void
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nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match)
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{
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struct nouveau_bios *bios = nouveau_bios(gpio);
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struct nv50_gpio_priv *priv = (void *)gpio;
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u8 ver, len;
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u16 entry;
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int ent = -1;
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while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
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static const u32 regs[] = { 0xe100, 0xe28c };
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u32 data = nv_ro32(bios, entry);
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u8 line = (data & 0x0000001f);
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u8 func = (data & 0x0000ff00) >> 8;
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u8 defs = !!(data & 0x01000000);
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u8 unk0 = !!(data & 0x02000000);
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u8 unk1 = !!(data & 0x04000000);
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u32 val = (unk1 << 16) | unk0;
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u32 reg = regs[line >> 4]; line &= 0x0f;
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if ( func == DCB_GPIO_UNUSED ||
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(match != DCB_GPIO_UNUSED && match != func))
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continue;
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gpio->set(gpio, 0, func, line, defs);
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nv_mask(priv, reg, 0x00010001 << line, val << line);
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}
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}
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static int
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nv50_gpio_location(int line, u32 *reg, u32 *shift)
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{
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const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
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if (line >= 32)
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return -EINVAL;
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*reg = nv50_gpio_reg[line >> 3];
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*shift = (line & 7) << 2;
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return 0;
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}
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static int
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nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
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{
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u32 reg, shift;
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if (nv50_gpio_location(line, ®, &shift))
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return -EINVAL;
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nv_mask(gpio, reg, 7 << shift, (((dir ^ 1) << 1) | out) << shift);
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return 0;
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}
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static int
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nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
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{
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u32 reg, shift;
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if (nv50_gpio_location(line, ®, &shift))
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return -EINVAL;
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return !!(nv_rd32(gpio, reg) & (4 << shift));
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}
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void
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nv50_gpio_irq_enable(struct nouveau_gpio *gpio, int line, bool on)
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{
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u32 reg = line < 16 ? 0xe050 : 0xe070;
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u32 mask = 0x00010001 << (line & 0xf);
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nv_wr32(gpio, reg + 4, mask);
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nv_mask(gpio, reg + 0, mask, on ? mask : 0);
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}
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void
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nv50_gpio_intr(struct nouveau_subdev *subdev)
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{
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struct nv50_gpio_priv *priv = (void *)subdev;
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u32 intr0, intr1 = 0;
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u32 hi, lo;
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intr0 = nv_rd32(priv, 0xe054) & nv_rd32(priv, 0xe050);
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if (nv_device(priv)->chipset >= 0x90)
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intr1 = nv_rd32(priv, 0xe074) & nv_rd32(priv, 0xe070);
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hi = (intr0 & 0x0000ffff) | (intr1 << 16);
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lo = (intr0 >> 16) | (intr1 & 0xffff0000);
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priv->base.isr_run(&priv->base, 0, hi | lo);
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nv_wr32(priv, 0xe054, intr0);
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if (nv_device(priv)->chipset >= 0x90)
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nv_wr32(priv, 0xe074, intr1);
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}
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static int
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nv50_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv50_gpio_priv *priv;
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int ret;
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ret = nouveau_gpio_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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priv->base.reset = nv50_gpio_reset;
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priv->base.drive = nv50_gpio_drive;
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priv->base.sense = nv50_gpio_sense;
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priv->base.irq_enable = nv50_gpio_irq_enable;
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nv_subdev(priv)->intr = nv50_gpio_intr;
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return 0;
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}
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void
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nv50_gpio_dtor(struct nouveau_object *object)
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{
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struct nv50_gpio_priv *priv = (void *)object;
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nouveau_gpio_destroy(&priv->base);
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}
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int
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nv50_gpio_init(struct nouveau_object *object)
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{
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struct nv50_gpio_priv *priv = (void *)object;
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int ret;
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ret = nouveau_gpio_init(&priv->base);
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if (ret)
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return ret;
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/* disable, and ack any pending gpio interrupts */
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nv_wr32(priv, 0xe050, 0x00000000);
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nv_wr32(priv, 0xe054, 0xffffffff);
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if (nv_device(priv)->chipset >= 0x90) {
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nv_wr32(priv, 0xe070, 0x00000000);
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nv_wr32(priv, 0xe074, 0xffffffff);
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}
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return 0;
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}
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int
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nv50_gpio_fini(struct nouveau_object *object, bool suspend)
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{
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struct nv50_gpio_priv *priv = (void *)object;
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nv_wr32(priv, 0xe050, 0x00000000);
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if (nv_device(priv)->chipset >= 0x90)
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nv_wr32(priv, 0xe070, 0x00000000);
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return nouveau_gpio_fini(&priv->base, suspend);
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}
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struct nouveau_oclass
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nv50_gpio_oclass = {
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.handle = NV_SUBDEV(GPIO, 0x50),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv50_gpio_ctor,
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.dtor = nv50_gpio_dtor,
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.init = nv50_gpio_init,
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.fini = nv50_gpio_fini,
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},
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};
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