![Thomas Renninger](/assets/img/avatar_default.png)
IA32-Intel Devel guide Volume 3A - 14.3.2.1 ------------------------------------------- ... Opportunistic processor performance operation can be disabled by setting bit 38 of IA32_MISC_ENABLES. This mechanism is intended for BIOS only. If IA32_MISC_ENABLES[38] is set, CPUID.06H:EAX[1] will return 0. Better detect things via cpuid, this cleans up the code a bit and the MSR parts were not working correctly anyway. Signed-off-by: Thomas Renninger <trenn@suse.de> CC: lenb@kernel.org CC: linux@dominikbrodowski.net CC: cpufreq@vger.kernel.org Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
177 lines
4.3 KiB
C
177 lines
4.3 KiB
C
#include <stdio.h>
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#include <errno.h>
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#include <string.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include "helpers/helpers.h"
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static const char *cpu_vendor_table[X86_VENDOR_MAX] = {
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"Unknown", "GenuineIntel", "AuthenticAMD",
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};
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#if defined(__i386__) || defined(__x86_64__)
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/* from gcc */
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#include <cpuid.h>
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/*
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* CPUID functions returning a single datum
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*
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* Define unsigned int cpuid_e[abcd]x(unsigned int op)
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*/
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#define cpuid_func(reg) \
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unsigned int cpuid_##reg(unsigned int op) \
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{ \
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unsigned int eax, ebx, ecx, edx; \
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__cpuid(op, eax, ebx, ecx, edx); \
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return reg; \
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}
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cpuid_func(eax);
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cpuid_func(ebx);
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cpuid_func(ecx);
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cpuid_func(edx);
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#endif /* defined(__i386__) || defined(__x86_64__) */
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/* get_cpu_info
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*
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* Extract CPU vendor, family, model, stepping info from /proc/cpuinfo
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*
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* Returns 0 on success or a negativ error code
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*
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* TBD: Should there be a cpuid alternative for this if /proc is not mounted?
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*/
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int get_cpu_info(unsigned int cpu, struct cpupower_cpu_info *cpu_info)
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{
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FILE *fp;
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char value[64];
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unsigned int proc, x;
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unsigned int unknown = 0xffffff;
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unsigned int cpuid_level, ext_cpuid_level;
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int ret = -EINVAL;
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cpu_info->vendor = X86_VENDOR_UNKNOWN;
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cpu_info->family = unknown;
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cpu_info->model = unknown;
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cpu_info->stepping = unknown;
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cpu_info->caps = 0;
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fp = fopen("/proc/cpuinfo", "r");
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if (!fp)
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return -EIO;
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while (!feof(fp)) {
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if (!fgets(value, 64, fp))
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continue;
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value[63 - 1] = '\0';
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if (!strncmp(value, "processor\t: ", 12))
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sscanf(value, "processor\t: %u", &proc);
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if (proc != cpu)
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continue;
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/* Get CPU vendor */
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if (!strncmp(value, "vendor_id", 9)) {
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for (x = 1; x < X86_VENDOR_MAX; x++) {
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if (strstr(value, cpu_vendor_table[x]))
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cpu_info->vendor = x;
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}
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/* Get CPU family, etc. */
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} else if (!strncmp(value, "cpu family\t: ", 13)) {
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sscanf(value, "cpu family\t: %u",
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&cpu_info->family);
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} else if (!strncmp(value, "model\t\t: ", 9)) {
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sscanf(value, "model\t\t: %u",
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&cpu_info->model);
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} else if (!strncmp(value, "stepping\t: ", 10)) {
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sscanf(value, "stepping\t: %u",
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&cpu_info->stepping);
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/* Exit -> all values must have been set */
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if (cpu_info->vendor == X86_VENDOR_UNKNOWN ||
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cpu_info->family == unknown ||
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cpu_info->model == unknown ||
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cpu_info->stepping == unknown) {
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ret = -EINVAL;
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goto out;
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}
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ret = 0;
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goto out;
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}
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}
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ret = -ENODEV;
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out:
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fclose(fp);
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/* Get some useful CPU capabilities from cpuid */
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if (cpu_info->vendor != X86_VENDOR_AMD &&
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cpu_info->vendor != X86_VENDOR_INTEL)
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return ret;
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cpuid_level = cpuid_eax(0);
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ext_cpuid_level = cpuid_eax(0x80000000);
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/* Invariant TSC */
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if (ext_cpuid_level >= 0x80000007 &&
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(cpuid_edx(0x80000007) & (1 << 8)))
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cpu_info->caps |= CPUPOWER_CAP_INV_TSC;
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/* Aperf/Mperf registers support */
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if (cpuid_level >= 6 && (cpuid_ecx(6) & 0x1))
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cpu_info->caps |= CPUPOWER_CAP_APERF;
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/* AMD Boost state enable/disable register */
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if (cpu_info->vendor == X86_VENDOR_AMD) {
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if (ext_cpuid_level >= 0x80000007 &&
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(cpuid_edx(0x80000007) & (1 << 9)))
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cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
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}
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if (cpu_info->vendor == X86_VENDOR_INTEL) {
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if (cpuid_level >= 6 &&
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(cpuid_eax(6) & (1 << 1)))
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cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA;
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}
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if (cpu_info->vendor == X86_VENDOR_INTEL) {
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/* Intel's perf-bias MSR support */
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if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3)))
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cpu_info->caps |= CPUPOWER_CAP_PERF_BIAS;
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/* Intel's Turbo Ratio Limit support */
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if (cpu_info->family == 6) {
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switch (cpu_info->model) {
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case 0x1A: /* Core i7, Xeon 5500 series
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* Bloomfield, Gainstown NHM-EP
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*/
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case 0x1E: /* Core i7 and i5 Processor
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* Clarksfield, Lynnfield, Jasper Forest
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*/
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case 0x1F: /* Core i7 and i5 Processor - Nehalem */
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case 0x25: /* Westmere Client
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* Clarkdale, Arrandale
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*/
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case 0x2C: /* Westmere EP - Gulftown */
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cpu_info->caps |= CPUPOWER_CAP_HAS_TURBO_RATIO;
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case 0x2A: /* SNB */
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case 0x2D: /* SNB Xeon */
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cpu_info->caps |= CPUPOWER_CAP_HAS_TURBO_RATIO;
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cpu_info->caps |= CPUPOWER_CAP_IS_SNB;
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break;
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case 0x2E: /* Nehalem-EX Xeon - Beckton */
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case 0x2F: /* Westmere-EX Xeon - Eagleton */
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default:
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break;
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}
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}
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}
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/* printf("ID: %u - Extid: 0x%x - Caps: 0x%llx\n",
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cpuid_level, ext_cpuid_level, cpu_info->caps);
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*/
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return ret;
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}
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