![Nick Piggin](/assets/img/avatar_default.png)
This implements ticket lock support for more than 255 CPUs on x86. The code gets switched according to the configured NR_CPUS. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
297 lines
6.9 KiB
C
297 lines
6.9 KiB
C
#ifndef _X86_SPINLOCK_H_
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#define _X86_SPINLOCK_H_
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#include <asm/atomic.h>
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#include <asm/rwlock.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <linux/compiler.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* These are fair FIFO ticket locks, which are currently limited to 256
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* CPUs.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#ifdef CONFIG_X86_32
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typedef char _slock_t;
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# define LOCK_INS_DEC "decb"
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# define LOCK_INS_XCH "xchgb"
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# define LOCK_INS_MOV "movb"
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# define LOCK_INS_CMP "cmpb"
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# define LOCK_PTR_REG "a"
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#else
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typedef int _slock_t;
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# define LOCK_INS_DEC "decl"
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# define LOCK_INS_XCH "xchgl"
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# define LOCK_INS_MOV "movl"
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# define LOCK_INS_CMP "cmpl"
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# define LOCK_PTR_REG "D"
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#endif
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#if defined(CONFIG_X86_32) && \
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(defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
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/*
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* On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
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* (PPro errata 66, 92)
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*/
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# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
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#else
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# define UNLOCK_LOCK_PREFIX
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#endif
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/*
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*
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* We use an xadd covering *both* parts of the lock, to increment the tail and
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* also load the position of the head, which takes care of memory ordering
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* issues and should be optimal for the uncontended case. Note the tail must be
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* in the high part, because a wide xadd increment of the low part would carry
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* up and contaminate the high part.
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*
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* With fewer than 2^8 possible CPUs, we can use x86's partial registers to
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* save some instructions and make the code more elegant. There really isn't
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* much between them in performance though, especially as locks are out of line.
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*/
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#if (NR_CPUS < 256)
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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return (((tmp >> 8) & 0xff) != (tmp & 0xff));
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}
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static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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short inc = 0x0100;
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__asm__ __volatile__ (
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LOCK_PREFIX "xaddw %w0, %1\n"
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"1:\t"
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"cmpb %h0, %b0\n\t"
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"je 2f\n\t"
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"rep ; nop\n\t"
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"movb %1, %b0\n\t"
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/* don't need lfence here, because loads are in-order */
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"jmp 1b\n"
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"2:"
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:"+Q" (inc), "+m" (lock->slock)
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:
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:"memory", "cc");
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int tmp;
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short new;
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asm volatile(
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"movw %2,%w0\n\t"
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"cmpb %h0,%b0\n\t"
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"jne 1f\n\t"
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"movw %w0,%w1\n\t"
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"incb %h1\n\t"
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"lock ; cmpxchgw %w1,%2\n\t"
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"1:"
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"sete %b1\n\t"
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"movzbl %b1,%0\n\t"
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:"=&a" (tmp), "=Q" (new), "+m" (lock->slock)
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:
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: "memory", "cc");
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return tmp;
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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UNLOCK_LOCK_PREFIX "incb %0"
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:"+m" (lock->slock)
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:
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:"memory", "cc");
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}
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#else
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
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}
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static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
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{
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int tmp = *(volatile signed int *)(&(lock)->slock);
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return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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int inc = 0x00010000;
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int tmp;
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__asm__ __volatile__ (
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"lock ; xaddl %0, %1\n"
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"movzwl %w0, %2\n\t"
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"shrl $16, %0\n\t"
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"1:\t"
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"cmpl %0, %2\n\t"
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"je 2f\n\t"
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"rep ; nop\n\t"
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"movzwl %1, %2\n\t"
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/* don't need lfence here, because loads are in-order */
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"jmp 1b\n"
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"2:"
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:"+Q" (inc), "+m" (lock->slock), "=r" (tmp)
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:
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:"memory", "cc");
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int tmp;
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int new;
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asm volatile(
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"movl %2,%0\n\t"
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"movl %0,%1\n\t"
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"roll $16, %0\n\t"
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"cmpl %0,%1\n\t"
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"jne 1f\n\t"
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"addl $0x00010000, %1\n\t"
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"lock ; cmpxchgl %1,%2\n\t"
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"1:"
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"sete %b1\n\t"
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"movzbl %b1,%0\n\t"
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:"=&a" (tmp), "=r" (new), "+m" (lock->slock)
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:
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: "memory", "cc");
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return tmp;
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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UNLOCK_LOCK_PREFIX "incw %0"
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:"+m" (lock->slock)
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:
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:"memory", "cc");
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}
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#endif
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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while (__raw_spin_is_locked(lock))
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cpu_relax();
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int __raw_read_can_lock(raw_rwlock_t *lock)
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{
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return (int)(lock)->lock > 0;
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}
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int __raw_write_can_lock(raw_rwlock_t *lock)
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{
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return (lock)->lock == RW_LOCK_BIAS;
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}
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
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"jns 1f\n"
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"call __read_lock_failed\n\t"
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"1:\n"
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::LOCK_PTR_REG (rw) : "memory");
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
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"jz 1f\n"
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"call __write_lock_failed\n\t"
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"1:\n"
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::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
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}
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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atomic_inc(count);
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return 0;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "addl %1, %0"
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: "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
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}
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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#endif
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