![Grant Likely](/assets/img/avatar_default.png)
Modules are not supposed to use any of the *_initcall*() hooks as the entry point. fsl_pq_mdio.c was using subsys_initcall_sync() instead of module_init() to guarantee that the MDIO bus was initialized before the Ethernet driver goes looking for the phy. However, the recent OF helpers rework happens to also make sure PHY connection is deferred to .open time, so using an initcall is no longer necessary. This patch replaces the initcall with a more traditional an accepted module_init() call. Tested on Freescale MPC8349emitxgp eval board. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: David S. Miller <davem@davemloft.net>
425 lines
9.6 KiB
C
425 lines
9.6 KiB
C
/*
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* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
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* Provides Bus interface for MIIM regs
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*
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* Author: Andy Fleming <afleming@freescale.com>
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*
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* Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
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*
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* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/crc32.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/of_mdio.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/ucc.h>
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#include "gianfar.h"
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#include "fsl_pq_mdio.h"
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/*
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* Write value to the PHY at mii_id at register regnum,
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* on the bus attached to the local interface, which may be different from the
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* generic mdio bus (tied to a single interface), waiting until the write is
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* done before returning. This is helpful in programming interfaces like
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* the TBI which control interfaces like onchip SERDES and are always tied to
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* the local mdio pins, which may not be the same as system mdio bus, used for
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* controlling the external PHYs, for example.
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*/
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int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
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int regnum, u16 value)
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{
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/* Set the PHY address and the register address we want to write */
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out_be32(®s->miimadd, (mii_id << 8) | regnum);
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/* Write out the value we want */
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out_be32(®s->miimcon, value);
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/* Wait for the transaction to finish */
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while (in_be32(®s->miimind) & MIIMIND_BUSY)
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cpu_relax();
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return 0;
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}
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/*
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* Read the bus for PHY at addr mii_id, register regnum, and
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* return the value. Clears miimcom first. All PHY operation
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* done on the bus attached to the local interface,
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* which may be different from the generic mdio bus
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* This is helpful in programming interfaces like
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* the TBI which, in turn, control interfaces like onchip SERDES
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* and are always tied to the local mdio pins, which may not be the
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* same as system mdio bus, used for controlling the external PHYs, for eg.
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*/
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int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
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int mii_id, int regnum)
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{
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u16 value;
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/* Set the PHY address and the register address we want to read */
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out_be32(®s->miimadd, (mii_id << 8) | regnum);
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/* Clear miimcom, and then initiate a read */
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out_be32(®s->miimcom, 0);
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out_be32(®s->miimcom, MII_READ_COMMAND);
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/* Wait for the transaction to finish */
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while (in_be32(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
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cpu_relax();
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/* Grab the value of the register from miimstat */
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value = in_be32(®s->miimstat);
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return value;
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}
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/*
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* Write value to the PHY at mii_id at register regnum,
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* on the bus, waiting until the write is done before returning.
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*/
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int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
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{
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struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
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/* Write to the local MII regs */
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return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
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}
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/*
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* Read the bus for PHY at addr mii_id, register regnum, and
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* return the value. Clears miimcom first.
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*/
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int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
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/* Read the local MII regs */
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return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
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}
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/* Reset the MIIM registers, and wait for the bus to free */
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static int fsl_pq_mdio_reset(struct mii_bus *bus)
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{
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struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
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int timeout = PHY_INIT_TIMEOUT;
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mutex_lock(&bus->mdio_lock);
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/* Reset the management interface */
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out_be32(®s->miimcfg, MIIMCFG_RESET);
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/* Setup the MII Mgmt clock speed */
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out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
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/* Wait until the bus is free */
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while ((in_be32(®s->miimind) & MIIMIND_BUSY) && timeout--)
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cpu_relax();
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mutex_unlock(&bus->mdio_lock);
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if (timeout < 0) {
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printk(KERN_ERR "%s: The MII Bus is stuck!\n",
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bus->name);
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return -EBUSY;
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}
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return 0;
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}
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void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
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{
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const u32 *addr;
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u64 taddr = OF_BAD_ADDR;
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addr = of_get_address(np, 0, NULL, NULL);
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if (addr)
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taddr = of_translate_address(np, addr);
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snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
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(unsigned long long)taddr);
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}
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EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
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/* Scan the bus in reverse, looking for an empty spot */
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static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
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{
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int i;
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for (i = PHY_MAX_ADDR; i > 0; i--) {
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u32 phy_id;
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if (get_phy_id(new_bus, i, &phy_id))
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return -1;
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if (phy_id == 0xffffffff)
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break;
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}
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return i;
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}
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#ifdef CONFIG_GIANFAR
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static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs)
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{
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struct gfar __iomem *enet_regs;
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/*
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* This is mildly evil, but so is our hardware for doing this.
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* Also, we have to cast back to struct gfar because of
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* definition weirdness done in gianfar.h.
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*/
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enet_regs = (struct gfar __iomem *)
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((char __iomem *)regs - offsetof(struct gfar, gfar_mii_regs));
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return &enet_regs->tbipa;
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}
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#endif
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#ifdef CONFIG_UCC_GETH
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static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
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{
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struct device_node *np = NULL;
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int err = 0;
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for_each_compatible_node(np, NULL, "ucc_geth") {
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struct resource tempres;
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err = of_address_to_resource(np, 0, &tempres);
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if (err)
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continue;
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/* if our mdio regs fall within this UCC regs range */
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if ((start >= tempres.start) && (end <= tempres.end)) {
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/* Find the id of the UCC */
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const u32 *id;
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id = of_get_property(np, "cell-index", NULL);
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if (!id) {
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id = of_get_property(np, "device-id", NULL);
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if (!id)
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continue;
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}
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*ucc_id = *id;
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return 0;
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}
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}
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if (err)
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return err;
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else
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return -EINVAL;
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}
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#endif
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static int fsl_pq_mdio_probe(struct of_device *ofdev,
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const struct of_device_id *match)
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{
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struct device_node *np = ofdev->node;
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struct device_node *tbi;
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struct fsl_pq_mdio __iomem *regs;
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u32 __iomem *tbipa;
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struct mii_bus *new_bus;
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int tbiaddr = -1;
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u64 addr, size;
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int err = 0;
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new_bus = mdiobus_alloc();
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if (NULL == new_bus)
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return -ENOMEM;
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new_bus->name = "Freescale PowerQUICC MII Bus",
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new_bus->read = &fsl_pq_mdio_read,
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new_bus->write = &fsl_pq_mdio_write,
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new_bus->reset = &fsl_pq_mdio_reset,
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fsl_pq_mdio_bus_name(new_bus->id, np);
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/* Set the PHY base address */
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addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
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regs = ioremap(addr, size);
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if (NULL == regs) {
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err = -ENOMEM;
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goto err_free_bus;
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}
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new_bus->priv = (void __force *)regs;
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new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
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if (NULL == new_bus->irq) {
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err = -ENOMEM;
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goto err_unmap_regs;
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}
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new_bus->parent = &ofdev->dev;
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dev_set_drvdata(&ofdev->dev, new_bus);
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if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
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of_device_is_compatible(np, "fsl,gianfar-tbi") ||
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of_device_is_compatible(np, "gianfar")) {
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#ifdef CONFIG_GIANFAR
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tbipa = get_gfar_tbipa(regs);
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#else
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err = -ENODEV;
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goto err_free_irqs;
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#endif
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} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
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of_device_is_compatible(np, "ucc_geth_phy")) {
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#ifdef CONFIG_UCC_GETH
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u32 id;
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tbipa = ®s->utbipar;
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if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
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goto err_free_irqs;
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ucc_set_qe_mux_mii_mng(id - 1);
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#else
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err = -ENODEV;
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goto err_free_irqs;
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#endif
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} else {
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err = -ENODEV;
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goto err_free_irqs;
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}
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for_each_child_of_node(np, tbi) {
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if (!strncmp(tbi->type, "tbi-phy", 8))
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break;
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}
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if (tbi) {
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const u32 *prop = of_get_property(tbi, "reg", NULL);
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if (prop)
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tbiaddr = *prop;
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}
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if (tbiaddr == -1) {
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out_be32(tbipa, 0);
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tbiaddr = fsl_pq_mdio_find_free(new_bus);
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}
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/*
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* We define TBIPA at 0 to be illegal, opting to fail for boards that
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* have PHYs at 1-31, rather than change tbipa and rescan.
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*/
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if (tbiaddr == 0) {
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err = -EBUSY;
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goto err_free_irqs;
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}
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out_be32(tbipa, tbiaddr);
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err = of_mdiobus_register(new_bus, np);
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if (err) {
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printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
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new_bus->name);
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goto err_free_irqs;
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}
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return 0;
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err_free_irqs:
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kfree(new_bus->irq);
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err_unmap_regs:
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iounmap(regs);
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err_free_bus:
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kfree(new_bus);
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return err;
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}
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static int fsl_pq_mdio_remove(struct of_device *ofdev)
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{
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struct device *device = &ofdev->dev;
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struct mii_bus *bus = dev_get_drvdata(device);
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mdiobus_unregister(bus);
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dev_set_drvdata(device, NULL);
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iounmap((void __iomem *)bus->priv);
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bus->priv = NULL;
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mdiobus_free(bus);
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return 0;
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}
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static struct of_device_id fsl_pq_mdio_match[] = {
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{
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.type = "mdio",
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.compatible = "ucc_geth_phy",
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},
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{
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.type = "mdio",
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.compatible = "gianfar",
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},
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{
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.compatible = "fsl,ucc-mdio",
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},
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{
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.compatible = "fsl,gianfar-tbi",
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},
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{
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.compatible = "fsl,gianfar-mdio",
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},
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{},
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};
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static struct of_platform_driver fsl_pq_mdio_driver = {
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.name = "fsl-pq_mdio",
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.probe = fsl_pq_mdio_probe,
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.remove = fsl_pq_mdio_remove,
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.match_table = fsl_pq_mdio_match,
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};
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int __init fsl_pq_mdio_init(void)
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{
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return of_register_platform_driver(&fsl_pq_mdio_driver);
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}
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module_init(fsl_pq_mdio_init);
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void fsl_pq_mdio_exit(void)
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{
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of_unregister_platform_driver(&fsl_pq_mdio_driver);
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}
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module_exit(fsl_pq_mdio_exit);
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