![Michael S. Tsirkin](/assets/img/avatar_default.png)
Implement reporting asynchronous CQ events in Mellanox HCA driver. Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
974 lines
26 KiB
C
974 lines
26 KiB
C
/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include "mthca_dev.h"
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#include "mthca_cmd.h"
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#include "mthca_config_reg.h"
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enum {
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MTHCA_NUM_ASYNC_EQE = 0x80,
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MTHCA_NUM_CMD_EQE = 0x80,
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MTHCA_EQ_ENTRY_SIZE = 0x20
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};
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/*
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* Must be packed because start is 64 bits but only aligned to 32 bits.
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*/
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struct mthca_eq_context {
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__be32 flags;
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__be64 start;
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__be32 logsize_usrpage;
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__be32 tavor_pd; /* reserved for Arbel */
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u8 reserved1[3];
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u8 intr;
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__be32 arbel_pd; /* lost_count for Tavor */
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__be32 lkey;
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u32 reserved2[2];
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__be32 consumer_index;
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__be32 producer_index;
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u32 reserved3[4];
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} __attribute__((packed));
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#define MTHCA_EQ_STATUS_OK ( 0 << 28)
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#define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28)
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#define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28)
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#define MTHCA_EQ_OWNER_SW ( 0 << 24)
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#define MTHCA_EQ_OWNER_HW ( 1 << 24)
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#define MTHCA_EQ_FLAG_TR ( 1 << 18)
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#define MTHCA_EQ_FLAG_OI ( 1 << 17)
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#define MTHCA_EQ_STATE_ARMED ( 1 << 8)
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#define MTHCA_EQ_STATE_FIRED ( 2 << 8)
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#define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8)
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#define MTHCA_EQ_STATE_ARBEL ( 8 << 8)
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enum {
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MTHCA_EVENT_TYPE_COMP = 0x00,
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MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
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MTHCA_EVENT_TYPE_COMM_EST = 0x02,
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MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
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MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
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MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14,
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MTHCA_EVENT_TYPE_CQ_ERROR = 0x04,
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MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
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MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
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MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
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MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
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MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
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MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
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MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
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MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09,
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MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
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MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e,
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MTHCA_EVENT_TYPE_CMD = 0x0a
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};
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#define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \
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(1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \
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(1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \
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(1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \
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(1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \
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(1ULL << MTHCA_EVENT_TYPE_ECC_DETECT))
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#define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \
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(1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
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(1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT))
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#define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD)
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#define MTHCA_EQ_DB_INC_CI (1 << 24)
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#define MTHCA_EQ_DB_REQ_NOT (2 << 24)
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#define MTHCA_EQ_DB_DISARM_CQ (3 << 24)
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#define MTHCA_EQ_DB_SET_CI (4 << 24)
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#define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24)
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struct mthca_eqe {
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u8 reserved1;
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u8 type;
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u8 reserved2;
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u8 subtype;
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union {
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u32 raw[6];
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struct {
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__be32 cqn;
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} __attribute__((packed)) comp;
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struct {
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u16 reserved1;
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__be16 token;
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u32 reserved2;
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u8 reserved3[3];
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u8 status;
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__be64 out_param;
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} __attribute__((packed)) cmd;
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struct {
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__be32 qpn;
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} __attribute__((packed)) qp;
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struct {
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__be32 srqn;
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} __attribute__((packed)) srq;
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struct {
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__be32 cqn;
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u32 reserved1;
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u8 reserved2[3];
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u8 syndrome;
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} __attribute__((packed)) cq_err;
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struct {
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u32 reserved1[2];
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__be32 port;
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} __attribute__((packed)) port_change;
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} event;
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u8 reserved3[3];
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u8 owner;
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} __attribute__((packed));
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#define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7)
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#define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7)
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static inline u64 async_mask(struct mthca_dev *dev)
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{
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return dev->mthca_flags & MTHCA_FLAG_SRQ ?
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MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK :
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MTHCA_ASYNC_EVENT_MASK;
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}
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static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
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{
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__be32 doorbell[2];
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doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn);
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doorbell[1] = cpu_to_be32(ci & (eq->nent - 1));
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/*
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* This barrier makes sure that all updates to ownership bits
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* done by set_eqe_hw() hit memory before the consumer index
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* is updated. set_eq_ci() allows the HCA to possibly write
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* more EQ entries, and we want to avoid the exceedingly
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* unlikely possibility of the HCA writing an entry and then
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* having set_eqe_hw() overwrite the owner field.
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*/
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wmb();
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mthca_write64(doorbell,
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dev->kar + MTHCA_EQ_DOORBELL,
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MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
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}
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static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
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{
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/* See comment in tavor_set_eq_ci() above. */
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wmb();
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__raw_writel((__force u32) cpu_to_be32(ci),
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dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8);
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/* We still want ordering, just not swabbing, so add a barrier */
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mb();
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}
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static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
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{
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if (mthca_is_memfree(dev))
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arbel_set_eq_ci(dev, eq, ci);
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else
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tavor_set_eq_ci(dev, eq, ci);
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}
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static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
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{
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__be32 doorbell[2];
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doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn);
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doorbell[1] = 0;
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mthca_write64(doorbell,
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dev->kar + MTHCA_EQ_DOORBELL,
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MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
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}
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static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
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{
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writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
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}
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static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
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{
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if (!mthca_is_memfree(dev)) {
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__be32 doorbell[2];
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doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn);
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doorbell[1] = cpu_to_be32(cqn);
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mthca_write64(doorbell,
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dev->kar + MTHCA_EQ_DOORBELL,
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MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
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}
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}
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static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry)
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{
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unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE;
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return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
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}
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static inline struct mthca_eqe* next_eqe_sw(struct mthca_eq *eq)
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{
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struct mthca_eqe* eqe;
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eqe = get_eqe(eq, eq->cons_index);
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return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe;
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}
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static inline void set_eqe_hw(struct mthca_eqe *eqe)
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{
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eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW;
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}
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static void port_change(struct mthca_dev *dev, int port, int active)
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{
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struct ib_event record;
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mthca_dbg(dev, "Port change to %s for port %d\n",
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active ? "active" : "down", port);
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record.device = &dev->ib_dev;
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record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
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record.element.port_num = port;
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ib_dispatch_event(&record);
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}
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static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq)
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{
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struct mthca_eqe *eqe;
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int disarm_cqn;
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int eqes_found = 0;
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while ((eqe = next_eqe_sw(eq))) {
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int set_ci = 0;
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/*
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* Make sure we read EQ entry contents after we've
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* checked the ownership bit.
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*/
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rmb();
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switch (eqe->type) {
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case MTHCA_EVENT_TYPE_COMP:
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disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
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disarm_cq(dev, eq->eqn, disarm_cqn);
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mthca_cq_completion(dev, disarm_cqn);
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break;
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case MTHCA_EVENT_TYPE_PATH_MIG:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_PATH_MIG);
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break;
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case MTHCA_EVENT_TYPE_COMM_EST:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_COMM_EST);
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break;
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case MTHCA_EVENT_TYPE_SQ_DRAINED:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_SQ_DRAINED);
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break;
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case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_QP_LAST_WQE_REACHED);
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break;
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case MTHCA_EVENT_TYPE_SRQ_LIMIT:
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mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
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IB_EVENT_SRQ_LIMIT_REACHED);
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break;
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case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_QP_FATAL);
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break;
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case MTHCA_EVENT_TYPE_PATH_MIG_FAILED:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_PATH_MIG_ERR);
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break;
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case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_QP_REQ_ERR);
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break;
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case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR:
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mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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IB_EVENT_QP_ACCESS_ERR);
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break;
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case MTHCA_EVENT_TYPE_CMD:
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mthca_cmd_event(dev,
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be16_to_cpu(eqe->event.cmd.token),
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eqe->event.cmd.status,
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be64_to_cpu(eqe->event.cmd.out_param));
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/*
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* cmd_event() may add more commands.
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* The card will think the queue has overflowed if
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* we don't tell it we've been processing events.
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*/
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set_ci = 1;
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break;
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case MTHCA_EVENT_TYPE_PORT_CHANGE:
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port_change(dev,
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(be32_to_cpu(eqe->event.port_change.port) >> 28) & 3,
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eqe->subtype == 0x4);
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break;
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case MTHCA_EVENT_TYPE_CQ_ERROR:
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mthca_warn(dev, "CQ %s on CQN %06x\n",
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eqe->event.cq_err.syndrome == 1 ?
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"overrun" : "access violation",
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be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
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mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
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IB_EVENT_CQ_ERR);
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break;
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case MTHCA_EVENT_TYPE_EQ_OVERFLOW:
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mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
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break;
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case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR:
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case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR:
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case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR:
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case MTHCA_EVENT_TYPE_ECC_DETECT:
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default:
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mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n",
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eqe->type, eqe->subtype, eq->eqn);
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break;
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};
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set_eqe_hw(eqe);
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++eq->cons_index;
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eqes_found = 1;
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if (unlikely(set_ci)) {
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/*
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* Conditional on hca_type is OK here because
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* this is a rare case, not the fast path.
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*/
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set_eq_ci(dev, eq, eq->cons_index);
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set_ci = 0;
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}
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}
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/*
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* Rely on caller to set consumer index so that we don't have
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* to test hca_type in our interrupt handling fast path.
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*/
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return eqes_found;
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}
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static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
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{
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struct mthca_dev *dev = dev_ptr;
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u32 ecr;
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int i;
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if (dev->eq_table.clr_mask)
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writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
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ecr = readl(dev->eq_regs.tavor.ecr_base + 4);
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if (!ecr)
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return IRQ_NONE;
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writel(ecr, dev->eq_regs.tavor.ecr_base +
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MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4);
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for (i = 0; i < MTHCA_NUM_EQ; ++i)
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if (ecr & dev->eq_table.eq[i].eqn_mask) {
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if (mthca_eq_int(dev, &dev->eq_table.eq[i]))
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tavor_set_eq_ci(dev, &dev->eq_table.eq[i],
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dev->eq_table.eq[i].cons_index);
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tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr,
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struct pt_regs *regs)
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{
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struct mthca_eq *eq = eq_ptr;
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struct mthca_dev *dev = eq->dev;
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mthca_eq_int(dev, eq);
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tavor_set_eq_ci(dev, eq, eq->cons_index);
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tavor_eq_req_not(dev, eq->eqn);
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/* MSI-X vectors always belong to us */
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return IRQ_HANDLED;
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}
|
|
|
|
static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr, struct pt_regs *regs)
|
|
{
|
|
struct mthca_dev *dev = dev_ptr;
|
|
int work = 0;
|
|
int i;
|
|
|
|
if (dev->eq_table.clr_mask)
|
|
writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
|
|
|
|
for (i = 0; i < MTHCA_NUM_EQ; ++i)
|
|
if (mthca_eq_int(dev, &dev->eq_table.eq[i])) {
|
|
work = 1;
|
|
arbel_set_eq_ci(dev, &dev->eq_table.eq[i],
|
|
dev->eq_table.eq[i].cons_index);
|
|
}
|
|
|
|
arbel_eq_req_not(dev, dev->eq_table.arm_mask);
|
|
|
|
return IRQ_RETVAL(work);
|
|
}
|
|
|
|
static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr,
|
|
struct pt_regs *regs)
|
|
{
|
|
struct mthca_eq *eq = eq_ptr;
|
|
struct mthca_dev *dev = eq->dev;
|
|
|
|
mthca_eq_int(dev, eq);
|
|
arbel_set_eq_ci(dev, eq, eq->cons_index);
|
|
arbel_eq_req_not(dev, eq->eqn_mask);
|
|
|
|
/* MSI-X vectors always belong to us */
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int __devinit mthca_create_eq(struct mthca_dev *dev,
|
|
int nent,
|
|
u8 intr,
|
|
struct mthca_eq *eq)
|
|
{
|
|
int npages = (nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
|
|
PAGE_SIZE;
|
|
u64 *dma_list = NULL;
|
|
dma_addr_t t;
|
|
struct mthca_mailbox *mailbox;
|
|
struct mthca_eq_context *eq_context;
|
|
int err = -ENOMEM;
|
|
int i;
|
|
u8 status;
|
|
|
|
eq->dev = dev;
|
|
eq->nent = roundup_pow_of_two(max(nent, 2));
|
|
|
|
eq->page_list = kmalloc(npages * sizeof *eq->page_list,
|
|
GFP_KERNEL);
|
|
if (!eq->page_list)
|
|
goto err_out;
|
|
|
|
for (i = 0; i < npages; ++i)
|
|
eq->page_list[i].buf = NULL;
|
|
|
|
dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
|
|
if (!dma_list)
|
|
goto err_out_free;
|
|
|
|
mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
|
|
if (IS_ERR(mailbox))
|
|
goto err_out_free;
|
|
eq_context = mailbox->buf;
|
|
|
|
for (i = 0; i < npages; ++i) {
|
|
eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
|
|
PAGE_SIZE, &t, GFP_KERNEL);
|
|
if (!eq->page_list[i].buf)
|
|
goto err_out_free_pages;
|
|
|
|
dma_list[i] = t;
|
|
pci_unmap_addr_set(&eq->page_list[i], mapping, t);
|
|
|
|
memset(eq->page_list[i].buf, 0, PAGE_SIZE);
|
|
}
|
|
|
|
for (i = 0; i < eq->nent; ++i)
|
|
set_eqe_hw(get_eqe(eq, i));
|
|
|
|
eq->eqn = mthca_alloc(&dev->eq_table.alloc);
|
|
if (eq->eqn == -1)
|
|
goto err_out_free_pages;
|
|
|
|
err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
|
|
dma_list, PAGE_SHIFT, npages,
|
|
0, npages * PAGE_SIZE,
|
|
MTHCA_MPT_FLAG_LOCAL_WRITE |
|
|
MTHCA_MPT_FLAG_LOCAL_READ,
|
|
&eq->mr);
|
|
if (err)
|
|
goto err_out_free_eq;
|
|
|
|
memset(eq_context, 0, sizeof *eq_context);
|
|
eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK |
|
|
MTHCA_EQ_OWNER_HW |
|
|
MTHCA_EQ_STATE_ARMED |
|
|
MTHCA_EQ_FLAG_TR);
|
|
if (mthca_is_memfree(dev))
|
|
eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL);
|
|
|
|
eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24);
|
|
if (mthca_is_memfree(dev)) {
|
|
eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num);
|
|
} else {
|
|
eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
|
|
eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num);
|
|
}
|
|
eq_context->intr = intr;
|
|
eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey);
|
|
|
|
err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status);
|
|
if (err) {
|
|
mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err);
|
|
goto err_out_free_mr;
|
|
}
|
|
if (status) {
|
|
mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n",
|
|
status);
|
|
err = -EINVAL;
|
|
goto err_out_free_mr;
|
|
}
|
|
|
|
kfree(dma_list);
|
|
mthca_free_mailbox(dev, mailbox);
|
|
|
|
eq->eqn_mask = swab32(1 << eq->eqn);
|
|
eq->cons_index = 0;
|
|
|
|
dev->eq_table.arm_mask |= eq->eqn_mask;
|
|
|
|
mthca_dbg(dev, "Allocated EQ %d with %d entries\n",
|
|
eq->eqn, eq->nent);
|
|
|
|
return err;
|
|
|
|
err_out_free_mr:
|
|
mthca_free_mr(dev, &eq->mr);
|
|
|
|
err_out_free_eq:
|
|
mthca_free(&dev->eq_table.alloc, eq->eqn);
|
|
|
|
err_out_free_pages:
|
|
for (i = 0; i < npages; ++i)
|
|
if (eq->page_list[i].buf)
|
|
dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
|
|
eq->page_list[i].buf,
|
|
pci_unmap_addr(&eq->page_list[i],
|
|
mapping));
|
|
|
|
mthca_free_mailbox(dev, mailbox);
|
|
|
|
err_out_free:
|
|
kfree(eq->page_list);
|
|
kfree(dma_list);
|
|
|
|
err_out:
|
|
return err;
|
|
}
|
|
|
|
static void mthca_free_eq(struct mthca_dev *dev,
|
|
struct mthca_eq *eq)
|
|
{
|
|
struct mthca_mailbox *mailbox;
|
|
int err;
|
|
u8 status;
|
|
int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
|
|
PAGE_SIZE;
|
|
int i;
|
|
|
|
mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
|
|
if (IS_ERR(mailbox))
|
|
return;
|
|
|
|
err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status);
|
|
if (err)
|
|
mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err);
|
|
if (status)
|
|
mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status);
|
|
|
|
dev->eq_table.arm_mask &= ~eq->eqn_mask;
|
|
|
|
if (0) {
|
|
mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
|
|
for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {
|
|
if (i % 4 == 0)
|
|
printk("[%02x] ", i * 4);
|
|
printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
|
|
if ((i + 1) % 4 == 0)
|
|
printk("\n");
|
|
}
|
|
}
|
|
|
|
mthca_free_mr(dev, &eq->mr);
|
|
for (i = 0; i < npages; ++i)
|
|
pci_free_consistent(dev->pdev, PAGE_SIZE,
|
|
eq->page_list[i].buf,
|
|
pci_unmap_addr(&eq->page_list[i], mapping));
|
|
|
|
kfree(eq->page_list);
|
|
mthca_free_mailbox(dev, mailbox);
|
|
}
|
|
|
|
static void mthca_free_irqs(struct mthca_dev *dev)
|
|
{
|
|
int i;
|
|
|
|
if (dev->eq_table.have_irq)
|
|
free_irq(dev->pdev->irq, dev);
|
|
for (i = 0; i < MTHCA_NUM_EQ; ++i)
|
|
if (dev->eq_table.eq[i].have_irq)
|
|
free_irq(dev->eq_table.eq[i].msi_x_vector,
|
|
dev->eq_table.eq + i);
|
|
}
|
|
|
|
static int __devinit mthca_map_reg(struct mthca_dev *dev,
|
|
unsigned long offset, unsigned long size,
|
|
void __iomem **map)
|
|
{
|
|
unsigned long base = pci_resource_start(dev->pdev, 0);
|
|
|
|
if (!request_mem_region(base + offset, size, DRV_NAME))
|
|
return -EBUSY;
|
|
|
|
*map = ioremap(base + offset, size);
|
|
if (!*map) {
|
|
release_mem_region(base + offset, size);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset,
|
|
unsigned long size, void __iomem *map)
|
|
{
|
|
unsigned long base = pci_resource_start(dev->pdev, 0);
|
|
|
|
release_mem_region(base + offset, size);
|
|
iounmap(map);
|
|
}
|
|
|
|
static int __devinit mthca_map_eq_regs(struct mthca_dev *dev)
|
|
{
|
|
unsigned long mthca_base;
|
|
|
|
mthca_base = pci_resource_start(dev->pdev, 0);
|
|
|
|
if (mthca_is_memfree(dev)) {
|
|
/*
|
|
* We assume that the EQ arm and EQ set CI registers
|
|
* fall within the first BAR. We can't trust the
|
|
* values firmware gives us, since those addresses are
|
|
* valid on the HCA's side of the PCI bus but not
|
|
* necessarily the host side.
|
|
*/
|
|
if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
|
|
&dev->clr_base)) {
|
|
mthca_err(dev, "Couldn't map interrupt clear register, "
|
|
"aborting.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/*
|
|
* Add 4 because we limit ourselves to EQs 0 ... 31,
|
|
* so we only need the low word of the register.
|
|
*/
|
|
if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.eq_arm_base) + 4, 4,
|
|
&dev->eq_regs.arbel.eq_arm)) {
|
|
mthca_err(dev, "Couldn't map EQ arm register, aborting.\n");
|
|
mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
|
|
dev->clr_base);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.eq_set_ci_base,
|
|
MTHCA_EQ_SET_CI_SIZE,
|
|
&dev->eq_regs.arbel.eq_set_ci_base)) {
|
|
mthca_err(dev, "Couldn't map EQ CI register, aborting.\n");
|
|
mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.eq_arm_base) + 4, 4,
|
|
dev->eq_regs.arbel.eq_arm);
|
|
mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
|
|
dev->clr_base);
|
|
return -ENOMEM;
|
|
}
|
|
} else {
|
|
if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
|
|
&dev->clr_base)) {
|
|
mthca_err(dev, "Couldn't map interrupt clear register, "
|
|
"aborting.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (mthca_map_reg(dev, MTHCA_ECR_BASE,
|
|
MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
|
|
&dev->eq_regs.tavor.ecr_base)) {
|
|
mthca_err(dev, "Couldn't map ecr register, "
|
|
"aborting.\n");
|
|
mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
|
|
dev->clr_base);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static void __devexit mthca_unmap_eq_regs(struct mthca_dev *dev)
|
|
{
|
|
if (mthca_is_memfree(dev)) {
|
|
mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.eq_set_ci_base,
|
|
MTHCA_EQ_SET_CI_SIZE,
|
|
dev->eq_regs.arbel.eq_set_ci_base);
|
|
mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.eq_arm_base) + 4, 4,
|
|
dev->eq_regs.arbel.eq_arm);
|
|
mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
|
|
dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
|
|
dev->clr_base);
|
|
} else {
|
|
mthca_unmap_reg(dev, MTHCA_ECR_BASE,
|
|
MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
|
|
dev->eq_regs.tavor.ecr_base);
|
|
mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
|
|
dev->clr_base);
|
|
}
|
|
}
|
|
|
|
int __devinit mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
|
|
{
|
|
int ret;
|
|
u8 status;
|
|
|
|
/*
|
|
* We assume that mapping one page is enough for the whole EQ
|
|
* context table. This is fine with all current HCAs, because
|
|
* we only use 32 EQs and each EQ uses 32 bytes of context
|
|
* memory, or 1 KB total.
|
|
*/
|
|
dev->eq_table.icm_virt = icm_virt;
|
|
dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
|
|
if (!dev->eq_table.icm_page)
|
|
return -ENOMEM;
|
|
dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0,
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
if (pci_dma_mapping_error(dev->eq_table.icm_dma)) {
|
|
__free_page(dev->eq_table.icm_page);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status);
|
|
if (!ret && status)
|
|
ret = -EINVAL;
|
|
if (ret) {
|
|
pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
__free_page(dev->eq_table.icm_page);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void __devexit mthca_unmap_eq_icm(struct mthca_dev *dev)
|
|
{
|
|
u8 status;
|
|
|
|
mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, PAGE_SIZE / 4096, &status);
|
|
pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
__free_page(dev->eq_table.icm_page);
|
|
}
|
|
|
|
int __devinit mthca_init_eq_table(struct mthca_dev *dev)
|
|
{
|
|
int err;
|
|
u8 status;
|
|
u8 intr;
|
|
int i;
|
|
|
|
err = mthca_alloc_init(&dev->eq_table.alloc,
|
|
dev->limits.num_eqs,
|
|
dev->limits.num_eqs - 1,
|
|
dev->limits.reserved_eqs);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mthca_map_eq_regs(dev);
|
|
if (err)
|
|
goto err_out_free;
|
|
|
|
if (dev->mthca_flags & MTHCA_FLAG_MSI ||
|
|
dev->mthca_flags & MTHCA_FLAG_MSI_X) {
|
|
dev->eq_table.clr_mask = 0;
|
|
} else {
|
|
dev->eq_table.clr_mask =
|
|
swab32(1 << (dev->eq_table.inta_pin & 31));
|
|
dev->eq_table.clr_int = dev->clr_base +
|
|
(dev->eq_table.inta_pin < 32 ? 4 : 0);
|
|
}
|
|
|
|
dev->eq_table.arm_mask = 0;
|
|
|
|
intr = (dev->mthca_flags & MTHCA_FLAG_MSI) ?
|
|
128 : dev->eq_table.inta_pin;
|
|
|
|
err = mthca_create_eq(dev, dev->limits.num_cqs,
|
|
(dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr,
|
|
&dev->eq_table.eq[MTHCA_EQ_COMP]);
|
|
if (err)
|
|
goto err_out_unmap;
|
|
|
|
err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE,
|
|
(dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr,
|
|
&dev->eq_table.eq[MTHCA_EQ_ASYNC]);
|
|
if (err)
|
|
goto err_out_comp;
|
|
|
|
err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE,
|
|
(dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr,
|
|
&dev->eq_table.eq[MTHCA_EQ_CMD]);
|
|
if (err)
|
|
goto err_out_async;
|
|
|
|
if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
|
|
static const char *eq_name[] = {
|
|
[MTHCA_EQ_COMP] = DRV_NAME " (comp)",
|
|
[MTHCA_EQ_ASYNC] = DRV_NAME " (async)",
|
|
[MTHCA_EQ_CMD] = DRV_NAME " (cmd)"
|
|
};
|
|
|
|
for (i = 0; i < MTHCA_NUM_EQ; ++i) {
|
|
err = request_irq(dev->eq_table.eq[i].msi_x_vector,
|
|
mthca_is_memfree(dev) ?
|
|
mthca_arbel_msi_x_interrupt :
|
|
mthca_tavor_msi_x_interrupt,
|
|
0, eq_name[i], dev->eq_table.eq + i);
|
|
if (err)
|
|
goto err_out_cmd;
|
|
dev->eq_table.eq[i].have_irq = 1;
|
|
}
|
|
} else {
|
|
err = request_irq(dev->pdev->irq,
|
|
mthca_is_memfree(dev) ?
|
|
mthca_arbel_interrupt :
|
|
mthca_tavor_interrupt,
|
|
SA_SHIRQ, DRV_NAME, dev);
|
|
if (err)
|
|
goto err_out_cmd;
|
|
dev->eq_table.have_irq = 1;
|
|
}
|
|
|
|
err = mthca_MAP_EQ(dev, async_mask(dev),
|
|
0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
|
|
if (err)
|
|
mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
|
|
dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err);
|
|
if (status)
|
|
mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n",
|
|
dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status);
|
|
|
|
err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
|
|
0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
|
|
if (err)
|
|
mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n",
|
|
dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err);
|
|
if (status)
|
|
mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n",
|
|
dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status);
|
|
|
|
for (i = 0; i < MTHCA_EQ_CMD; ++i)
|
|
if (mthca_is_memfree(dev))
|
|
arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask);
|
|
else
|
|
tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
|
|
|
|
return 0;
|
|
|
|
err_out_cmd:
|
|
mthca_free_irqs(dev);
|
|
mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]);
|
|
|
|
err_out_async:
|
|
mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
|
|
|
|
err_out_comp:
|
|
mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]);
|
|
|
|
err_out_unmap:
|
|
mthca_unmap_eq_regs(dev);
|
|
|
|
err_out_free:
|
|
mthca_alloc_cleanup(&dev->eq_table.alloc);
|
|
return err;
|
|
}
|
|
|
|
void __devexit mthca_cleanup_eq_table(struct mthca_dev *dev)
|
|
{
|
|
u8 status;
|
|
int i;
|
|
|
|
mthca_free_irqs(dev);
|
|
|
|
mthca_MAP_EQ(dev, async_mask(dev),
|
|
1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
|
|
mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
|
|
1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
|
|
|
|
for (i = 0; i < MTHCA_NUM_EQ; ++i)
|
|
mthca_free_eq(dev, &dev->eq_table.eq[i]);
|
|
|
|
mthca_unmap_eq_regs(dev);
|
|
|
|
mthca_alloc_cleanup(&dev->eq_table.alloc);
|
|
}
|