![Linus Torvalds](/assets/img/avatar_default.png)
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
1223 lines
30 KiB
C
1223 lines
30 KiB
C
/*
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* linux/drivers/media/mmc/omap.c
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*
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* Copyright (C) 2004 Nokia Corporation
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* Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
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* Misc hacks here and there by Tony Lindgren <tony@atomide.com>
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* Other hacks (DMA, SD, etc) by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/protocol.h>
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#include <linux/mmc/card.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/scatterlist.h>
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#include <asm/mach-types.h>
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/fpga.h>
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#include <asm/arch/tps65010.h>
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#include "omap.h"
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#define DRIVER_NAME "mmci-omap"
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#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
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/* Specifies how often in millisecs to poll for card status changes
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* when the cover switch is open */
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#define OMAP_MMC_SWITCH_POLL_DELAY 500
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static int mmc_omap_enable_poll = 1;
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struct mmc_omap_host {
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int initialized;
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int suspended;
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struct mmc_request * mrq;
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struct mmc_command * cmd;
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struct mmc_data * data;
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struct mmc_host * mmc;
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struct device * dev;
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unsigned char id; /* 16xx chips have 2 MMC blocks */
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struct clk * iclk;
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struct clk * fclk;
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struct resource *res;
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void __iomem *base;
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int irq;
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unsigned char bus_mode;
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unsigned char hw_bus_mode;
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unsigned int sg_len;
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int sg_idx;
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u16 * buffer;
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u32 buffer_bytes_left;
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u32 total_bytes_left;
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unsigned use_dma:1;
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unsigned brs_received:1, dma_done:1;
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unsigned dma_is_read:1;
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unsigned dma_in_use:1;
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int dma_ch;
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spinlock_t dma_lock;
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struct timer_list dma_timer;
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unsigned dma_len;
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short power_pin;
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short wp_pin;
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int switch_pin;
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struct work_struct switch_work;
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struct timer_list switch_timer;
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int switch_last_state;
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};
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static inline int
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mmc_omap_cover_is_open(struct mmc_omap_host *host)
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{
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if (host->switch_pin < 0)
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return 0;
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return omap_get_gpio_datain(host->switch_pin);
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}
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static ssize_t
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mmc_omap_show_cover_switch(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct mmc_omap_host *host = dev_get_drvdata(dev);
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return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
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"closed");
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}
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static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
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static ssize_t
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mmc_omap_show_enable_poll(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
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}
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static ssize_t
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mmc_omap_store_enable_poll(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t size)
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{
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int enable_poll;
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if (sscanf(buf, "%10d", &enable_poll) != 1)
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return -EINVAL;
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if (enable_poll != mmc_omap_enable_poll) {
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struct mmc_omap_host *host = dev_get_drvdata(dev);
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mmc_omap_enable_poll = enable_poll;
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if (enable_poll && host->switch_pin >= 0)
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schedule_work(&host->switch_work);
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}
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return size;
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}
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static DEVICE_ATTR(enable_poll, 0664,
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mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
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static void
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mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
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{
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u32 cmdreg;
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u32 resptype;
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u32 cmdtype;
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host->cmd = cmd;
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resptype = 0;
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cmdtype = 0;
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/* Our hardware needs to know exact type */
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switch (RSP_TYPE(mmc_resp_type(cmd))) {
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case RSP_TYPE(MMC_RSP_R1):
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/* resp 1, resp 1b */
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resptype = 1;
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break;
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case RSP_TYPE(MMC_RSP_R2):
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resptype = 2;
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break;
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case RSP_TYPE(MMC_RSP_R3):
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resptype = 3;
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break;
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default:
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break;
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}
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if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
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cmdtype = OMAP_MMC_CMDTYPE_ADTC;
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} else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
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cmdtype = OMAP_MMC_CMDTYPE_BC;
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} else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
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cmdtype = OMAP_MMC_CMDTYPE_BCR;
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} else {
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cmdtype = OMAP_MMC_CMDTYPE_AC;
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}
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cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
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if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
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cmdreg |= 1 << 6;
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if (cmd->flags & MMC_RSP_BUSY)
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cmdreg |= 1 << 11;
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if (host->data && !(host->data->flags & MMC_DATA_WRITE))
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cmdreg |= 1 << 15;
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clk_enable(host->fclk);
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OMAP_MMC_WRITE(host->base, CTO, 200);
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OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
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OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16);
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OMAP_MMC_WRITE(host->base, IE,
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OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
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OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
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OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
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OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
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OMAP_MMC_STAT_END_OF_DATA);
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OMAP_MMC_WRITE(host->base, CMD, cmdreg);
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}
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static void
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mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
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{
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if (host->dma_in_use) {
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enum dma_data_direction dma_data_dir;
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BUG_ON(host->dma_ch < 0);
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if (data->error != MMC_ERR_NONE)
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omap_stop_dma(host->dma_ch);
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/* Release DMA channel lazily */
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mod_timer(&host->dma_timer, jiffies + HZ);
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if (data->flags & MMC_DATA_WRITE)
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dma_data_dir = DMA_TO_DEVICE;
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else
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dma_data_dir = DMA_FROM_DEVICE;
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
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dma_data_dir);
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}
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host->data = NULL;
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host->sg_len = 0;
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clk_disable(host->fclk);
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/* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
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* dozens of requests until the card finishes writing data.
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* It'd be cheaper to just wait till an EOFB interrupt arrives...
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*/
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if (!data->stop) {
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host->mrq = NULL;
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mmc_request_done(host->mmc, data->mrq);
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return;
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}
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mmc_omap_start_command(host, data->stop);
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}
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static void
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mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
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{
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unsigned long flags;
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int done;
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if (!host->dma_in_use) {
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mmc_omap_xfer_done(host, data);
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return;
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}
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done = 0;
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spin_lock_irqsave(&host->dma_lock, flags);
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if (host->dma_done)
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done = 1;
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else
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host->brs_received = 1;
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spin_unlock_irqrestore(&host->dma_lock, flags);
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if (done)
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mmc_omap_xfer_done(host, data);
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}
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static void
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mmc_omap_dma_timer(unsigned long data)
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{
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struct mmc_omap_host *host = (struct mmc_omap_host *) data;
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BUG_ON(host->dma_ch < 0);
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omap_free_dma(host->dma_ch);
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host->dma_ch = -1;
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}
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static void
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mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
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{
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unsigned long flags;
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int done;
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done = 0;
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spin_lock_irqsave(&host->dma_lock, flags);
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if (host->brs_received)
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done = 1;
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else
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host->dma_done = 1;
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spin_unlock_irqrestore(&host->dma_lock, flags);
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if (done)
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mmc_omap_xfer_done(host, data);
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}
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static void
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mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
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{
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host->cmd = NULL;
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136) {
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/* response type 2 */
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cmd->resp[3] =
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OMAP_MMC_READ(host->base, RSP0) |
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(OMAP_MMC_READ(host->base, RSP1) << 16);
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cmd->resp[2] =
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OMAP_MMC_READ(host->base, RSP2) |
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(OMAP_MMC_READ(host->base, RSP3) << 16);
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cmd->resp[1] =
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OMAP_MMC_READ(host->base, RSP4) |
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(OMAP_MMC_READ(host->base, RSP5) << 16);
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cmd->resp[0] =
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OMAP_MMC_READ(host->base, RSP6) |
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(OMAP_MMC_READ(host->base, RSP7) << 16);
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} else {
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/* response types 1, 1b, 3, 4, 5, 6 */
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cmd->resp[0] =
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OMAP_MMC_READ(host->base, RSP6) |
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(OMAP_MMC_READ(host->base, RSP7) << 16);
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}
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}
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if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
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host->mrq = NULL;
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clk_disable(host->fclk);
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mmc_request_done(host->mmc, cmd->mrq);
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}
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}
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/* PIO only */
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static void
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mmc_omap_sg_to_buf(struct mmc_omap_host *host)
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{
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struct scatterlist *sg;
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sg = host->data->sg + host->sg_idx;
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host->buffer_bytes_left = sg->length;
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host->buffer = page_address(sg->page) + sg->offset;
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if (host->buffer_bytes_left > host->total_bytes_left)
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host->buffer_bytes_left = host->total_bytes_left;
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}
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/* PIO only */
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static void
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mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
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{
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int n;
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if (host->buffer_bytes_left == 0) {
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host->sg_idx++;
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BUG_ON(host->sg_idx == host->sg_len);
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mmc_omap_sg_to_buf(host);
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}
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n = 64;
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if (n > host->buffer_bytes_left)
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n = host->buffer_bytes_left;
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host->buffer_bytes_left -= n;
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host->total_bytes_left -= n;
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host->data->bytes_xfered += n;
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if (write) {
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__raw_writesw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
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} else {
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__raw_readsw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
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}
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}
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static inline void mmc_omap_report_irq(u16 status)
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{
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static const char *mmc_omap_status_bits[] = {
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"EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
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"CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
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};
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int i, c = 0;
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for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
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if (status & (1 << i)) {
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if (c)
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printk(" ");
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printk("%s", mmc_omap_status_bits[i]);
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c++;
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}
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}
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static irqreturn_t mmc_omap_irq(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
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u16 status;
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int end_command;
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int end_transfer;
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int transfer_error;
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if (host->cmd == NULL && host->data == NULL) {
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status = OMAP_MMC_READ(host->base, STAT);
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dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
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if (status != 0) {
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OMAP_MMC_WRITE(host->base, STAT, status);
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OMAP_MMC_WRITE(host->base, IE, 0);
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}
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return IRQ_HANDLED;
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}
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end_command = 0;
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end_transfer = 0;
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transfer_error = 0;
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while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) {
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OMAP_MMC_WRITE(host->base, STAT, status);
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#ifdef CONFIG_MMC_DEBUG
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dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
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status, host->cmd != NULL ? host->cmd->opcode : -1);
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mmc_omap_report_irq(status);
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printk("\n");
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#endif
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if (host->total_bytes_left) {
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if ((status & OMAP_MMC_STAT_A_FULL) ||
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(status & OMAP_MMC_STAT_END_OF_DATA))
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mmc_omap_xfer_data(host, 0);
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if (status & OMAP_MMC_STAT_A_EMPTY)
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mmc_omap_xfer_data(host, 1);
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}
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if (status & OMAP_MMC_STAT_END_OF_DATA) {
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end_transfer = 1;
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}
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if (status & OMAP_MMC_STAT_DATA_TOUT) {
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dev_dbg(mmc_dev(host->mmc), "data timeout\n");
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if (host->data) {
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host->data->error |= MMC_ERR_TIMEOUT;
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transfer_error = 1;
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}
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}
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if (status & OMAP_MMC_STAT_DATA_CRC) {
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if (host->data) {
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host->data->error |= MMC_ERR_BADCRC;
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dev_dbg(mmc_dev(host->mmc),
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"data CRC error, bytes left %d\n",
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host->total_bytes_left);
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transfer_error = 1;
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} else {
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dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
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}
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}
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if (status & OMAP_MMC_STAT_CMD_TOUT) {
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/* Timeouts are routine with some commands */
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if (host->cmd) {
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if (host->cmd->opcode != MMC_ALL_SEND_CID &&
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host->cmd->opcode !=
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MMC_SEND_OP_COND &&
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host->cmd->opcode !=
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MMC_APP_CMD &&
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!mmc_omap_cover_is_open(host))
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dev_err(mmc_dev(host->mmc),
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"command timeout, CMD %d\n",
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host->cmd->opcode);
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host->cmd->error = MMC_ERR_TIMEOUT;
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end_command = 1;
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}
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}
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if (status & OMAP_MMC_STAT_CMD_CRC) {
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if (host->cmd) {
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dev_err(mmc_dev(host->mmc),
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"command CRC error (CMD%d, arg 0x%08x)\n",
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host->cmd->opcode, host->cmd->arg);
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host->cmd->error = MMC_ERR_BADCRC;
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end_command = 1;
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} else
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dev_err(mmc_dev(host->mmc),
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"command CRC error without cmd?\n");
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}
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if (status & OMAP_MMC_STAT_CARD_ERR) {
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if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
|
|
u32 response = OMAP_MMC_READ(host->base, RSP6)
|
|
| (OMAP_MMC_READ(host->base, RSP7) << 16);
|
|
/* STOP sometimes sets must-ignore bits */
|
|
if (!(response & (R1_CC_ERROR
|
|
| R1_ILLEGAL_COMMAND
|
|
| R1_COM_CRC_ERROR))) {
|
|
end_command = 1;
|
|
continue;
|
|
}
|
|
}
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
|
|
host->cmd->opcode);
|
|
if (host->cmd) {
|
|
host->cmd->error = MMC_ERR_FAILED;
|
|
end_command = 1;
|
|
}
|
|
if (host->data) {
|
|
host->data->error = MMC_ERR_FAILED;
|
|
transfer_error = 1;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* NOTE: On 1610 the END_OF_CMD may come too early when
|
|
* starting a write
|
|
*/
|
|
if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
|
|
(!(status & OMAP_MMC_STAT_A_EMPTY))) {
|
|
end_command = 1;
|
|
}
|
|
}
|
|
|
|
if (end_command) {
|
|
mmc_omap_cmd_done(host, host->cmd);
|
|
}
|
|
if (transfer_error)
|
|
mmc_omap_xfer_done(host, host->data);
|
|
else if (end_transfer)
|
|
mmc_omap_end_of_data(host, host->data);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
|
|
|
|
schedule_work(&host->switch_work);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void mmc_omap_switch_timer(unsigned long arg)
|
|
{
|
|
struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
|
|
|
|
schedule_work(&host->switch_work);
|
|
}
|
|
|
|
/* FIXME: Handle card insertion and removal properly. Maybe use a mask
|
|
* for MMC state? */
|
|
static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
|
|
{
|
|
}
|
|
|
|
static void mmc_omap_switch_handler(void *data)
|
|
{
|
|
struct mmc_omap_host *host = (struct mmc_omap_host *) data;
|
|
struct mmc_card *card;
|
|
static int complained = 0;
|
|
int cards = 0, cover_open;
|
|
|
|
if (host->switch_pin == -1)
|
|
return;
|
|
cover_open = mmc_omap_cover_is_open(host);
|
|
if (cover_open != host->switch_last_state) {
|
|
kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
|
|
host->switch_last_state = cover_open;
|
|
}
|
|
mmc_detect_change(host->mmc, 0);
|
|
list_for_each_entry(card, &host->mmc->cards, node) {
|
|
if (mmc_card_present(card))
|
|
cards++;
|
|
}
|
|
if (mmc_omap_cover_is_open(host)) {
|
|
if (!complained) {
|
|
dev_info(mmc_dev(host->mmc), "cover is open");
|
|
complained = 1;
|
|
}
|
|
if (mmc_omap_enable_poll)
|
|
mod_timer(&host->switch_timer, jiffies +
|
|
msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
|
|
} else {
|
|
complained = 0;
|
|
}
|
|
}
|
|
|
|
/* Prepare to transfer the next segment of a scatterlist */
|
|
static void
|
|
mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
|
|
{
|
|
int dma_ch = host->dma_ch;
|
|
unsigned long data_addr;
|
|
u16 buf, frame;
|
|
u32 count;
|
|
struct scatterlist *sg = &data->sg[host->sg_idx];
|
|
int src_port = 0;
|
|
int dst_port = 0;
|
|
int sync_dev = 0;
|
|
|
|
data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA;
|
|
frame = data->blksz;
|
|
count = sg_dma_len(sg);
|
|
|
|
if ((data->blocks == 1) && (count > data->blksz))
|
|
count = frame;
|
|
|
|
host->dma_len = count;
|
|
|
|
/* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
|
|
* Use 16 or 32 word frames when the blocksize is at least that large.
|
|
* Blocksize is usually 512 bytes; but not for some SD reads.
|
|
*/
|
|
if (cpu_is_omap15xx() && frame > 32)
|
|
frame = 32;
|
|
else if (frame > 64)
|
|
frame = 64;
|
|
count /= frame;
|
|
frame >>= 1;
|
|
|
|
if (!(data->flags & MMC_DATA_WRITE)) {
|
|
buf = 0x800f | ((frame - 1) << 8);
|
|
|
|
if (cpu_class_is_omap1()) {
|
|
src_port = OMAP_DMA_PORT_TIPB;
|
|
dst_port = OMAP_DMA_PORT_EMIFF;
|
|
}
|
|
if (cpu_is_omap24xx())
|
|
sync_dev = OMAP24XX_DMA_MMC1_RX;
|
|
|
|
omap_set_dma_src_params(dma_ch, src_port,
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
data_addr, 0, 0);
|
|
omap_set_dma_dest_params(dma_ch, dst_port,
|
|
OMAP_DMA_AMODE_POST_INC,
|
|
sg_dma_address(sg), 0, 0);
|
|
omap_set_dma_dest_data_pack(dma_ch, 1);
|
|
omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
|
|
} else {
|
|
buf = 0x0f80 | ((frame - 1) << 0);
|
|
|
|
if (cpu_class_is_omap1()) {
|
|
src_port = OMAP_DMA_PORT_EMIFF;
|
|
dst_port = OMAP_DMA_PORT_TIPB;
|
|
}
|
|
if (cpu_is_omap24xx())
|
|
sync_dev = OMAP24XX_DMA_MMC1_TX;
|
|
|
|
omap_set_dma_dest_params(dma_ch, dst_port,
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
data_addr, 0, 0);
|
|
omap_set_dma_src_params(dma_ch, src_port,
|
|
OMAP_DMA_AMODE_POST_INC,
|
|
sg_dma_address(sg), 0, 0);
|
|
omap_set_dma_src_data_pack(dma_ch, 1);
|
|
omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
|
|
}
|
|
|
|
/* Max limit for DMA frame count is 0xffff */
|
|
if (unlikely(count > 0xffff))
|
|
BUG();
|
|
|
|
OMAP_MMC_WRITE(host->base, BUF, buf);
|
|
omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
|
|
frame, count, OMAP_DMA_SYNC_FRAME,
|
|
sync_dev, 0);
|
|
}
|
|
|
|
/* A scatterlist segment completed */
|
|
static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
|
|
{
|
|
struct mmc_omap_host *host = (struct mmc_omap_host *) data;
|
|
struct mmc_data *mmcdat = host->data;
|
|
|
|
if (unlikely(host->dma_ch < 0)) {
|
|
dev_err(mmc_dev(host->mmc),
|
|
"DMA callback while DMA not enabled\n");
|
|
return;
|
|
}
|
|
/* FIXME: We really should do something to _handle_ the errors */
|
|
if (ch_status & OMAP1_DMA_TOUT_IRQ) {
|
|
dev_err(mmc_dev(host->mmc),"DMA timeout\n");
|
|
return;
|
|
}
|
|
if (ch_status & OMAP_DMA_DROP_IRQ) {
|
|
dev_err(mmc_dev(host->mmc), "DMA sync error\n");
|
|
return;
|
|
}
|
|
if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
|
|
return;
|
|
}
|
|
mmcdat->bytes_xfered += host->dma_len;
|
|
host->sg_idx++;
|
|
if (host->sg_idx < host->sg_len) {
|
|
mmc_omap_prepare_dma(host, host->data);
|
|
omap_start_dma(host->dma_ch);
|
|
} else
|
|
mmc_omap_dma_done(host, host->data);
|
|
}
|
|
|
|
static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
|
|
{
|
|
const char *dev_name;
|
|
int sync_dev, dma_ch, is_read, r;
|
|
|
|
is_read = !(data->flags & MMC_DATA_WRITE);
|
|
del_timer_sync(&host->dma_timer);
|
|
if (host->dma_ch >= 0) {
|
|
if (is_read == host->dma_is_read)
|
|
return 0;
|
|
omap_free_dma(host->dma_ch);
|
|
host->dma_ch = -1;
|
|
}
|
|
|
|
if (is_read) {
|
|
if (host->id == 1) {
|
|
sync_dev = OMAP_DMA_MMC_RX;
|
|
dev_name = "MMC1 read";
|
|
} else {
|
|
sync_dev = OMAP_DMA_MMC2_RX;
|
|
dev_name = "MMC2 read";
|
|
}
|
|
} else {
|
|
if (host->id == 1) {
|
|
sync_dev = OMAP_DMA_MMC_TX;
|
|
dev_name = "MMC1 write";
|
|
} else {
|
|
sync_dev = OMAP_DMA_MMC2_TX;
|
|
dev_name = "MMC2 write";
|
|
}
|
|
}
|
|
r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
|
|
host, &dma_ch);
|
|
if (r != 0) {
|
|
dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
|
|
return r;
|
|
}
|
|
host->dma_ch = dma_ch;
|
|
host->dma_is_read = is_read;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
|
|
{
|
|
u16 reg;
|
|
|
|
reg = OMAP_MMC_READ(host->base, SDIO);
|
|
reg &= ~(1 << 5);
|
|
OMAP_MMC_WRITE(host->base, SDIO, reg);
|
|
/* Set maximum timeout */
|
|
OMAP_MMC_WRITE(host->base, CTO, 0xff);
|
|
}
|
|
|
|
static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
|
|
{
|
|
int timeout;
|
|
u16 reg;
|
|
|
|
/* Convert ns to clock cycles by assuming 20MHz frequency
|
|
* 1 cycle at 20MHz = 500 ns
|
|
*/
|
|
timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
|
|
|
|
/* Check if we need to use timeout multiplier register */
|
|
reg = OMAP_MMC_READ(host->base, SDIO);
|
|
if (timeout > 0xffff) {
|
|
reg |= (1 << 5);
|
|
timeout /= 1024;
|
|
} else
|
|
reg &= ~(1 << 5);
|
|
OMAP_MMC_WRITE(host->base, SDIO, reg);
|
|
OMAP_MMC_WRITE(host->base, DTO, timeout);
|
|
}
|
|
|
|
static void
|
|
mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
|
|
{
|
|
struct mmc_data *data = req->data;
|
|
int i, use_dma, block_size;
|
|
unsigned sg_len;
|
|
|
|
host->data = data;
|
|
if (data == NULL) {
|
|
OMAP_MMC_WRITE(host->base, BLEN, 0);
|
|
OMAP_MMC_WRITE(host->base, NBLK, 0);
|
|
OMAP_MMC_WRITE(host->base, BUF, 0);
|
|
host->dma_in_use = 0;
|
|
set_cmd_timeout(host, req);
|
|
return;
|
|
}
|
|
|
|
|
|
block_size = data->blksz;
|
|
|
|
OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
|
|
OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
|
|
set_data_timeout(host, req);
|
|
|
|
/* cope with calling layer confusion; it issues "single
|
|
* block" writes using multi-block scatterlists.
|
|
*/
|
|
sg_len = (data->blocks == 1) ? 1 : data->sg_len;
|
|
|
|
/* Only do DMA for entire blocks */
|
|
use_dma = host->use_dma;
|
|
if (use_dma) {
|
|
for (i = 0; i < sg_len; i++) {
|
|
if ((data->sg[i].length % block_size) != 0) {
|
|
use_dma = 0;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
host->sg_idx = 0;
|
|
if (use_dma) {
|
|
if (mmc_omap_get_dma_channel(host, data) == 0) {
|
|
enum dma_data_direction dma_data_dir;
|
|
|
|
if (data->flags & MMC_DATA_WRITE)
|
|
dma_data_dir = DMA_TO_DEVICE;
|
|
else
|
|
dma_data_dir = DMA_FROM_DEVICE;
|
|
|
|
host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
|
|
sg_len, dma_data_dir);
|
|
host->total_bytes_left = 0;
|
|
mmc_omap_prepare_dma(host, req->data);
|
|
host->brs_received = 0;
|
|
host->dma_done = 0;
|
|
host->dma_in_use = 1;
|
|
} else
|
|
use_dma = 0;
|
|
}
|
|
|
|
/* Revert to PIO? */
|
|
if (!use_dma) {
|
|
OMAP_MMC_WRITE(host->base, BUF, 0x1f1f);
|
|
host->total_bytes_left = data->blocks * block_size;
|
|
host->sg_len = sg_len;
|
|
mmc_omap_sg_to_buf(host);
|
|
host->dma_in_use = 0;
|
|
}
|
|
}
|
|
|
|
static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
|
|
{
|
|
struct mmc_omap_host *host = mmc_priv(mmc);
|
|
|
|
WARN_ON(host->mrq != NULL);
|
|
|
|
host->mrq = req;
|
|
|
|
/* only touch fifo AFTER the controller readies it */
|
|
mmc_omap_prepare_data(host, req);
|
|
mmc_omap_start_command(host, req->cmd);
|
|
if (host->dma_in_use)
|
|
omap_start_dma(host->dma_ch);
|
|
}
|
|
|
|
static void innovator_fpga_socket_power(int on)
|
|
{
|
|
#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
|
|
|
|
if (on) {
|
|
fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
|
|
OMAP1510_FPGA_POWER);
|
|
} else {
|
|
fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
|
|
OMAP1510_FPGA_POWER);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Turn the socket power on/off. Innovator uses FPGA, most boards
|
|
* probably use GPIO.
|
|
*/
|
|
static void mmc_omap_power(struct mmc_omap_host *host, int on)
|
|
{
|
|
if (on) {
|
|
if (machine_is_omap_innovator())
|
|
innovator_fpga_socket_power(1);
|
|
else if (machine_is_omap_h2())
|
|
tps65010_set_gpio_out_value(GPIO3, HIGH);
|
|
else if (machine_is_omap_h3())
|
|
/* GPIO 4 of TPS65010 sends SD_EN signal */
|
|
tps65010_set_gpio_out_value(GPIO4, HIGH);
|
|
else if (cpu_is_omap24xx()) {
|
|
u16 reg = OMAP_MMC_READ(host->base, CON);
|
|
OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11));
|
|
} else
|
|
if (host->power_pin >= 0)
|
|
omap_set_gpio_dataout(host->power_pin, 1);
|
|
} else {
|
|
if (machine_is_omap_innovator())
|
|
innovator_fpga_socket_power(0);
|
|
else if (machine_is_omap_h2())
|
|
tps65010_set_gpio_out_value(GPIO3, LOW);
|
|
else if (machine_is_omap_h3())
|
|
tps65010_set_gpio_out_value(GPIO4, LOW);
|
|
else if (cpu_is_omap24xx()) {
|
|
u16 reg = OMAP_MMC_READ(host->base, CON);
|
|
OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11));
|
|
} else
|
|
if (host->power_pin >= 0)
|
|
omap_set_gpio_dataout(host->power_pin, 0);
|
|
}
|
|
}
|
|
|
|
static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct mmc_omap_host *host = mmc_priv(mmc);
|
|
int dsor;
|
|
int realclock, i;
|
|
|
|
realclock = ios->clock;
|
|
|
|
if (ios->clock == 0)
|
|
dsor = 0;
|
|
else {
|
|
int func_clk_rate = clk_get_rate(host->fclk);
|
|
|
|
dsor = func_clk_rate / realclock;
|
|
if (dsor < 1)
|
|
dsor = 1;
|
|
|
|
if (func_clk_rate / dsor > realclock)
|
|
dsor++;
|
|
|
|
if (dsor > 250)
|
|
dsor = 250;
|
|
dsor++;
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
dsor |= 1 << 15;
|
|
}
|
|
|
|
switch (ios->power_mode) {
|
|
case MMC_POWER_OFF:
|
|
mmc_omap_power(host, 0);
|
|
break;
|
|
case MMC_POWER_UP:
|
|
case MMC_POWER_ON:
|
|
mmc_omap_power(host, 1);
|
|
dsor |= 1<<11;
|
|
break;
|
|
}
|
|
|
|
host->bus_mode = ios->bus_mode;
|
|
host->hw_bus_mode = host->bus_mode;
|
|
|
|
clk_enable(host->fclk);
|
|
|
|
/* On insanely high arm_per frequencies something sometimes
|
|
* goes somehow out of sync, and the POW bit is not being set,
|
|
* which results in the while loop below getting stuck.
|
|
* Writing to the CON register twice seems to do the trick. */
|
|
for (i = 0; i < 2; i++)
|
|
OMAP_MMC_WRITE(host->base, CON, dsor);
|
|
if (ios->power_mode == MMC_POWER_UP) {
|
|
/* Send clock cycles, poll completion */
|
|
OMAP_MMC_WRITE(host->base, IE, 0);
|
|
OMAP_MMC_WRITE(host->base, STAT, 0xffff);
|
|
OMAP_MMC_WRITE(host->base, CMD, 1<<7);
|
|
while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
|
|
OMAP_MMC_WRITE(host->base, STAT, 1);
|
|
}
|
|
clk_disable(host->fclk);
|
|
}
|
|
|
|
static int mmc_omap_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct mmc_omap_host *host = mmc_priv(mmc);
|
|
|
|
return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
|
|
}
|
|
|
|
static struct mmc_host_ops mmc_omap_ops = {
|
|
.request = mmc_omap_request,
|
|
.set_ios = mmc_omap_set_ios,
|
|
.get_ro = mmc_omap_get_ro,
|
|
};
|
|
|
|
static int __init mmc_omap_probe(struct platform_device *pdev)
|
|
{
|
|
struct omap_mmc_conf *minfo = pdev->dev.platform_data;
|
|
struct mmc_host *mmc;
|
|
struct mmc_omap_host *host = NULL;
|
|
struct resource *r;
|
|
int ret = 0;
|
|
int irq;
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!r || irq < 0)
|
|
return -ENXIO;
|
|
|
|
r = request_mem_region(pdev->resource[0].start,
|
|
pdev->resource[0].end - pdev->resource[0].start + 1,
|
|
pdev->name);
|
|
if (!r)
|
|
return -EBUSY;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
|
|
if (!mmc) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
|
|
spin_lock_init(&host->dma_lock);
|
|
init_timer(&host->dma_timer);
|
|
host->dma_timer.function = mmc_omap_dma_timer;
|
|
host->dma_timer.data = (unsigned long) host;
|
|
|
|
host->id = pdev->id;
|
|
host->res = r;
|
|
host->irq = irq;
|
|
|
|
if (cpu_is_omap24xx()) {
|
|
host->iclk = clk_get(&pdev->dev, "mmc_ick");
|
|
if (IS_ERR(host->iclk))
|
|
goto out;
|
|
clk_enable(host->iclk);
|
|
}
|
|
|
|
if (!cpu_is_omap24xx())
|
|
host->fclk = clk_get(&pdev->dev, "mmc_ck");
|
|
else
|
|
host->fclk = clk_get(&pdev->dev, "mmc_fck");
|
|
|
|
if (IS_ERR(host->fclk)) {
|
|
ret = PTR_ERR(host->fclk);
|
|
goto out;
|
|
}
|
|
|
|
/* REVISIT:
|
|
* Also, use minfo->cover to decide how to manage
|
|
* the card detect sensing.
|
|
*/
|
|
host->power_pin = minfo->power_pin;
|
|
host->switch_pin = minfo->switch_pin;
|
|
host->wp_pin = minfo->wp_pin;
|
|
host->use_dma = 1;
|
|
host->dma_ch = -1;
|
|
|
|
host->irq = pdev->resource[1].start;
|
|
host->base = (void __iomem*)IO_ADDRESS(r->start);
|
|
|
|
if (minfo->wire4)
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
|
|
mmc->ops = &mmc_omap_ops;
|
|
mmc->f_min = 400000;
|
|
mmc->f_max = 24000000;
|
|
mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
|
|
|
|
/* Use scatterlist DMA to reduce per-transfer costs.
|
|
* NOTE max_seg_size assumption that small blocks aren't
|
|
* normally used (except e.g. for reading SD registers).
|
|
*/
|
|
mmc->max_phys_segs = 32;
|
|
mmc->max_hw_segs = 32;
|
|
mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
|
|
mmc->max_seg_size = mmc->max_sectors * 512;
|
|
|
|
if (host->power_pin >= 0) {
|
|
if ((ret = omap_request_gpio(host->power_pin)) != 0) {
|
|
dev_err(mmc_dev(host->mmc),
|
|
"Unable to get GPIO pin for MMC power\n");
|
|
goto out;
|
|
}
|
|
omap_set_gpio_direction(host->power_pin, 0);
|
|
}
|
|
|
|
ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
|
|
if (ret)
|
|
goto out;
|
|
|
|
host->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
if (host->switch_pin >= 0) {
|
|
INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
|
|
init_timer(&host->switch_timer);
|
|
host->switch_timer.function = mmc_omap_switch_timer;
|
|
host->switch_timer.data = (unsigned long) host;
|
|
if (omap_request_gpio(host->switch_pin) != 0) {
|
|
dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
|
|
host->switch_pin = -1;
|
|
goto no_switch;
|
|
}
|
|
|
|
omap_set_gpio_direction(host->switch_pin, 1);
|
|
ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
|
|
mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
|
|
if (ret) {
|
|
dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
|
|
omap_free_gpio(host->switch_pin);
|
|
host->switch_pin = -1;
|
|
goto no_switch;
|
|
}
|
|
ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
|
|
if (ret == 0) {
|
|
ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
|
|
if (ret != 0)
|
|
device_remove_file(&pdev->dev, &dev_attr_cover_switch);
|
|
}
|
|
if (ret) {
|
|
dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
|
|
free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
|
|
omap_free_gpio(host->switch_pin);
|
|
host->switch_pin = -1;
|
|
goto no_switch;
|
|
}
|
|
if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
|
|
schedule_work(&host->switch_work);
|
|
}
|
|
|
|
no_switch:
|
|
return 0;
|
|
|
|
out:
|
|
/* FIXME: Free other resources too. */
|
|
if (host) {
|
|
if (host->iclk && !IS_ERR(host->iclk))
|
|
clk_put(host->iclk);
|
|
if (host->fclk && !IS_ERR(host->fclk))
|
|
clk_put(host->fclk);
|
|
mmc_free_host(host->mmc);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int mmc_omap_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_omap_host *host = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (host) {
|
|
mmc_remove_host(host->mmc);
|
|
free_irq(host->irq, host);
|
|
|
|
if (host->power_pin >= 0)
|
|
omap_free_gpio(host->power_pin);
|
|
if (host->switch_pin >= 0) {
|
|
device_remove_file(&pdev->dev, &dev_attr_enable_poll);
|
|
device_remove_file(&pdev->dev, &dev_attr_cover_switch);
|
|
free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
|
|
omap_free_gpio(host->switch_pin);
|
|
host->switch_pin = -1;
|
|
del_timer_sync(&host->switch_timer);
|
|
flush_scheduled_work();
|
|
}
|
|
if (host->iclk && !IS_ERR(host->iclk))
|
|
clk_put(host->iclk);
|
|
if (host->fclk && !IS_ERR(host->fclk))
|
|
clk_put(host->fclk);
|
|
mmc_free_host(host->mmc);
|
|
}
|
|
|
|
release_mem_region(pdev->resource[0].start,
|
|
pdev->resource[0].end - pdev->resource[0].start + 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
{
|
|
int ret = 0;
|
|
struct mmc_omap_host *host = platform_get_drvdata(pdev);
|
|
|
|
if (host && host->suspended)
|
|
return 0;
|
|
|
|
if (host) {
|
|
ret = mmc_suspend_host(host->mmc, mesg);
|
|
if (ret == 0)
|
|
host->suspended = 1;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int mmc_omap_resume(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
struct mmc_omap_host *host = platform_get_drvdata(pdev);
|
|
|
|
if (host && !host->suspended)
|
|
return 0;
|
|
|
|
if (host) {
|
|
ret = mmc_resume_host(host->mmc);
|
|
if (ret == 0)
|
|
host->suspended = 0;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define mmc_omap_suspend NULL
|
|
#define mmc_omap_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver mmc_omap_driver = {
|
|
.probe = mmc_omap_probe,
|
|
.remove = mmc_omap_remove,
|
|
.suspend = mmc_omap_suspend,
|
|
.resume = mmc_omap_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init mmc_omap_init(void)
|
|
{
|
|
return platform_driver_register(&mmc_omap_driver);
|
|
}
|
|
|
|
static void __exit mmc_omap_exit(void)
|
|
{
|
|
platform_driver_unregister(&mmc_omap_driver);
|
|
}
|
|
|
|
module_init(mmc_omap_init);
|
|
module_exit(mmc_omap_exit);
|
|
|
|
MODULE_DESCRIPTION("OMAP Multimedia Card driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS(DRIVER_NAME);
|
|
MODULE_AUTHOR("Juha Yrjölä");
|