![Avi Kivity](/assets/img/avatar_default.png)
This paves the way for multiple architecture support. Note that while ioapic.c could potentially be shared with ia64, it is also moved. Signed-off-by: Avi Kivity <avi@qumranet.com>
451 lines
9.6 KiB
C
451 lines
9.6 KiB
C
/*
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* 8259 interrupt controller emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2007 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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* Authors:
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* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
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* Port from Qemu.
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*/
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#include <linux/mm.h>
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#include "irq.h"
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#include <linux/kvm_host.h>
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/*
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* set irq level. If an edge is detected, then the IRR is set to 1
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*/
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static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
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{
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int mask;
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mask = 1 << irq;
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if (s->elcr & mask) /* level triggered */
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if (level) {
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s->irr |= mask;
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s->last_irr |= mask;
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} else {
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s->irr &= ~mask;
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s->last_irr &= ~mask;
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}
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else /* edge triggered */
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if (level) {
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if ((s->last_irr & mask) == 0)
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s->irr |= mask;
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s->last_irr |= mask;
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} else
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s->last_irr &= ~mask;
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}
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/*
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* return the highest priority found in mask (highest = smallest
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* number). Return 8 if no irq
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*/
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static inline int get_priority(struct kvm_kpic_state *s, int mask)
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{
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int priority;
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if (mask == 0)
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return 8;
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priority = 0;
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while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
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priority++;
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return priority;
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}
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/*
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* return the pic wanted interrupt. return -1 if none
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*/
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static int pic_get_irq(struct kvm_kpic_state *s)
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{
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int mask, cur_priority, priority;
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mask = s->irr & ~s->imr;
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priority = get_priority(s, mask);
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if (priority == 8)
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return -1;
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/*
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* compute current priority. If special fully nested mode on the
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* master, the IRQ coming from the slave is not taken into account
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* for the priority computation.
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*/
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mask = s->isr;
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if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
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mask &= ~(1 << 2);
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cur_priority = get_priority(s, mask);
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if (priority < cur_priority)
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/*
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* higher priority found: an irq should be generated
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*/
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return (priority + s->priority_add) & 7;
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else
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return -1;
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}
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/*
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* raise irq to CPU if necessary. must be called every time the active
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* irq may change
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*/
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static void pic_update_irq(struct kvm_pic *s)
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{
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int irq2, irq;
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irq2 = pic_get_irq(&s->pics[1]);
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if (irq2 >= 0) {
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/*
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* if irq request by slave pic, signal master PIC
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*/
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pic_set_irq1(&s->pics[0], 2, 1);
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pic_set_irq1(&s->pics[0], 2, 0);
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}
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irq = pic_get_irq(&s->pics[0]);
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if (irq >= 0)
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s->irq_request(s->irq_request_opaque, 1);
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else
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s->irq_request(s->irq_request_opaque, 0);
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}
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void kvm_pic_update_irq(struct kvm_pic *s)
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{
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pic_update_irq(s);
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}
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void kvm_pic_set_irq(void *opaque, int irq, int level)
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{
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struct kvm_pic *s = opaque;
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pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
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pic_update_irq(s);
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}
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/*
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* acknowledge interrupt 'irq'
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*/
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static inline void pic_intack(struct kvm_kpic_state *s, int irq)
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{
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if (s->auto_eoi) {
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if (s->rotate_on_auto_eoi)
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s->priority_add = (irq + 1) & 7;
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} else
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s->isr |= (1 << irq);
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/*
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* We don't clear a level sensitive interrupt here
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*/
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if (!(s->elcr & (1 << irq)))
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s->irr &= ~(1 << irq);
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}
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int kvm_pic_read_irq(struct kvm_pic *s)
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{
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int irq, irq2, intno;
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irq = pic_get_irq(&s->pics[0]);
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if (irq >= 0) {
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pic_intack(&s->pics[0], irq);
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if (irq == 2) {
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irq2 = pic_get_irq(&s->pics[1]);
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if (irq2 >= 0)
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pic_intack(&s->pics[1], irq2);
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else
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/*
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* spurious IRQ on slave controller
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*/
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irq2 = 7;
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intno = s->pics[1].irq_base + irq2;
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irq = irq2 + 8;
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} else
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intno = s->pics[0].irq_base + irq;
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} else {
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/*
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* spurious IRQ on host controller
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*/
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irq = 7;
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intno = s->pics[0].irq_base + irq;
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}
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pic_update_irq(s);
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return intno;
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}
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void kvm_pic_reset(struct kvm_kpic_state *s)
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{
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s->last_irr = 0;
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s->irr = 0;
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s->imr = 0;
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s->isr = 0;
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s->priority_add = 0;
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s->irq_base = 0;
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s->read_reg_select = 0;
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s->poll = 0;
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s->special_mask = 0;
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s->init_state = 0;
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s->auto_eoi = 0;
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s->rotate_on_auto_eoi = 0;
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s->special_fully_nested_mode = 0;
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s->init4 = 0;
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}
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static void pic_ioport_write(void *opaque, u32 addr, u32 val)
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{
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struct kvm_kpic_state *s = opaque;
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int priority, cmd, irq;
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addr &= 1;
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if (addr == 0) {
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if (val & 0x10) {
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kvm_pic_reset(s); /* init */
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/*
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* deassert a pending interrupt
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*/
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s->pics_state->irq_request(s->pics_state->
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irq_request_opaque, 0);
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s->init_state = 1;
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s->init4 = val & 1;
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if (val & 0x02)
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printk(KERN_ERR "single mode not supported");
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if (val & 0x08)
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printk(KERN_ERR
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"level sensitive irq not supported");
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} else if (val & 0x08) {
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if (val & 0x04)
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s->poll = 1;
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if (val & 0x02)
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s->read_reg_select = val & 1;
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if (val & 0x40)
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s->special_mask = (val >> 5) & 1;
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} else {
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cmd = val >> 5;
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switch (cmd) {
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case 0:
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case 4:
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s->rotate_on_auto_eoi = cmd >> 2;
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break;
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case 1: /* end of interrupt */
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case 5:
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priority = get_priority(s, s->isr);
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if (priority != 8) {
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irq = (priority + s->priority_add) & 7;
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s->isr &= ~(1 << irq);
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if (cmd == 5)
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s->priority_add = (irq + 1) & 7;
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pic_update_irq(s->pics_state);
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}
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break;
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case 3:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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pic_update_irq(s->pics_state);
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break;
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case 6:
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s->priority_add = (val + 1) & 7;
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pic_update_irq(s->pics_state);
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break;
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case 7:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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s->priority_add = (irq + 1) & 7;
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pic_update_irq(s->pics_state);
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break;
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default:
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break; /* no operation */
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}
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}
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} else
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switch (s->init_state) {
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case 0: /* normal mode */
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s->imr = val;
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pic_update_irq(s->pics_state);
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break;
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case 1:
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s->irq_base = val & 0xf8;
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s->init_state = 2;
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break;
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case 2:
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if (s->init4)
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s->init_state = 3;
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else
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s->init_state = 0;
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break;
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case 3:
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s->special_fully_nested_mode = (val >> 4) & 1;
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s->auto_eoi = (val >> 1) & 1;
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s->init_state = 0;
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break;
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}
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}
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static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
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{
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int ret;
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ret = pic_get_irq(s);
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if (ret >= 0) {
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if (addr1 >> 7) {
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s->pics_state->pics[0].isr &= ~(1 << 2);
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s->pics_state->pics[0].irr &= ~(1 << 2);
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}
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s->irr &= ~(1 << ret);
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s->isr &= ~(1 << ret);
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if (addr1 >> 7 || ret != 2)
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pic_update_irq(s->pics_state);
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} else {
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ret = 0x07;
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pic_update_irq(s->pics_state);
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}
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return ret;
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}
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static u32 pic_ioport_read(void *opaque, u32 addr1)
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{
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struct kvm_kpic_state *s = opaque;
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unsigned int addr;
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int ret;
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addr = addr1;
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addr &= 1;
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if (s->poll) {
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ret = pic_poll_read(s, addr1);
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s->poll = 0;
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} else
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if (addr == 0)
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if (s->read_reg_select)
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ret = s->isr;
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else
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ret = s->irr;
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else
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ret = s->imr;
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return ret;
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}
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static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
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{
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struct kvm_kpic_state *s = opaque;
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s->elcr = val & s->elcr_mask;
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}
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static u32 elcr_ioport_read(void *opaque, u32 addr1)
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{
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struct kvm_kpic_state *s = opaque;
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return s->elcr;
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}
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static int picdev_in_range(struct kvm_io_device *this, gpa_t addr)
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{
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switch (addr) {
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case 0x20:
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case 0x21:
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case 0xa0:
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case 0xa1:
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case 0x4d0:
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case 0x4d1:
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return 1;
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default:
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return 0;
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}
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}
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static void picdev_write(struct kvm_io_device *this,
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gpa_t addr, int len, const void *val)
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{
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struct kvm_pic *s = this->private;
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unsigned char data = *(unsigned char *)val;
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if (len != 1) {
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if (printk_ratelimit())
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printk(KERN_ERR "PIC: non byte write\n");
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return;
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}
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switch (addr) {
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case 0x20:
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case 0x21:
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case 0xa0:
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case 0xa1:
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pic_ioport_write(&s->pics[addr >> 7], addr, data);
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break;
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case 0x4d0:
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case 0x4d1:
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elcr_ioport_write(&s->pics[addr & 1], addr, data);
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break;
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}
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}
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static void picdev_read(struct kvm_io_device *this,
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gpa_t addr, int len, void *val)
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{
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struct kvm_pic *s = this->private;
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unsigned char data = 0;
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if (len != 1) {
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if (printk_ratelimit())
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printk(KERN_ERR "PIC: non byte read\n");
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return;
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}
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switch (addr) {
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case 0x20:
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case 0x21:
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case 0xa0:
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case 0xa1:
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data = pic_ioport_read(&s->pics[addr >> 7], addr);
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break;
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case 0x4d0:
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case 0x4d1:
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data = elcr_ioport_read(&s->pics[addr & 1], addr);
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break;
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}
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*(unsigned char *)val = data;
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}
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/*
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* callback when PIC0 irq status changed
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*/
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static void pic_irq_request(void *opaque, int level)
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{
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struct kvm *kvm = opaque;
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struct kvm_vcpu *vcpu = kvm->vcpus[0];
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pic_irqchip(kvm)->output = level;
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if (vcpu)
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kvm_vcpu_kick(vcpu);
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}
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struct kvm_pic *kvm_create_pic(struct kvm *kvm)
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{
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struct kvm_pic *s;
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s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
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if (!s)
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return NULL;
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s->pics[0].elcr_mask = 0xf8;
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s->pics[1].elcr_mask = 0xde;
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s->irq_request = pic_irq_request;
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s->irq_request_opaque = kvm;
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s->pics[0].pics_state = s;
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s->pics[1].pics_state = s;
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/*
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* Initialize PIO device
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*/
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s->dev.read = picdev_read;
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s->dev.write = picdev_write;
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s->dev.in_range = picdev_in_range;
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s->dev.private = s;
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kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
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return s;
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}
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