![Yinghai Lu](/assets/img/avatar_default.png)
make known_pat_cpu to think amd k8 and fam10h is ok too. also make tom2 below to be WRBACK Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
847 lines
23 KiB
C
847 lines
23 KiB
C
/* Generic MTRR (Memory Type Range Register) driver.
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Copyright (C) 1997-2000 Richard Gooch
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Copyright (c) 2002 Patrick Mochel
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with this library; if not, write to the Free
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Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Richard Gooch may be reached by email at rgooch@atnf.csiro.au
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The postal address is:
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Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
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Source: "Pentium Pro Family Developer's Manual, Volume 3:
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Operating System Writer's Guide" (Intel document number 242692),
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section 11.11.7
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This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
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on 6-7 March 2002.
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Source: Intel Architecture Software Developers Manual, Volume 3:
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System Programming Guide; Section 9.11. (1997 edition - PPro).
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/mutex.h>
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#include <asm/e820.h>
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#include <asm/mtrr.h>
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#include <asm/uaccess.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/kvm_para.h>
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#include "mtrr.h"
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u32 num_var_ranges = 0;
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unsigned int mtrr_usage_table[MAX_VAR_RANGES];
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static DEFINE_MUTEX(mtrr_mutex);
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u64 size_or_mask, size_and_mask;
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static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {};
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struct mtrr_ops * mtrr_if = NULL;
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static void set_mtrr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type);
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void set_mtrr_ops(struct mtrr_ops * ops)
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{
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if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
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mtrr_ops[ops->vendor] = ops;
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}
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/* Returns non-zero if we have the write-combining memory type */
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static int have_wrcomb(void)
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{
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struct pci_dev *dev;
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u8 rev;
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if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
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/* ServerWorks LE chipsets < rev 6 have problems with write-combining
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Don't allow it and leave room for other chipsets to be tagged */
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if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
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dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
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pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
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if (rev <= 5) {
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printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
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pci_dev_put(dev);
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return 0;
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}
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}
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/* Intel 450NX errata # 23. Non ascending cacheline evictions to
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write combining memory may resulting in data corruption */
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if (dev->vendor == PCI_VENDOR_ID_INTEL &&
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dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
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printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
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pci_dev_put(dev);
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return 0;
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}
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pci_dev_put(dev);
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}
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return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
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}
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/* This function returns the number of variable MTRRs */
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static void __init set_num_var_ranges(void)
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{
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unsigned long config = 0, dummy;
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if (use_intel()) {
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rdmsr(MTRRcap_MSR, config, dummy);
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} else if (is_cpu(AMD))
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config = 2;
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else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
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config = 8;
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num_var_ranges = config & 0xff;
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}
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static void __init init_table(void)
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{
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int i, max;
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max = num_var_ranges;
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for (i = 0; i < max; i++)
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mtrr_usage_table[i] = 1;
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}
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struct set_mtrr_data {
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atomic_t count;
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atomic_t gate;
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unsigned long smp_base;
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unsigned long smp_size;
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unsigned int smp_reg;
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mtrr_type smp_type;
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};
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static void ipi_handler(void *info)
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/* [SUMMARY] Synchronisation handler. Executed by "other" CPUs.
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[RETURNS] Nothing.
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*/
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{
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#ifdef CONFIG_SMP
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struct set_mtrr_data *data = info;
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unsigned long flags;
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local_irq_save(flags);
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atomic_dec(&data->count);
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while(!atomic_read(&data->gate))
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cpu_relax();
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/* The master has cleared me to execute */
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if (data->smp_reg != ~0U)
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mtrr_if->set(data->smp_reg, data->smp_base,
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data->smp_size, data->smp_type);
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else
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mtrr_if->set_all();
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atomic_dec(&data->count);
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while(atomic_read(&data->gate))
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cpu_relax();
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atomic_dec(&data->count);
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local_irq_restore(flags);
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#endif
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}
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static inline int types_compatible(mtrr_type type1, mtrr_type type2) {
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return type1 == MTRR_TYPE_UNCACHABLE ||
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type2 == MTRR_TYPE_UNCACHABLE ||
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(type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
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(type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
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}
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/**
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* set_mtrr - update mtrrs on all processors
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* @reg: mtrr in question
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* @base: mtrr base
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* @size: mtrr size
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* @type: mtrr type
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*
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* This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
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*
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* 1. Send IPI to do the following:
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* 2. Disable Interrupts
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* 3. Wait for all procs to do so
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* 4. Enter no-fill cache mode
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* 5. Flush caches
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* 6. Clear PGE bit
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* 7. Flush all TLBs
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* 8. Disable all range registers
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* 9. Update the MTRRs
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* 10. Enable all range registers
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* 11. Flush all TLBs and caches again
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* 12. Enter normal cache mode and reenable caching
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* 13. Set PGE
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* 14. Wait for buddies to catch up
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* 15. Enable interrupts.
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*
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* What does that mean for us? Well, first we set data.count to the number
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* of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait
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* until it hits 0 and proceed. We set the data.gate flag and reset data.count.
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* Meanwhile, they are waiting for that flag to be set. Once it's set, each
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* CPU goes through the transition of updating MTRRs. The CPU vendors may each do it
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* differently, so we call mtrr_if->set() callback and let them take care of it.
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* When they're done, they again decrement data->count and wait for data.gate to
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* be reset.
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* When we finish, we wait for data.count to hit 0 and toggle the data.gate flag.
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* Everyone then enables interrupts and we all continue on.
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*
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* Note that the mechanism is the same for UP systems, too; all the SMP stuff
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* becomes nops.
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*/
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static void set_mtrr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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{
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struct set_mtrr_data data;
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unsigned long flags;
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data.smp_reg = reg;
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data.smp_base = base;
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data.smp_size = size;
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data.smp_type = type;
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atomic_set(&data.count, num_booting_cpus() - 1);
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/* make sure data.count is visible before unleashing other CPUs */
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smp_wmb();
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atomic_set(&data.gate,0);
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/* Start the ball rolling on other CPUs */
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if (smp_call_function(ipi_handler, &data, 1, 0) != 0)
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panic("mtrr: timed out waiting for other CPUs\n");
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local_irq_save(flags);
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while(atomic_read(&data.count))
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cpu_relax();
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/* ok, reset count and toggle gate */
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atomic_set(&data.count, num_booting_cpus() - 1);
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smp_wmb();
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atomic_set(&data.gate,1);
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/* do our MTRR business */
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/* HACK!
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* We use this same function to initialize the mtrrs on boot.
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* The state of the boot cpu's mtrrs has been saved, and we want
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* to replicate across all the APs.
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* If we're doing that @reg is set to something special...
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*/
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if (reg != ~0U)
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mtrr_if->set(reg,base,size,type);
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/* wait for the others */
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while(atomic_read(&data.count))
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cpu_relax();
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atomic_set(&data.count, num_booting_cpus() - 1);
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smp_wmb();
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atomic_set(&data.gate,0);
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/*
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* Wait here for everyone to have seen the gate change
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* So we're the last ones to touch 'data'
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*/
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while(atomic_read(&data.count))
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cpu_relax();
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local_irq_restore(flags);
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}
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/**
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* mtrr_add_page - Add a memory type region
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* @base: Physical base address of region in pages (in units of 4 kB!)
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* @size: Physical size of region in pages (4 kB)
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* @type: Type of MTRR desired
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* @increment: If this is true do usage counting on the region
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*
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* Memory type region registers control the caching on newer Intel and
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* non Intel processors. This function allows drivers to request an
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* MTRR is added. The details and hardware specifics of each processor's
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* implementation are hidden from the caller, but nevertheless the
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* caller should expect to need to provide a power of two size on an
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* equivalent power of two boundary.
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*
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* If the region cannot be added either because all regions are in use
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* or the CPU cannot support it a negative value is returned. On success
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* the register number for this entry is returned, but should be treated
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* as a cookie only.
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*
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* On a multiprocessor machine the changes are made to all processors.
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* This is required on x86 by the Intel processors.
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*
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* The available types are
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*
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* %MTRR_TYPE_UNCACHABLE - No caching
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*
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* %MTRR_TYPE_WRBACK - Write data back in bursts whenever
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*
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* %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
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*
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* %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
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*
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* BUGS: Needs a quiet flag for the cases where drivers do not mind
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* failures and do not wish system log messages to be sent.
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*/
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int mtrr_add_page(unsigned long base, unsigned long size,
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unsigned int type, bool increment)
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{
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int i, replace, error;
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mtrr_type ltype;
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unsigned long lbase, lsize;
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if (!mtrr_if)
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return -ENXIO;
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if ((error = mtrr_if->validate_add_page(base,size,type)))
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return error;
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if (type >= MTRR_NUM_TYPES) {
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printk(KERN_WARNING "mtrr: type: %u invalid\n", type);
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return -EINVAL;
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}
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/* If the type is WC, check that this processor supports it */
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if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
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printk(KERN_WARNING
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"mtrr: your processor doesn't support write-combining\n");
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return -ENOSYS;
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}
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if (!size) {
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printk(KERN_WARNING "mtrr: zero sized request\n");
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return -EINVAL;
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}
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if (base & size_or_mask || size & size_or_mask) {
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printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n");
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return -EINVAL;
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}
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error = -EINVAL;
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replace = -1;
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/* No CPU hotplug when we change MTRR entries */
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get_online_cpus();
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/* Search for existing MTRR */
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mutex_lock(&mtrr_mutex);
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for (i = 0; i < num_var_ranges; ++i) {
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase)
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continue;
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/* At this point we know there is some kind of overlap/enclosure */
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if (base < lbase || base + size - 1 > lbase + lsize - 1) {
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if (base <= lbase && base + size - 1 >= lbase + lsize - 1) {
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/* New region encloses an existing region */
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if (type == ltype) {
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replace = replace == -1 ? i : -2;
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continue;
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}
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else if (types_compatible(type, ltype))
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continue;
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}
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printk(KERN_WARNING
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"mtrr: 0x%lx000,0x%lx000 overlaps existing"
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" 0x%lx000,0x%lx000\n", base, size, lbase,
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lsize);
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goto out;
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}
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/* New region is enclosed by an existing region */
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if (ltype != type) {
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if (types_compatible(type, ltype))
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continue;
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printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
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base, size, mtrr_attrib_to_str(ltype),
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mtrr_attrib_to_str(type));
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goto out;
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}
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if (increment)
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++mtrr_usage_table[i];
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error = i;
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goto out;
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}
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/* Search for an empty MTRR */
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i = mtrr_if->get_free_region(base, size, replace);
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if (i >= 0) {
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set_mtrr(i, base, size, type);
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if (likely(replace < 0)) {
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mtrr_usage_table[i] = 1;
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} else {
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mtrr_usage_table[i] = mtrr_usage_table[replace];
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if (increment)
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mtrr_usage_table[i]++;
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if (unlikely(replace != i)) {
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set_mtrr(replace, 0, 0, 0);
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mtrr_usage_table[replace] = 0;
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}
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}
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} else
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printk(KERN_INFO "mtrr: no more MTRRs available\n");
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error = i;
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out:
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mutex_unlock(&mtrr_mutex);
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put_online_cpus();
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return error;
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}
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static int mtrr_check(unsigned long base, unsigned long size)
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{
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if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
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printk(KERN_WARNING
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"mtrr: size and base must be multiples of 4 kiB\n");
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printk(KERN_DEBUG
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"mtrr: size: 0x%lx base: 0x%lx\n", size, base);
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dump_stack();
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return -1;
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}
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return 0;
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}
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/**
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* mtrr_add - Add a memory type region
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* @base: Physical base address of region
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* @size: Physical size of region
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* @type: Type of MTRR desired
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* @increment: If this is true do usage counting on the region
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*
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* Memory type region registers control the caching on newer Intel and
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* non Intel processors. This function allows drivers to request an
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* MTRR is added. The details and hardware specifics of each processor's
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* implementation are hidden from the caller, but nevertheless the
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* caller should expect to need to provide a power of two size on an
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* equivalent power of two boundary.
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*
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* If the region cannot be added either because all regions are in use
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* or the CPU cannot support it a negative value is returned. On success
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* the register number for this entry is returned, but should be treated
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* as a cookie only.
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*
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* On a multiprocessor machine the changes are made to all processors.
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* This is required on x86 by the Intel processors.
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*
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* The available types are
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*
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* %MTRR_TYPE_UNCACHABLE - No caching
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*
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* %MTRR_TYPE_WRBACK - Write data back in bursts whenever
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*
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* %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
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*
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* %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
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*
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* BUGS: Needs a quiet flag for the cases where drivers do not mind
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* failures and do not wish system log messages to be sent.
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*/
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int
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mtrr_add(unsigned long base, unsigned long size, unsigned int type,
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bool increment)
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{
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if (mtrr_check(base, size))
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return -EINVAL;
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return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
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increment);
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}
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/**
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* mtrr_del_page - delete a memory type region
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* @reg: Register returned by mtrr_add
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* @base: Physical base address
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* @size: Size of region
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*
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* If register is supplied then base and size are ignored. This is
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* how drivers should call it.
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*
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* Releases an MTRR region. If the usage count drops to zero the
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* register is freed and the region returns to default state.
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* On success the register is returned, on failure a negative error
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* code.
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*/
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int mtrr_del_page(int reg, unsigned long base, unsigned long size)
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{
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int i, max;
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mtrr_type ltype;
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unsigned long lbase, lsize;
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int error = -EINVAL;
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if (!mtrr_if)
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return -ENXIO;
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max = num_var_ranges;
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/* No CPU hotplug when we change MTRR entries */
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get_online_cpus();
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mutex_lock(&mtrr_mutex);
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if (reg < 0) {
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/* Search for existing MTRR */
|
|
for (i = 0; i < max; ++i) {
|
|
mtrr_if->get(i, &lbase, &lsize, <ype);
|
|
if (lbase == base && lsize == size) {
|
|
reg = i;
|
|
break;
|
|
}
|
|
}
|
|
if (reg < 0) {
|
|
printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
|
|
size);
|
|
goto out;
|
|
}
|
|
}
|
|
if (reg >= max) {
|
|
printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
|
|
goto out;
|
|
}
|
|
mtrr_if->get(reg, &lbase, &lsize, <ype);
|
|
if (lsize < 1) {
|
|
printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
|
|
goto out;
|
|
}
|
|
if (mtrr_usage_table[reg] < 1) {
|
|
printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
|
|
goto out;
|
|
}
|
|
if (--mtrr_usage_table[reg] < 1)
|
|
set_mtrr(reg, 0, 0, 0);
|
|
error = reg;
|
|
out:
|
|
mutex_unlock(&mtrr_mutex);
|
|
put_online_cpus();
|
|
return error;
|
|
}
|
|
/**
|
|
* mtrr_del - delete a memory type region
|
|
* @reg: Register returned by mtrr_add
|
|
* @base: Physical base address
|
|
* @size: Size of region
|
|
*
|
|
* If register is supplied then base and size are ignored. This is
|
|
* how drivers should call it.
|
|
*
|
|
* Releases an MTRR region. If the usage count drops to zero the
|
|
* register is freed and the region returns to default state.
|
|
* On success the register is returned, on failure a negative error
|
|
* code.
|
|
*/
|
|
|
|
int
|
|
mtrr_del(int reg, unsigned long base, unsigned long size)
|
|
{
|
|
if (mtrr_check(base, size))
|
|
return -EINVAL;
|
|
return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
|
|
}
|
|
|
|
EXPORT_SYMBOL(mtrr_add);
|
|
EXPORT_SYMBOL(mtrr_del);
|
|
|
|
/* HACK ALERT!
|
|
* These should be called implicitly, but we can't yet until all the initcall
|
|
* stuff is done...
|
|
*/
|
|
static void __init init_ifs(void)
|
|
{
|
|
#ifndef CONFIG_X86_64
|
|
amd_init_mtrr();
|
|
cyrix_init_mtrr();
|
|
centaur_init_mtrr();
|
|
#endif
|
|
}
|
|
|
|
/* The suspend/resume methods are only for CPU without MTRR. CPU using generic
|
|
* MTRR driver doesn't require this
|
|
*/
|
|
struct mtrr_value {
|
|
mtrr_type ltype;
|
|
unsigned long lbase;
|
|
unsigned long lsize;
|
|
};
|
|
|
|
static struct mtrr_value mtrr_state[MAX_VAR_RANGES];
|
|
|
|
static int mtrr_save(struct sys_device * sysdev, pm_message_t state)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < num_var_ranges; i++) {
|
|
mtrr_if->get(i,
|
|
&mtrr_state[i].lbase,
|
|
&mtrr_state[i].lsize,
|
|
&mtrr_state[i].ltype);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int mtrr_restore(struct sys_device * sysdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < num_var_ranges; i++) {
|
|
if (mtrr_state[i].lsize)
|
|
set_mtrr(i,
|
|
mtrr_state[i].lbase,
|
|
mtrr_state[i].lsize,
|
|
mtrr_state[i].ltype);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
static struct sysdev_driver mtrr_sysdev_driver = {
|
|
.suspend = mtrr_save,
|
|
.resume = mtrr_restore,
|
|
};
|
|
|
|
static int disable_mtrr_trim;
|
|
|
|
static int __init disable_mtrr_trim_setup(char *str)
|
|
{
|
|
disable_mtrr_trim = 1;
|
|
return 0;
|
|
}
|
|
early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
|
|
|
|
/*
|
|
* Newer AMD K8s and later CPUs have a special magic MSR way to force WB
|
|
* for memory >4GB. Check for that here.
|
|
* Note this won't check if the MTRRs < 4GB where the magic bit doesn't
|
|
* apply to are wrong, but so far we don't know of any such case in the wild.
|
|
*/
|
|
#define Tom2Enabled (1U << 21)
|
|
#define Tom2ForceMemTypeWB (1U << 22)
|
|
|
|
int __init amd_special_default_mtrr(void)
|
|
{
|
|
u32 l, h;
|
|
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
|
|
return 0;
|
|
if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
|
|
return 0;
|
|
/* In case some hypervisor doesn't pass SYSCFG through */
|
|
if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
|
|
return 0;
|
|
/*
|
|
* Memory between 4GB and top of mem is forced WB by this magic bit.
|
|
* Reserved before K8RevF, but should be zero there.
|
|
*/
|
|
if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) ==
|
|
(Tom2Enabled | Tom2ForceMemTypeWB))
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mtrr_trim_uncached_memory - trim RAM not covered by MTRRs
|
|
* @end_pfn: ending page frame number
|
|
*
|
|
* Some buggy BIOSes don't setup the MTRRs properly for systems with certain
|
|
* memory configurations. This routine checks that the highest MTRR matches
|
|
* the end of memory, to make sure the MTRRs having a write back type cover
|
|
* all of the memory the kernel is intending to use. If not, it'll trim any
|
|
* memory off the end by adjusting end_pfn, removing it from the kernel's
|
|
* allocation pools, warning the user with an obnoxious message.
|
|
*/
|
|
int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
|
|
{
|
|
unsigned long i, base, size, highest_pfn = 0, def, dummy;
|
|
mtrr_type type;
|
|
u64 trim_start, trim_size;
|
|
|
|
/*
|
|
* Make sure we only trim uncachable memory on machines that
|
|
* support the Intel MTRR architecture:
|
|
*/
|
|
if (!is_cpu(INTEL) || disable_mtrr_trim)
|
|
return 0;
|
|
rdmsr(MTRRdefType_MSR, def, dummy);
|
|
def &= 0xff;
|
|
if (def != MTRR_TYPE_UNCACHABLE)
|
|
return 0;
|
|
|
|
if (amd_special_default_mtrr())
|
|
return 0;
|
|
|
|
/* Find highest cached pfn */
|
|
for (i = 0; i < num_var_ranges; i++) {
|
|
mtrr_if->get(i, &base, &size, &type);
|
|
if (type != MTRR_TYPE_WRBACK)
|
|
continue;
|
|
if (highest_pfn < base + size)
|
|
highest_pfn = base + size;
|
|
}
|
|
|
|
/* kvm/qemu doesn't have mtrr set right, don't trim them all */
|
|
if (!highest_pfn) {
|
|
if (!kvm_para_available()) {
|
|
printk(KERN_WARNING
|
|
"WARNING: strange, CPU MTRRs all blank?\n");
|
|
WARN_ON(1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
if (highest_pfn < end_pfn) {
|
|
printk(KERN_WARNING "WARNING: BIOS bug: CPU MTRRs don't cover"
|
|
" all of memory, losing %luMB of RAM.\n",
|
|
(end_pfn - highest_pfn) >> (20 - PAGE_SHIFT));
|
|
|
|
WARN_ON(1);
|
|
|
|
printk(KERN_INFO "update e820 for mtrr\n");
|
|
trim_start = highest_pfn;
|
|
trim_start <<= PAGE_SHIFT;
|
|
trim_size = end_pfn;
|
|
trim_size <<= PAGE_SHIFT;
|
|
trim_size -= trim_start;
|
|
update_memory_range(trim_start, trim_size, E820_RAM,
|
|
E820_RESERVED);
|
|
update_e820();
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mtrr_bp_init - initialize mtrrs on the boot CPU
|
|
*
|
|
* This needs to be called early; before any of the other CPUs are
|
|
* initialized (i.e. before smp_init()).
|
|
*
|
|
*/
|
|
void __init mtrr_bp_init(void)
|
|
{
|
|
init_ifs();
|
|
|
|
if (cpu_has_mtrr) {
|
|
mtrr_if = &generic_mtrr_ops;
|
|
size_or_mask = 0xff000000; /* 36 bits */
|
|
size_and_mask = 0x00f00000;
|
|
|
|
/* This is an AMD specific MSR, but we assume(hope?) that
|
|
Intel will implement it to when they extend the address
|
|
bus of the Xeon. */
|
|
if (cpuid_eax(0x80000000) >= 0x80000008) {
|
|
u32 phys_addr;
|
|
phys_addr = cpuid_eax(0x80000008) & 0xff;
|
|
/* CPUID workaround for Intel 0F33/0F34 CPU */
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
|
|
boot_cpu_data.x86 == 0xF &&
|
|
boot_cpu_data.x86_model == 0x3 &&
|
|
(boot_cpu_data.x86_mask == 0x3 ||
|
|
boot_cpu_data.x86_mask == 0x4))
|
|
phys_addr = 36;
|
|
|
|
size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
|
|
size_and_mask = ~size_or_mask & 0xfffff00000ULL;
|
|
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
|
|
boot_cpu_data.x86 == 6) {
|
|
/* VIA C* family have Intel style MTRRs, but
|
|
don't support PAE */
|
|
size_or_mask = 0xfff00000; /* 32 bits */
|
|
size_and_mask = 0;
|
|
}
|
|
} else {
|
|
switch (boot_cpu_data.x86_vendor) {
|
|
case X86_VENDOR_AMD:
|
|
if (cpu_has_k6_mtrr) {
|
|
/* Pre-Athlon (K6) AMD CPU MTRRs */
|
|
mtrr_if = mtrr_ops[X86_VENDOR_AMD];
|
|
size_or_mask = 0xfff00000; /* 32 bits */
|
|
size_and_mask = 0;
|
|
}
|
|
break;
|
|
case X86_VENDOR_CENTAUR:
|
|
if (cpu_has_centaur_mcr) {
|
|
mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
|
|
size_or_mask = 0xfff00000; /* 32 bits */
|
|
size_and_mask = 0;
|
|
}
|
|
break;
|
|
case X86_VENDOR_CYRIX:
|
|
if (cpu_has_cyrix_arr) {
|
|
mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
|
|
size_or_mask = 0xfff00000; /* 32 bits */
|
|
size_and_mask = 0;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (mtrr_if) {
|
|
set_num_var_ranges();
|
|
init_table();
|
|
if (use_intel())
|
|
get_mtrr_state();
|
|
}
|
|
}
|
|
|
|
void mtrr_ap_init(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
if (!mtrr_if || !use_intel())
|
|
return;
|
|
/*
|
|
* Ideally we should hold mtrr_mutex here to avoid mtrr entries changed,
|
|
* but this routine will be called in cpu boot time, holding the lock
|
|
* breaks it. This routine is called in two cases: 1.very earily time
|
|
* of software resume, when there absolutely isn't mtrr entry changes;
|
|
* 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to
|
|
* prevent mtrr entry changes
|
|
*/
|
|
local_irq_save(flags);
|
|
|
|
mtrr_if->set_all();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/**
|
|
* Save current fixed-range MTRR state of the BSP
|
|
*/
|
|
void mtrr_save_state(void)
|
|
{
|
|
smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1, 1);
|
|
}
|
|
|
|
static int __init mtrr_init_finialize(void)
|
|
{
|
|
if (!mtrr_if)
|
|
return 0;
|
|
if (use_intel())
|
|
mtrr_state_warn();
|
|
else {
|
|
/* The CPUs haven't MTRR and seem to not support SMP. They have
|
|
* specific drivers, we use a tricky method to support
|
|
* suspend/resume for them.
|
|
* TBD: is there any system with such CPU which supports
|
|
* suspend/resume? if no, we should remove the code.
|
|
*/
|
|
sysdev_driver_register(&cpu_sysdev_class,
|
|
&mtrr_sysdev_driver);
|
|
}
|
|
return 0;
|
|
}
|
|
subsys_initcall(mtrr_init_finialize);
|